Commit Graph

375474 Commits

Author SHA1 Message Date
Steven J. Hill 0131f2b2c9 MIPS: microMIPS: Optimise 'strncpy' core library function.
Optimise 'strncpy' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Steven J. Hill 26c5e07d14 MIPS: microMIPS: Optimise 'memset' core library function.
Optimise 'memset' to use microMIPS instructions and/or optimisations
for binary size reduction. When the microMIPS ISA is not being used,
the library function compiles to the original binary code.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Steven J. Hill bce860833a MIPS: microMIPS: Add configuration option for microMIPS kernel.
This adds the option to build the Linux kernel using only the
microMIPS ISA. The resulting kernel binary is, at a minimum,
20% smaller than using the MIPS32R2 ISA.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Steven J. Hill 1658f914ff MIPS: microMIPS: Disable LL/SC and fix linker bug.
Partially revert commit e0c14a260d66ba35935600d6435940a566fe806b
and turn off LL/SC when building a pure microMIPS kernel. This is
a temporary fix until the cmpxchg assembly macro functions are
re-written to not use the HI/LO registers in address calculations.

Also add .insn in selected user access functions which would
otherwise produce ISA mode jump incompatibilities. This is also a
temporary fix.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Douglas Leung 01be057b33 MIPS: microMIPS: Add vdso support.
Support vdso in microMIPS mode.

Signed-off-by: Douglas Leung <Douglas.Leung@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:19 +02:00
Leonid Yegoshin 34c2f668d0 MIPS: microMIPS: Add unaligned access support.
Add logic needed to handle unaligned accesses in microMIPS mode.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
2013-05-09 17:55:19 +02:00
Leonid Yegoshin fb6883e580 MIPS: microMIPS: Support handling of delay slots.
Add logic needed to properly calculate exceptions for delay slots
when in microMIPS mode.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Steven J. Hill 2a0b24f56c MIPS: microMIPS: Add support for exception handling.
All exceptions must be taken in microMIPS mode, never in classic
MIPS mode or the kernel falls apart. A few NOP instructions are
used to maintain the correct alignment of microMIPS versions of
the exception vectors.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Leonid Yegoshin 102cedc32a MIPS: microMIPS: Floating point support.
Add logic needed to do floating point emulation in microMIPS mode.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Steven J. Hill <Steven. Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Steven J. Hill cf6d905828 MIPS: microMIPS: Fix macro naming in micro-assembler.
The macros did not properly take into account the ISA that
the kernel was being compiled with. A classic MIPS kernel
will have the standard 'uasm_i_##op' macro functions with
'MM_uasm_i_##op' macro functions for the microMIPS version.
A pure microMIPS kernel will have the standard macros with
'CL_uasm_i_##op' macro functions for the classic version.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Steven J. Hill 8fe4bb98e4 MIPS: microMIPS: Fix incorrect mask for jump immediate.
Jump or branch target addresses have the first bit set. The
original mask did not take this into account and will cause
a field overflow warning for the target address when a jump
immediate instruction is built.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-05-09 17:55:18 +02:00
Sanjay Lal 50c8308538 KVM/MIPS32: Binary patching of select privileged instructions.
Currently, the following instructions are translated:
- CACHE (indexed)
- CACHE (va based): translated to a SYNCI, overkill on D-CACHE operations,
  but still much faster than a trap.
- mfc0/mtc0: the virtual COP0 registers for the guest are implemented as
  2-D array.
  [COP#][SEL] and this is mapped into the guest kernel address space @ VA 0x0.
  mfc0/mtc0 operations are transformed to load/stores.

Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-09 17:48:22 +02:00
Sanjay Lal 2f4d9b5442 KVM/MIPS32: Do not call vcpu_load when injecting interrupts.
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-09 17:48:22 +02:00
Steven Rostedt (Red Hat) 7c088b5120 ftrace: Have ftrace_regex_write() return either read or error
As ftrace_regex_write() reads the result of ftrace_process_regex()
which can sometimes return a positive number, only consider a
failure if the return is negative. Otherwise, it will skip possible
other registered probes and by returning a positive number that
wasn't read, it will confuse the user processes doing the writing.

Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2013-05-09 11:35:12 -04:00
Steven Rostedt (Red Hat) ff305ded9f tracing: Return error if register_ftrace_function_probe() fails for event_enable_func()
register_ftrace_function_probe() returns the number of functions
it registered, which can be zero, it can also return a negative number
if something went wrong. But event_enable_func() only checks for
the case that it didn't register anything, it needs to also check
for the case that something went wrong and return that error code
as well.

Added some comments about the code as well, to make it more
understandable.

Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2013-05-09 11:30:26 -04:00
Masami Hiramatsu a5b85bd155 tracing: Don't succeed if event_enable_func did not register anything
Return 0 instead of the number of activated ftrace function probes if
event_enable_func succeeded and return an error code if it failed or
did not register any functions. But it currently returns the number
of registered functions and if it didn't register anything, it returns 0,
but that is considered success.

This also fixes the return value. As if it succeeds, it returns the
number of functions that were enabled, which is returned back to
the user in ftrace_regex_write (the write() return code). If only
one function is enabled, then the return code of the write is one,
and this can confuse the user program in thinking it only wrote 1
byte.

Link: http://lkml.kernel.org/r/20130509054413.30398.55650.stgit@mhiramat-M0-7522

Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Tom Zanussi <tom.zanussi@intel.com>
Signed-off-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
[ Rewrote change log to reflect that this fixes two bugs - SR ]
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
2013-05-09 11:26:01 -04:00
Srivatsa S. Bhat c8c64d165c EDAC: Don't give write permission to read-only files
I get the following warning on boot:

------------[ cut here ]------------
WARNING: at drivers/base/core.c:575 device_create_file+0x9a/0xa0()
Hardware name:  -[8737R2A]-
Write permission without 'store'
...
</snip>

Drilling down, this is related to dynamic channel ce_count attribute
files sporting a S_IWUSR mode without a ->store() function. Looking
around, it appears that they aren't supposed to have a ->store()
function. So remove the bogus write permission to get rid of the
warning.

Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
Cc: Mauro Carvalho Chehab <mchehab@redhat.com>
Cc: <stable@vger.kernel.org> # 3.[89]
[ shorten commit message ]
Signed-off-by: Borislav Petkov <bp@suse.de>
2013-05-09 12:40:45 +02:00
Steven Miao 5ae89ee043 bfin cache: dcplb map: add 16M dcplb map for BF60x
use 16M data cplb map on BF60x to avoid too much dcplb miss overhead
cleanup cplb info

Signed-off-by: Steven Miao <realmz6@gmail.com>
2013-05-09 18:22:45 +08:00
Paolo Bonzini 326f578f7e KVM: emulator: emulate SALC
This is an almost-undocumented instruction available in 32-bit mode.
I say "almost" undocumented because AMD documents it in their opcode
maps just to say that it is unavailable in 64-bit mode (sections
"A.2.1 One-Byte Opcodes" and "B.3 Invalid and Reassigned Instructions
in 64-Bit Mode").

It is roughly equivalent to "sbb %al, %al" except it does not
set the flags.  Use fastop to emulate it, but do not use the opcode
directly because it would fail if the host is 64-bit!

Reported-by: Jun'ichi Nomura <j-nomura@ce.jp.nec.com>
Cc: stable@vger.kernel.org # 3.9
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-05-09 13:15:08 +03:00
Paolo Bonzini 7fa57952d7 KVM: emulator: emulate XLAT
This is used by SGABIOS, KVM breaks with emulate_invalid_guest_state=1.
It is just a MOV in disguise, with a funny source address.

Reported-by: Jun'ichi Nomura <j-nomura@ce.jp.nec.com>
Cc: stable@vger.kernel.org # 3.9
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-05-09 13:14:51 +03:00
Paolo Bonzini a035d5c64d KVM: emulator: emulate AAM
This is used by SGABIOS, KVM breaks with emulate_invalid_guest_state=1.

AAM needs the source operand to be unsigned; do the same in AAD as well
for consistency, even though it does not affect the result.

Reported-by: Jun'ichi Nomura <j-nomura@ce.jp.nec.com>
Cc: stable@vger.kernel.org # 3.9
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
2013-05-09 13:12:58 +03:00
Vineet Gupta a690984d60 ARC: [mm] refactor the core (i|d)cache line ops loops
Nothing semantical
* simplify the alignement code by using & operation only
* rename variables clearly as paddr

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-09 14:18:50 +05:30
Michal Simek a047775e7e microblaze: Enable IRQ in arch_cpu_idle
Microblaze requires to enable IRQ in cpu_idle loop.

It should be the part of this patch:
"microblaze: Use generic idle loop"
(sha1: e962bb9e9c)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 10:46:16 +02:00
Vineet Gupta c917a36f5f ARC: [mm] serious bug in vaddr based icache flush
vaddr used to index the cache was clipped from the wrong end, and thus
would potentially fail to flush the correct lines.

The problem was dorment for so long because up until the recent
optimizations it was only used for ptrace break-point only flushes.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-09 13:45:12 +05:30
Geert Uytterhoeven b341d84c8a xtensa: Switch to asm-generic/linkage.h
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2013-05-09 01:07:12 -07:00
Chris Zankel a078ccff56 xtensa: fix redboot load address
With the patch to support MMUv3, the base address for the loaded
binary image has changed, and a fix was applied to the U-Boot image.
This fixes the RedBoot image.

Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:12 -07:00
Max Filippov efefbcc500 xtensa: ISS: fix timer_lock usage in rs_open
This fixes the following lockdep splat:

[   66.460000] =================================
[   66.460000] [ INFO: inconsistent lock state ]
[   66.460000] 3.9.0-rc5-00161-ga48dd49 #4 Not tainted
[   66.460000] ---------------------------------
[   66.460000] inconsistent {SOFTIRQ-ON-W} -> {IN-SOFTIRQ-W} usage.
[   66.460000] swapper/1 [HC0[0]:SC1[1]:HE1:SE0] takes:
[   66.460000]  (timer_lock){+.?...}, at: [<d0006cde>] rs_poll+0x12/0xdc
[   66.460000] {SOFTIRQ-ON-W} state was registered at:
[   66.460000]   [<d00421f0>] lock_acquire+0xec/0x13c
[   66.460000]   [<d01ea036>] _raw_spin_lock+0x3a/0x84
[   66.460000]   [<d0006c8c>] rs_open+0x18/0x58
[   66.460000]   [<d0139ea2>] tty_open+0x262/0x3cc
[   66.460000]   [<d00942e0>] chrdev_open+0x8c/0xe0
[   66.460000]   [<d00907b2>] do_dentry_open$isra$16+0x10e/0x190
[   66.460000]   [<d0091141>] finish_open+0x39/0x48
[   66.460000]   [<d009a0b4>] do_last$isra$34+0x6c4/0x824
[   66.460000]   [<d009a27a>] path_openat+0x66/0x310
[   66.460000]   [<d009a53a>] do_filp_open+0x16/0x44
[   66.460000]   [<d0091445>] do_sys_open+0xd5/0x13c
[   66.460000]   [<d00914be>] sys_open+0x12/0x18
[   66.460000]   [<d0413ffc>] kernel_init_freeable+0xe4/0x12c
[   66.460000]   [<d01e2a9c>] kernel_init+0xc/0x9c
[   66.460000]   [<d00044fc>] ret_from_kernel_thread+0x8/0xc
[   66.460000] irq event stamp: 132542
[   66.460000] hardirqs last  enabled at (132542): [<d01ea2ec>] _raw_spin_unlock_irq+0x30/0x44
[   66.460000] hardirqs last disabled at (132541): [<d01ea11e>] _raw_spin_lock_irq+0xe/0x8c
[   66.460000] softirqs last  enabled at (132234): [<d0017d32>] __do_softirq+0x216/0x2a4
[   66.460000] softirqs last disabled at (132539): [<d0018024>] irq_exit+0x38/0x40
[   66.460000]
[   66.460000] other info that might help us debug this:
[   66.460000]  Possible unsafe locking scenario:
[   66.460000]
[   66.460000]        CPU0
[   66.460000]        ----
[   66.460000]   lock(timer_lock);
[   66.460000]   <Interrupt>
[   66.460000]     lock(timer_lock);
[   66.460000]
[   66.460000]  *** DEADLOCK ***
[   66.460000]
[   66.460000] 1 lock held by swapper/1:
[   66.460000]  #0:  (((&serial_timer))){+.-...}, at: [<d001c65c>] call_timer_fn+0x0/0x1f0
[   66.460000]
Stack: d7c2fac0 00000018 00000004 00000001 d7c2faa0 00000004 00000006 d7c2fa90
       9003e87c d7c2fae0 d7c30000 d025a87c 00000001 0000000f 00000000 d7c2fac0
       9004005d d7c2fb10 d7c30000 d7c30338 00000001 00000001 00000000 d7c30338
[   66.460000] Call Trace:
[   66.460000]  [<d01e4f93>] print_usage_bug$part$26+0x1c3/0x1c8
[   66.460000]  [<d003e87c>] mark_lock+0x2b4/0x440
[   66.460000]  [<d004005d>] __lock_acquire+0x54d/0x16c4
[   66.460000]  [<d00421f0>] lock_acquire+0xec/0x13c
[   66.460000]  [<d01ea036>] _raw_spin_lock+0x3a/0x84
[   66.460000]  [<d0006cde>] rs_poll+0x12/0xdc
[   66.460000]  [<d001c71a>] call_timer_fn+0xbe/0x1f0
[   66.460000]  [<d001cd90>] run_timer_softirq+0x198/0x1f4
[   66.460000]  [<d0017c30>] __do_softirq+0x114/0x2a4
[   66.460000]  [<d0018024>] irq_exit+0x38/0x40
[   66.460000]  [<d00046c0>] do_IRQ+0x44/0x48
[   66.460000]  [<d0005c58>] do_interrupt+0x4c/0x54
[   66.460000]  [<d0003c80>] common_exception_return+0x0/0x5c
[   66.460000]  [<d006682c>] free_pcppages_bulk+0x254/0x308
[   66.460000]

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov 895666a992 xtensa: disable IRQs while IRQ handler is running
IRQ handlers are expected to run with IRQs disabled.
See e.g. http://lwn.net/Articles/380931/ for a longer story.

This was overlooked in the commit
  2d1c645 xtensa: dispatch medium-priority interrupts
Revert to old behavior and simplify interrupt entry and exit code.
Interrupt handler still honours IRQ priority.

do_notify_resume/schedule must be called with interrupts enabled, enable
interrupts if we return from user exception.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov 8f371c7521 xtensa: enable lockdep support
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov 031d0112d7 xtensa: fix arch_irqs_disabled_flags implementation
IRQs are disabled when PS.EXCM is set or PS.INTLEVEL is equal to or
higher than LOCKLEVEL.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov c92931b200 xtensa: add irq flags trace support
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:11 -07:00
Max Filippov 3ae908c99e xtensa: provide custom CALLER_ADDR* implementations
Definition of CALLER_ADDR* through __builtin_return_address makes
compiler insert calls to __xtensa_libgcc_window_spill, which in turn
makes fast_syscall_spill_registers syscall that clobbers registers when
called from the kernel mode, leading to invalid opcode exceptions on
return to userspace.

Provide definition for CALLER_ADDR0 as MAKE_PC_FROM_RA(a0, a1) and in
case CONFIG_FRAME_POINTER is enabled extract CALLER_ADDR{1-3} from
stack.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov 3e4196a5cc xtensa: add stacktrace support
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov 4e96274e2b xtensa: clean up stpill_registers
- remove unused asm parameters;
- fix EXCM bit setting in the PS SR during _spill_registers call.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov f4b93ba931 xtensa: don't use a7 in simcalls
To support FRAME_POINTER avoid using a7 in __simc (none of the existing
simcalls needs it). Replace calls to __simc with more specific
simc_read, simc_write and simc_lseek calls.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov 0f7f931027 xtensa: don't attempt to use unconfigured timers
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:10 -07:00
Max Filippov b06c14e5c1 xtensa: provide default platform_pcibios_init implementation
This fixes the following build error:

  arch/xtensa/kernel/built-in.o:(.init.literal+0xe8): undefined reference
	to `platform_pcibios_init'
  arch/xtensa/kernel/built-in.o: In function `setup_arch':
  (.init.text+0x20e): undefined reference to `platform_pcibios_init'

and allows platform to omit definition of platform_pcibios_init if it's
empty.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Paul Bolle 5e44fd012b xtensa: remove KCORE_ELF again
The Kconfig symbol KCORE_ELF was removed in v2.6.0, but reappeared in two
architectures. It is useless. Remove it again.

Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Max Filippov 93e294ac99 xtensa: document MMUv3 setup sequence
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Max Filippov e85e335f8f xtensa: add MMU v3 support
MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB
way 6:

Way 6 (512 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0x00000000  0x00000000  0x01  0x03 RWX Bypass
        0x20000000  0x20000000  0x01  0x03 RWX Bypass
        0x40000000  0x40000000  0x01  0x03 RWX Bypass
        0x60000000  0x60000000  0x01  0x03 RWX Bypass
        0x80000000  0x80000000  0x01  0x03 RWX Bypass
        0xa0000000  0xa0000000  0x01  0x03 RWX Bypass
        0xc0000000  0xc0000000  0x01  0x03 RWX Bypass
        0xe0000000  0xe0000000  0x01  0x03 RWX Bypass

This patch adds remapping code at the reset vector or at the kernel
_start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that
reconfigures MMUv3 as MMUv2:

Way 5 (128 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xd0000000  0x00000000  0x01  0x07 RWX WB
        0xd8000000  0x00000000  0x01  0x03 RWX Bypass
Way 6 (256 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xe0000000  0xf0000000  0x01  0x07 RWX WB
        0xf0000000  0xf0000000  0x01  0x03 RWX Bypass

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Max Filippov d83ff0bb82 xtensa: fix ibreakenable register update
Only set the register when there is at least one ibreak register,
otherwise the build fails:
	arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable'
	for 'wsr' instruction
	arch/xtensa/platforms/iss/setup.c:67: Error: invalid register
	'ibreakenable' for 'wsr' instruction

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Max Filippov 74f5bf029e xtensa: fix oprofile building as module
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09 01:07:09 -07:00
Michal Simek f663b60f52 microblaze: Fix uaccess_ok macro
Fix access_ok macro no to permit
case where user will try to access
the last address space which is equal
to segment address.

Example:
segment addr = 0xbfff ffff
address = 0xbfff fff0
size = 0x10

Current wrong implementation
0xbfff ffff >= (0xbfff fff0 | 0x10 | (0xbfff fff0 + 0x10))
0xbfff ffff >= (0xbfff fff0        | 0xc000 0000)
0xbfff ffff >= 0xf000 0000
return 0 which is access failed even the combination is valid.
because get_fs().seq returns the last valid address.

This patch fix this problem.

Size equals to zero is valid access.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:04:32 +02:00
Michal Simek 6dc92c9c3f microblaze: Add support for new cpu versions and target architecture
Update PVR values based on reference manual.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:04:31 +02:00
Michal Simek 08aaefa0df microblaze: Do not select OPT_LIB_ASM by default
This option is valid only for BE systems.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:04:31 +02:00
Michal Simek 5eec2f0228 microblaze: Fix initrd support
Initrd/ramdisk support has been never validated.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:04:31 +02:00
Michal Simek 4323cd48a1 microblaze: Do not use r6 in head.S
r6 stores pointer to ramdisk and shouldn't
be used before it is passed to machine_early_init.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:01:21 +02:00
Michal Simek ef9cb4e19b microblaze: pci: Remove duplicated header
Remove duplicated header.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:01:21 +02:00
Dan Christensen 7c2c85137f microblaze: Set the default irq_domain
Register the irq_domain created during initialization as the default so
that device drivers can pass NULL to irq_create_mapping and get a
virtual irq to pass to request_irq.

Signed-off-by: Dan Christensen <opello@opello.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:01:21 +02:00
Wei Yongjun 995fb054eb microblaze: pci: Remove duplicated include from pci-common.c
Remove duplicated include.

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-09 09:01:21 +02:00