3 Commits

Author	SHA1	Message	Date
Sudeep Holla	7934d69abf	arm64: Add L2 cache topology to ARM Ltd boards/models ... Commit 5d425c1865 ("arm64: kernel: add support for cpu cache information") adds cacheinfo support for ARM64. Since there's no architectural way of detecting the cpus that share particular cache, device tree can be used and the core cacheinfo already supports the same. This patch adds the L2 cache topology on Juno board, FVP/RTSM and foundation models. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Liviu Dudau <Liviu.Dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2015-02-25 17:12:21 +01:00
Liviu Dudau	6bc474de36	arm64: ARM: Fix the Generic Timers interrupt active level description ... The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional description" that generic timers provide an active-LOW interrupt output. Fix the device trees to correctly describe this. While doing this update the CPU mask to match the number of described CPUs as well. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2014-11-28 22:38:14 +01:00
Robert Richter	ca5b34100c	dts, arm64: Move dts files to vendor subdirs ... Moving dts files to vendor subdirs. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Robert Richter <rrichter@cavium.com>	2014-10-21 18:06:59 +02:00