mirror of https://gitee.com/openkylin/linux.git
136 Commits
| Author | SHA1 | Message | Date |
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Linus Torvalds
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ac43507589 |
This tag contains the Linux port for C-SKY(csky) based on linux-4.19
Release, which has been through 10 rounds of review on mailing list. We almost got the Acked-by/Reviewed-by of all patches except "Process management and Signal", but all've been tested. Here is the LTP-20180118 test report: ----------------------------------------------- Total Tests: 1298 Total Skipped Tests: 281 Total Failures: 10 Kernel Version: 4.19.0+ Machine Architecture: csky Hostname: buildroot ----------------------------------------------- This patchset adds architecture support to Linux for C-SKY's 32-bit embedded There are two ABI versions with several CPU cores in this patchset: ABIv1: 610 (16-bit instruction, 32-bit data path, VIPT Cache ...) ABIv2: 807 810 860 (16/32-bit variable length instruction, PIPT Cache, SMP ...) More information: http://en.c-sky.com The development repo: https://github.com/c-sky/csky-linux ABI Documentation: https://github.com/c-sky/csky-doc Here is the pre-built cross compiler for fast test from our CI: https://gitlab.com/c-sky/buildroot/-/jobs/101608095/artifacts/file/output/images/csky_toolchain_qemu_csky_ck807f_4.18_glibc_defconfig_482b221e52908be1c9b2ccb444255e1562bb7025.tar.xz We use buildroot as our CI-test enviornment. "LTP, Lmbench ..." will be tested for every commit. See here for more details: https://gitlab.com/c-sky/buildroot/pipelines We'll continouslly improve csky subsystem in future. Changes in v10: - Remove duplicated headers in asm/Kbuild and uapi/asm/Kbuild. - Change to (__NR_arch_specific_syscall + 1) in unistd.h. - Drop dword access for get_user_size patch. - Involve the interrupt controller drivers after got Reviewed-by. Changes in v9: - Remove unused code in smp.c and use per_cpu for ipi_data. - Fixup r15 register access in abiv1/alignment.c. - Improve the changelog comment in commit-msg. Changes in v8: - Pass make allmodconfig. - Implement abiv1 get_user_dword(). - Remove set_irq_mapping() used by driver in smp.c. Changes in v7: - Use checkpatch.pl to check all patches and fixup as possible. - Remove github.com/c-sky print in bootup. - Give a return in DMA_ATTR_NON_CONSISTENT in csky_dma_alloc_atomic(). - Remove the NSIGXXX in fpu.c and use force_sig_fault() in fpu.c. - Remove irq.h and add it in asm/Kbuild. - Use byteswap helpers in abiv1/bswapXi.c. - Fixup arch_sync_dma() only with one page problem. Changes in v6: - use asm-generic/bitops/atomic.h for all in asm/bitops.h - fix flush_cache_range and tlb_start_vma - fix compile error with include linux/bug.h in cmpxchg.h - improve the comment Changes in v5: - remove redundant smp_mb operations in spinlock.h - add commit message for dt-bindings docs - add CPUHP_AP_CSKY_TIMER_STARTING in hotplug.h for csky_mptimer - add COMPILE_TEST for timer-gx6605s Kconfig - seperate csky two interrupt controllers with 2 patches - add MAINTAINERS patch for csky - move IPI_IRQ into csky_mptimer, fixup irq_mapping problem - coding convension Changes in v4: - cleanup defconfig - use ksys_ in syscall.c - remove wrong comment in vdso.c - Use GENERIC_IRQ_MULTI_HANDLER - optimize the memset.c - fixup dts warnings - remove big-endian in byteorder.h Changes in v3: dc560f1 csky: change to EM_CSKY 252 for elf.h 2ac3ddf csky: remove gx6605s.dts af00b8c csky: add defconfig and qemu.dts 6c87efb csky: remove the deprecate name. f6dda39 csky: add dt-bindings doc. d9f02a8 csky: remove KERNEL_VERSION in upstream branch 7bd663c csky: Use kernel/dma/noncoherent.c 1544c09 csky: bugfix emmc hang up LINS-976 e963271 csky: cleanup include/asm/Kbuild cd267ba csky: remove CSKY_DEBUG_INFO 78950da csky: remove dcache invalid. 13fe51d csky: remove csum_ipv6_magic(), use generic one. a7372db csky: bugfix CK810 access twice error. 1bb7c69 csky: bugfix add gcc asm memory for barrier. 5ea3257 csky: add -msoft-float instead of -mfloat-abi=soft. 38b037d csky: bugfix losing cache flush range. ab5e8c4 csky: Add ticket-spinlock and qrwlock support. c9aaec5 csky: rename cskyksyms.c to libgcc_ksyms.c 28c5e48 csky: avoid the MB on failure: trylock f929c97 csky: bugfix idly4 may cause exception. 09dc496 csky: Use GENERIC_ASHLDI3/ASHRDI3 etc 6ecc99d csky: optimize smp boot code. 16f50df csky: asm/bug.h simple implement. 0ba532a csky: csky asm/atomic.h added. df66947 csky: asm/compat.h added |
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Guo Ren
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edff1b4835 |
irqchip: add C-SKY APB bus interrupt controller
The driver is for C-SKY APB bus interrupt controller. It's a simple interrupt controller which use pending reg to detect the irq and use enable/disable reg to mask/unmask interrupt sources. A lot of SOCs based on C-SKY CPU use the interrupt controller as root controller. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> |
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Guo Ren
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d8a5f5f791 |
irqchip: add C-SKY SMP interrupt controller
The driver is for C-SKY SMP interrupt controller. It support 16 soft-irqs, 16 private-irqs, and 992 max external-irqs, a total of 1024 interrupts. C-SKY CPU 807/810/860 SMP/non-SMP could use it. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> |
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Miquel Raynal
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61ce8d8d8a |
irqchip/irq-mvebu-sei: Add new driver for Marvell SEI
This is a cascaded interrupt controller in the AP806 GIC that collapses
SEIs (System Error Interrupt) coming from the AP and the CPs (through
the ICU).
The SEI handles up to 64 interrupts. The first 21 interrupts are wired
from the AP. The next 43 interrupts are from the CPs and are triggered
through MSI messages. To handle this complexity, the driver has to
declare to the upper layer: one IRQ domain for the wired interrupts,
one IRQ domain for the MSIs; and acts as a MSI controller ('parent')
by declaring an MSI domain.
Suggested-by: Haim Boot <hayim@marvell.com>
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Linus Torvalds
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1009aa1205 |
RISC-V Updates for the 4.19 Merge Window
This tag contains some major improvements to the RISC-V port, including
the necessary interrupt controller and timer support to actually make it
to userspace. Support for three devices has been added:
* Support for the ISA-mandated timers on RISC-V systems.
* Support for the ISA-mandated first-level interrupt controller on
RISC-V systems, which is handled as part of our core arch code because
it's very small and tightly tied to the ISA.
* Support for SiFive's platform-level interrupt controller, which talks
to the actual devices.
In addition to these new devices, there are a handful of cleanups all
over the RISC-V tree:
* Build fixes for various configurations
* A fix to the vDSO build's makefile so it respects CFLAGS.
* The addition of __lshrti3, a libgcc derived function necessary for
some 32-bit configurations.
* !SMP && PERF_EVENTS
* Cleanups to the arch code to remove the remnants of old versions of
the drivers that were just properly submitted.
* Some dead code from the timer driver, most of which wasn't ever
even compiled.
* Cleanups of some interrupt #defines, which are now local to the
interrupt handling code.
* Fixes to ptrace(), which while not being sufficient to fully make GDB
work are at least sufficient to get simple GDB tasks to work.
* Early printk support via RISC-V's architecturally mandated SBI console
device.
* A fix to our early debug trap handler to ensure it's always aligned.
These patches have all been through a fairly extensive review process,
but as this enables a whole pile of functionality (ie, userspace) I'm
confident we'll need to submit a few more patches. The only concrete
issues I know about are the sys_riscv_flush_icache patches, but as I
managed to screw those up on Friday I figured it'd be best to let them
bake another week.
This tag boots a Fedora root filesystem on QEMU's master branch for me,
and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on
the HiFive Unleashed.
Thanks to Christoph Hellwig and the other guys at WD for getting the new
drivers in shape!
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Merge tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux
Pull RISC-V updates from Palmer Dabbelt:
"This contains some major improvements to the RISC-V port, including
the necessary interrupt controller and timer support to actually make
it to userspace. Support for three devices has been added:
- the ISA-mandated timers on RISC-V systems.
- the ISA-mandated first-level interrupt controller on RISC-V
systems, which is handled as part of our core arch code because
it's very small and tightly tied to the ISA.
- SiFive's platform-level interrupt controller, which talks to the
actual devices.
In addition to these new devices, there are a handful of cleanups all
over the RISC-V tree:
- build fixes for various configurations:
* A fix to the vDSO build's makefile so it respects CFLAGS.
* The addition of __lshrti3, a libgcc derived function necessary
for some 32-bit configurations.
* !SMP && PERF_EVENTS
- Cleanups to the arch code to remove the remnants of old versions of
the drivers that were just properly submitted.
* Some dead code from the timer driver, most of which wasn't ever
even compiled.
* Cleanups of some interrupt #defines, which are now local to the
interrupt handling code.
- Fixes to ptrace(), which while not being sufficient to fully make
GDB work are at least sufficient to get simple GDB tasks to work.
- Early printk support via RISC-V's architecturally mandated SBI
console device.
- A fix to our early debug trap handler to ensure it's always
aligned.
These patches have all been through a fairly extensive review process,
but as this enables a whole pile of functionality (ie, userspace) I'm
confident we'll need to submit a few more patches. The only concrete
issues I know about are the sys_riscv_flush_icache patches, but as I
managed to screw those up on Friday I figured it'd be best to let them
bake another week.
This tag boots a Fedora root filesystem on QEMU's master branch for
me, and before this morning's rebase (from 4.18-rc8 to 4.18) it booted
on the HiFive Unleashed.
Thanks to Christoph Hellwig and the other guys at WD for getting the
new drivers in shape!"
* tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller
dt-bindings: interrupt-controller: RISC-V local interrupt controller
RISC-V: Fix !CONFIG_SMP compilation error
irqchip: add a SiFive PLIC driver
RISC-V: Add the directive for alignment of stvec's value
clocksource: new RISC-V SBI timer driver
RISC-V: implement low-level interrupt handling
RISC-V: add a definition for the SIE SEIE bit
RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
RISC-V: simplify software interrupt / IPI code
RISC-V: remove timer leftovers
RISC-V: Add early printk support via the SBI console
RISC-V: Don't increment sepc after breakpoint.
RISC-V: implement __lshrti3.
RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO
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Christoph Hellwig
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8237f8bc4f
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irqchip: add a SiFive PLIC driver
Add a driver for the SiFive implementation of the RISC-V Platform Level Interrupt Controller (PLIC). The PLIC connects global interrupt sources to the local interrupt controller on each hart. This driver is based on the driver in the RISC-V tree from Palmer Dabbelt, but has been almost entirely rewritten since, and includes many fixes from Atish Patra. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Atish Patra <atish.patra@wdc.com> [Binding update by Palmer] Signed-off-by: Palmer Dabbelt <palmer@sifive.com> |
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Palmer Dabbelt
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4f7799d96e |
genirq/irqchip: Remove MULTI_IRQ_HANDLER as it's now obselete
Now that every user of MULTI_IRQ_HANDLER has been convereted over to use GENERIC_IRQ_MULTI_HANDLER remove the references to MULTI_IRQ_HANDLER. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux@armlinux.org.uk Cc: catalin.marinas@arm.com Cc: Will Deacon <will.deacon@arm.com> Cc: jonas@southpole.se Cc: stefan.kristiansson@saunalahti.fi Cc: shorne@gmail.com Cc: jason@lakedaemon.net Cc: marc.zyngier@arm.com Cc: Arnd Bergmann <arnd@arndb.de> Cc: nicolas.pitre@linaro.org Cc: vladimir.murzin@arm.com Cc: keescook@chromium.org Cc: jinb.park7@gmail.com Cc: yamada.masahiro@socionext.com Cc: alexandre.belloni@bootlin.com Cc: pombredanne@nexb.com Cc: Greg KH <gregkh@linuxfoundation.org> Cc: kstewart@linuxfoundation.org Cc: jhogan@kernel.org Cc: mark.rutland@arm.com Cc: ard.biesheuvel@linaro.org Cc: james.morse@arm.com Cc: linux-arm-kernel@lists.infradead.org Cc: openrisc@lists.librecores.org Link: https://lkml.kernel.org/r/20180622170126.6308-6-palmer@sifive.com |
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Palmer Dabbelt
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08fb550cb3 |
irqchip: Port the ARM IRQ drivers to GENERIC_IRQ_MULTI_HANDLER
GENERIC_IRQ_MULTI_HANDLER is incompatible with MULTI_IRQ_HANDLER because they define the same symbols. Multiple generic irqchip drivers select MULTI_IRQ_HANDLER, which is now defined on all architectures that provide set_handle_irq(). To solve this select GENERIC_IRQ_MULTI_HANDLER for all drivers that used to select MULTI_IRQ_HANDLER, but only when MULTI_IRQ_HANDLER doesn't exist. After that every architecture can be converted over from MULTI_IRQ_HANDLER to GENERIC_IRQ_MULTI_HANDLER before removing the extra MULTI_IRQ_HANDLER scaffolding. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux@armlinux.org.uk Cc: catalin.marinas@arm.com Cc: Will Deacon <will.deacon@arm.com> Cc: jonas@southpole.se Cc: stefan.kristiansson@saunalahti.fi Cc: shorne@gmail.com Cc: jason@lakedaemon.net Cc: marc.zyngier@arm.com Cc: Arnd Bergmann <arnd@arndb.de> Cc: nicolas.pitre@linaro.org Cc: vladimir.murzin@arm.com Cc: keescook@chromium.org Cc: jinb.park7@gmail.com Cc: yamada.masahiro@socionext.com Cc: alexandre.belloni@bootlin.com Cc: pombredanne@nexb.com Cc: Greg KH <gregkh@linuxfoundation.org> Cc: kstewart@linuxfoundation.org Cc: jhogan@kernel.org Cc: mark.rutland@arm.com Cc: ard.biesheuvel@linaro.org Cc: james.morse@arm.com Cc: linux-arm-kernel@lists.infradead.org Cc: openrisc@lists.librecores.org Cc: Shea Levy <shea@shealevy.com> Link: https://lkml.kernel.org/r/20180622170126.6308-2-palmer@sifive.com |
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Linus Torvalds
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df34df483a |
Staging/IIO patches for 4.17-rc1
Here is the big set of Staging/IIO driver patches for 4.17-rc1. It is a lot, over 500 changes, but not huge by previous kernel release standards. We deleted more lines than we added again (27k added vs. 91k remvoed), thanks to finally being able to delete the IRDA drivers and networking code. We also deleted the ccree crypto driver, but that's coming back in through the crypto tree to you, in a much cleaned-up form. Added this round is at lot of "mt7621" device support, which is for an embedded device that Neil Brown cares about, and of course a handful of new IIO drivers as well. And finally, the fsl-mc core code moved out of the staging tree to the "real" part of the kernel, which is nice to see happen as well. Full details are in the shortlog, which has all of the tiny cleanup patches described. All of these have been in linux-next for a while with no reported issues. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCWsSnAA8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+yn60ACgxKvU/5XBP14hBkBpAcD0Q43OHe0AniEti65M Kw03GWK3NNM3pzk49BjZ =sj3K -----END PGP SIGNATURE----- Merge tag 'staging-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging Pull staging/IIO updates from Greg KH: "Here is the big set of Staging/IIO driver patches for 4.17-rc1. It is a lot, over 500 changes, but not huge by previous kernel release standards. We deleted more lines than we added again (27k added vs. 91k remvoed), thanks to finally being able to delete the IRDA drivers and networking code. We also deleted the ccree crypto driver, but that's coming back in through the crypto tree to you, in a much cleaned-up form. Added this round is at lot of "mt7621" device support, which is for an embedded device that Neil Brown cares about, and of course a handful of new IIO drivers as well. And finally, the fsl-mc core code moved out of the staging tree to the "real" part of the kernel, which is nice to see happen as well. Full details are in the shortlog, which has all of the tiny cleanup patches described. All of these have been in linux-next for a while with no reported issues" * tag 'staging-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (579 commits) staging: rtl8723bs: Remove yield call, replace with cond_resched() staging: rtl8723bs: Replace yield() call with cond_resched() staging: rtl8723bs: Remove unecessary newlines from 'odm.h'. staging: rtl8723bs: Rework 'struct _ODM_Phy_Status_Info_' coding style. staging: rtl8723bs: Rework 'struct _ODM_Per_Pkt_Info_' coding style. staging: rtl8723bs: Replace NULL pointer comparison with '!'. staging: rtl8723bs: Factor out rtl8723bs_recv_tasklet() sections. staging: rtl8723bs: Fix function signature that goes over 80 characters. staging: rtl8723bs: Fix lines too long in update_recvframe_attrib(). staging: rtl8723bs: Remove unnecessary blank lines in 'rtl8723bs_recv.c'. staging: rtl8723bs: Change camel case to snake case in 'rtl8723bs_recv.c'. staging: rtl8723bs: Add missing braces in else statement. staging: rtl8723bs: Add spaces around ternary operators. staging: rtl8723bs: Fix lines with trailing open parentheses. staging: rtl8723bs: Remove unnecessary length #define's. staging: rtl8723bs: Fix IEEE80211 authentication algorithm constants. staging: rtl8723bs: Fix alignment in rtw_wx_set_auth(). staging: rtl8723bs: Remove braces from single statement conditionals. staging: rtl8723bs: Remove unecessary braces from switch statement. staging: rtl8723bs: Fix newlines in rtw_wx_set_auth(). ... |
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Alexandre Belloni
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19d9916448 |
irqchip: Add a driver for the Microsemi Ocelot controller
The Microsemi Ocelot SoC has a pretty simple IRQ controller in its ICPU block. Add a driver for it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Archana Sathyakumar
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f55c73aef8 |
irqchip/pdc: Add PDC interrupt controller for QCOM SoCs
The Power Domain Controller (PDC) on QTI SoCs like SDM845 houses an interrupt controller along with other domain control functions to handle interrupt related functions like handle falling edge or active low which are not detected at the GIC and handle wakeup interrupts. The interrupt controller is on an always-on domain for the purpose of waking up the processor. Only a subset of the processor's interrupts are routed through the PDC to the GIC. The PDC powers on the processors' domain, when in low power mode and replays pending interrupts so the GIC may wake up the processor. Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Bogdan Purcareata
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7afe031c1a |
staging: fsl-mc: Move irqchip code out of staging
Now that the fsl-mc bus core infrastructure is out of staging, the remaining irqchip glue code used (irq-gic-v3-its-fsl-mc-msi.c) goes to drivers/irqchip. Create new Kconfig option for irqchip code that depends on FSL_MC_BUS and ARM_GIC_V3_ITS. This ensures irqchip code only gets built on ARM64 platforms. We can now remove #ifdef GENERIC_MSI_DOMAIN_OPS as it was only needed for x86. Signed-off-by: Stuart Yoder <stuyoder@gmail.com> [rebased, add dpaa2_eth and dpio #include updates] Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> [rebased, split irqchip to separate patch] Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> [add Kconfig dependency on ARM_GIC_V3_ITS] Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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Miodrag Dinic
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4235ff50cf |
irqchip/irq-goldfish-pic: Add Goldfish PIC driver
Add device driver for a virtual programmable interrupt controller The virtual PIC is designed as a device tree-based interrupt controller. The compatible string used by OS for binding the driver is "google,goldfish-pic". Signed-off-by: Miodrag Dinic <miodrag.dinic@mips.com> Signed-off-by: Goran Ferenc <goran.ferenc@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Thomas Gleixner
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41cc30412d |
irqchip updates for 4.15, take #4
- A core irq fix for legacy cases where the irq trigger is not reported by firmware - A couple of GICv3/4 fixes (Kconfig, of-node refcount, error handling) - Trivial pr_err fixes -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAloJ2UYVHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDtkcP/i2HrgT5CmoA315h5HLXfFImxZwg YG7ti3zqu1TM7HXNlfBgSltqiU5UgYOd2KjgUR+w30t1239DwxVdtoy6ZgGWXlfe xmHlXAiEDkqaAV3P/RHKkl8xRDkyWhKmfY1ym/So0J68EPytuiZiT4wJZO39u/xk Gi2fW38gywl4bEb9MA48noEnkNkr93DjJfFyiPxPYiAaWeFRoP+X5l171kTpCdSv sT5hfQvfsz7mQZVecMBwGg6QuWnlUplkzPb4lNhuk/tJTU97vf3Py8abzeiGqBMa 5NoH9PUMZs0L8kv6DgR2DEOmhmmk0+mwO7VWVT3eVtYoxSS8oW0i2OzgB9kCOy8+ LZi+M0fMSL6hiAgwlV5YrHYvsVl2rGjCNAqC+q2ggpW4XH9Kql2caki331mGqAyr qDeI0SWaABz5c9ajtsfQ78T0FE70xwIJ5TT1RmtKt2LFCpJjBacjK3vUST2ypIrF k0AJTmBwEefKNvxTrjkZtenblCVo92lT+boAv7HuI612NicVSBEsK7S+96kGlGMw KNi+cwGriJRWIbsn+VMpLFGyPgEmWQ1p/4Z/tkwSevqOl/k8KrNw6+VoyDS1PmJU gIQ0hh8wMnm2l9VGJARc0+pHKr0KYN52j+jZI5+OGNKKAZ0jGYI4t2JiemtOwmet q2KNdm6mvBYUYirj =/8DQ -----END PGP SIGNATURE----- Merge tag 'irqchip-4.15-4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent Pull irqchip updates for 4.15, take #4 from Marc Zyngier - A core irq fix for legacy cases where the irq trigger is not reported by firmware - A couple of GICv3/4 fixes (Kconfig, of-node refcount, error handling) - Trivial pr_err fixes |
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Linus Torvalds
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670310dfba |
Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq core updates from Thomas Gleixner:
"A rather large update for the interrupt core code and the irq chip drivers:
- Add a new bitmap matrix allocator and supporting changes, which is
used to replace the x86 vector allocator which comes with separate
pull request. This allows to replace the convoluted nested loop
allocation function in x86 with a facility which supports the
recently added property of managed interrupts proper and allows to
switch to a best effort vector reservation scheme, which addresses
problems with vector exhaustion.
- A large update to the ARM GIC-V3-ITS driver adding support for
range selectors.
- New interrupt controllers:
- Meson and Meson8 GPIO
- BCM7271 L2
- Socionext EXIU
If you expected that this will stop at some point, I have to
disappoint you. There are new ones posted already. Sigh!
- STM32 interrupt controller support for new platforms.
- A pile of fixes, cleanups and updates to the MIPS GIC driver
- The usual small fixes, cleanups and updates all over the place.
Most visible one is to move the irq chip drivers Kconfig switches
into a separate Kconfig menu"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (70 commits)
genirq: Fix type of shifting literal 1 in __setup_irq()
irqdomain: Drop pointless NULL check in virq_debug_show_one
genirq/proc: Return proper error code when irq_set_affinity() fails
irq/work: Use llist_for_each_entry_safe
irqchip: mips-gic: Print warning if inherited GIC base is used
irqchip/mips-gic: Add pr_fmt and reword pr_* messages
irqchip/stm32: Move the wakeup on interrupt mask
irqchip/stm32: Fix initial values
irqchip/stm32: Add stm32h7 support
dt-bindings/interrupt-controllers: Add compatible string for stm32h7
irqchip/stm32: Add multi-bank management
irqchip/stm32: Select GENERIC_IRQ_CHIP
irqchip/exiu: Add support for Socionext Synquacer EXIU controller
dt-bindings: Add description of Socionext EXIU interrupt controller
irqchip/gic-v3-its: Fix VPE activate callback return value
irqchip: mips-gic: Make IPI bitmaps static
irqchip: mips-gic: Share register writes in gic_set_type()
irqchip: mips-gic: Remove gic_vpes variable
irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs
irqchip: mips-gic: Configure EIC when CPUs come online
...
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Marc Zyngier
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29f411399a |
irqchip/gic-v3-its: Remove artificial dependency on PCI
The GICv3 ITS doesn't really depend on PCI. Only the PCI/MSI
part of it does, and there is no reason not to blow away most
of the irqchip stack because PCI is not selected (though not
selecting PCI seem to be asking for punishment, but hey...).
So let's split the PCI-specific part from the ITS in the Kconfig
file, and let's make that part depend on PCI. Architecture specific
hacks (arch/arm{,64}/Kconfig) will be addressed in a separate patch.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Thomas Gleixner
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9dc505d6df |
irqchip updates for 4.15, take #3
- New Socionext Synquacer EXIU driver - stm32 new platform support and fixes - One GICv4 bugfix - A couple of MIPS GIC cleanups -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAloEPrsVHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDZ+wP/Ryg9wZ87jUuWXE0iK9U//4GXk5p t5I8bv+ajzxVDZgmoruN8rxGOVIoB9vfPj2IKAbP/Je3fAVgmEnhn57T3/qxuoQj VsO2QyUeY5uqoZrvFkha/J3YFiZQ0gXXwFDCBKE9F/aXUx+z4YSE2SXMLI16p5LZ wD340BJ6RBgzcdu/iIpHP9mWbK+h4OCwOt8UG1m4aOQkCQxwO4onbzC7ck17vnyU /w+AKjQBjjMzVCqPgY/Thj+rP3bPpQ3H0YUN7yxMuwpJX2vPan++SLIJIXNsnXo2 E4goqDoCYN/jvA0SKF2b3+7ylLAI4+CI2IKADYiSk7CqjtXl7GeyR0dAj3E9/MGE ymNAo05dxDVfx+qNu8SqPRfqksXcK0eK1gR0069Y2+8THIArybyF7q+bPvCTHtQb 0vZkBHHyUq2turMueomqxHP5FyUVe+4eTpQvTpkgnO1nHcDjkranyK4lMIgFi0ST OQfm3ZftmPE290PQKm+BCyJpgVYeSXiVuZUpev3SLzpMTLKZRVn2KVjOz9w5Mrse COT7LYGUkiRAVocI2Z2Ch9NNSQnTjE+tKShQEUr24uALuqWAeUl5OPhh5iiZjRcj HwHFv5huXP+0vt4IGpF60P91hLBGVQGpAkRMPc2GNKTv6Aynf0HSgW9Ksi5NKnHz chIm8ZAYPuqfFBjm =Rym/ -----END PGP SIGNATURE----- Merge tag 'irqchip-4.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates for 4.15, take #3 from Marc Zyngier: - New Socionext Synquacer EXIU driver - stm32 new platform support and fixes - One GICv4 bugfix - A couple of MIPS GIC cleanups |
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Ludovic Barre
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0e7d780721 |
irqchip/stm32: Select GENERIC_IRQ_CHIP
This patch adds GENERIC_IRQ_CHIP to stm32 exti config. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Stafford Horne
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9b54470afd |
irqchip: add initial support for ompic
IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as described in the Multi-core support section of the OpenRISC 1.2 architecture specification: https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf Each OpenRISC core contains a full interrupt controller which is used in the SMP architecture for interrupt balancing. This IPI device, the ompic, is the only external device required for enabling SMP on OpenRISC. Pending ops are stored in a memory bit mask which can allow multiple pending operations to be set and serviced at a time. This is mostly borrowed from the alpha IPI implementation. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> [shorne@gmail.com: converted ops to bitmask, wrote commit message] Signed-off-by: Stafford Horne <shorne@gmail.com> |
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Thomas Gleixner
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d9ee91c1b1 |
irqchip/meson: Disable COMPILE_TEST
The driver fails to compile with CONFIG_COMPILE_TEST=y on x86: irq-meson-gpio.c: In function ‘meson_gpio_irq_parse_dt’: irq-meson-gpio.c:343:8: error: implicit declaration of function ‘of_property_read_variable_u32_array’ ret = of_property_read_variable_u32_array(node, Adding COMPILE_TEST to a driver requires at least compile testing it for x86.... Reported-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Heiner Kallweit <hkallweit1@gmail.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Marc Zyngier <marc.zyngier@arm.com> |
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Jerome Brunet
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215f4cc0fb |
irqchip/meson: Add support for gpio interrupt controller
Add support for the interrupt gpio controller found on Amlogic's meson SoC family. This controller is a separate controller from the gpio controller. It is able to spy on the SoC pad. It is essentially a 256 to 8 router with a filtering block to select level or edge and polarity. The number of actual mappable inputs depends on the SoC. Cc: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Randy Dunlap
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c94fb639d5 |
irqchip: Add Kconfig menu
Add a menu for IRQ chip drivers. This makes the Device drivers menu be more consistent (listing "subsystems" instead of specific options) and makes the IRQCHIP options be listed in expected places for 'make menu|xconfig'. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Jason Cooper <jason@lakedaemon.net> Link: https://lkml.kernel.org/r/3db7385a-c6a1-5c93-0797-6f4b6b2b2cde@infradead.org |
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Thomas Gleixner
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9fbd7fd28d |
irqchip updates for 4.14
- irqchip-specific part of the monster GICv4 series - new UniPhier AIDET irqchip driver - new variants of some Freescale MSI widget - blanket removal of of_node->full_name in printk - random collection of fixes -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAlmoQxkVHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDVUMQAIyE1q3fjSNZ+EkfK8+mbcWC80Wc suklgcqVbHahu6FHuHALlR7rgJIPSaFYFpDIwybA9A0Pwia/5Jf2mOL3RGVF4f97 nyHlSS16kocZz8lKn+NtgcaUiFRma3y7GNek0pnsSlm+Vu+Syw3xssN+yYcGujTu jWRocvIqIJlScpzHG/Ulx3tZTXYfipQFfIQ3+9gm/i+KYqTwGDH/MsdxI7uAbctx YJGwLVtv4MGGmNHaq4iS64d55yrG/4Yqv+q92zFaaxj+V0di+Ds01+MDhdq8X7N/ fhLGY/Yh/I3FiIIdIO/O1sj1EPO6lLbg4DPYXIMdjzwhBdKhu8i66/ttH/Kx//Aa 1hhLZSN6rYiJM3lWcTxej45bs8MR/3MBm4gKpZxTgJ12YRIwgY8lRyoqXTlto5ls w10yi5wFsJaAO1E/HdEs/dyndV1jpvGo9KIRnfh7E5+Hw7PCYs9kZa4MUtq9RYT8 Civyppi2sMfKYtGvwm+FS6sIigoFCh4DJ5MmUbM5CLh5imnggyYJlTsJdBuxVDZM 1RoDnX/YebpVceezIZ/oCKq60Utck0Oqge2pc+NjVQupAp/x/13R/7DQPnFCq/OL Avx9kBtSzdYmYgE3EWt9n+h4LT23JpOym2OEUF3fhpPE96BKAJkMEPB/QlBi39fo 0cZEX8M7xq5KjRJy =3ZS3 -----END PGP SIGNATURE----- Merge tag 'irqchip-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates for 4.14 from Marc Zyngier: - irqchip-specific part of the monster GICv4 series - new UniPhier AIDET irqchip driver - new variants of some Freescale MSI widget - blanket removal of of_node->full_name in printk - random collection of fixes |
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Masahiro Yamada
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5ed34d3a43 |
irqchip: Add UniPhier AIDET irqchip driver
UniPhier SoCs contain AIDET (ARM Interrupt Detector). This is intended to provide additional features that are not covered by GIC. The main purpose is to provide logic inverter to support low level and falling edge trigger types for interrupt lines from on-board devices. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Marc Zyngier
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5009121214 |
irqchip/xtensa-mx: Report that effective affinity is a single target
The xtensa-mx driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Chris Zankel <chris@zankel.net> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: http://lkml.kernel.org/r/20170818083925.10108-13-marc.zyngier@arm.com |
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Marc Zyngier
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18416e45b7 |
irqchip/mips-gic: Report that effective affinity is a single target
The MIPS GIC driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Chris Zankel <chris@zankel.net> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: http://lkml.kernel.org/r/20170818083925.10108-12-marc.zyngier@arm.com |
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Marc Zyngier
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b8d9884ac6 |
irqchip/bcm-7038-l1: Report that effective affinity is a single target
The BCM 7038-L1 driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Chris Zankel <chris@zankel.net> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: http://lkml.kernel.org/r/20170818083925.10108-9-marc.zyngier@arm.com |
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Marc Zyngier
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d0ed5e8e14 |
irqchip/bcm-6345-l1: Report that effective affinity is a single target
The BCM 6345-L1 driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Chris Zankel <chris@zankel.net> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: http://lkml.kernel.org/r/20170818083925.10108-8-marc.zyngier@arm.com |
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Marc Zyngier
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e31793a3e5 |
irqchip/armada-370-xp: Report that effective affinity is a single target
The Armada 370 XP driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Chris Zankel <chris@zankel.net> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: http://lkml.kernel.org/r/20170818083925.10108-7-marc.zyngier@arm.com |
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Marc Zyngier
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956ae91ae8 |
irqchip/gic-v3: Report that effective affinity is a single target
The GICv3 driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Chris Zankel <chris@zankel.net> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: http://lkml.kernel.org/r/20170818083925.10108-5-marc.zyngier@arm.com |
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Marc Zyngier
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0c9e498286 |
irqchip/gic: Report that effective affinity is a single target
The GIC driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Lunn <andrew@lunn.ch> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Chris Zankel <chris@zankel.net> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: http://lkml.kernel.org/r/20170818083925.10108-4-marc.zyngier@arm.com |
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Linus Torvalds
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55a7b2125c |
arm64 updates for 4.13:
- RAS reporting via GHES/APEI (ACPI) - Indirect ftrace trampolines for modules - Improvements to kernel fault reporting - Page poisoning - Sigframe cleanups and preparation for SVE context - Core dump fixes - Sparse fixes (mainly relating to endianness) - xgene SoC PMU v3 driver - Misc cleanups and non-critical fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJZWiuVAAoJELescNyEwWM0g/gIAIRpVEzjE61zfm/KCsVuIu4O p6F/HrvF/ApvlFcth8LDpTDYUholzT1e9wmx/O0Ll37UvFUrReT03R5MMJ02WU8s hRg0N4izdg2BPa9zuaP/XE5i6WmFfRAwFsv6PzX77FjNGk0M4zhW8acNpWHYMBQT DwXT/xCvg6045Sj6CuwfcIqqVHrz6/kpBmvdbW7G3/WpIHpUGIWM9EO3mkuLGMj0 j0VSCxfAVJvWwmKEBdFExLNjqxvSlVAMOIEAw7yBNLjuheiL+afK+Y1BggB00oe8 14+6viOgW6L97VmPpYVn0YDseqeGg5DqlNF3NqjTqdmzWH/ApAvL4WXN7SL2jbU= =RNzb -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Will Deacon: - RAS reporting via GHES/APEI (ACPI) - Indirect ftrace trampolines for modules - Improvements to kernel fault reporting - Page poisoning - Sigframe cleanups and preparation for SVE context - Core dump fixes - Sparse fixes (mainly relating to endianness) - xgene SoC PMU v3 driver - Misc cleanups and non-critical fixes * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (75 commits) arm64: fix endianness annotation for 'struct jit_ctx' and friends arm64: cpuinfo: constify attribute_group structures. arm64: ptrace: Fix incorrect get_user() use in compat_vfp_set() arm64: ptrace: Remove redundant overrun check from compat_vfp_set() arm64: ptrace: Avoid setting compat FP[SC]R to garbage if get_user fails arm64: fix endianness annotation for __apply_alternatives()/get_alt_insn() arm64: fix endianness annotation in get_kaslr_seed() arm64: add missing conversion to __wsum in ip_fast_csum() arm64: fix endianness annotation in acpi_parking_protocol.c arm64: use readq() instead of readl() to read 64bit entry_point arm64: fix endianness annotation for reloc_insn_movw() & reloc_insn_imm() arm64: fix endianness annotation for aarch64_insn_write() arm64: fix endianness annotation in aarch64_insn_read() arm64: fix endianness annotation in call_undef_hook() arm64: fix endianness annotation for debug-monitors.c ras: mark stub functions as 'inline' arm64: pass endianness info to sparse arm64: ftrace: fix !CONFIG_ARM64_MODULE_PLTS kernels arm64: signal: Allow expansion of the signal frame acpi: apei: check for pending errors when probing GHES entries ... |
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Thomas Petazzoni
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e0de91a977 |
irqchip/irq-mvebu-icu: Add new driver for Marvell ICU
The Marvell ICU unit is found in the CP110 block of the Marvell Armada 7K and 8K SoCs. It collects the wired interrupts of the devices located in the CP110 and turns them into SPI interrupts in the GIC located in the AP806 side of the SoC, by using a memory transaction. Until now, the ICU was configured in a static fashion by the firmware, and Linux was relying on this static configuration. By having Linux configure the ICU, we are more flexible, and we can allocate dynamically the GIC SPI interrupts only for devices that are actually in use. The driver was initially written by Hanna Hawa <hannah@marvell.com>. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Thomas Petazzoni
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a68a63cb4d |
irqchip/irq-mvebu-gicp: Add new driver for Marvell GICP
This commit adds a simple driver for the Marvell GICP, a hardware unit that converts memory writes into GIC SPI interrupts. The driver provides a number of functions to the ICU driver to allocate GICP interrupts, and get the physical addresses that the ICUs should write to to set/clear interrupts. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Lorenzo Pieralisi
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c6bb8f89fa |
ARM64/irqchip: Update ACPI_IORT symbol selection logic
ACPI IORT is an ACPI addendum to describe the connection topology of devices with IOMMUs and interrupt controllers on ARM64 ACPI systems. Currently the ACPI IORT Kbuild symbol is selected whenever the Kbuild symbol ARM_GIC_V3_ITS is enabled, which in turn is selected by ARM64 Kbuild defaults. This makes the logic behind ACPI_IORT selection a bit twisted and not easy to follow. On ARM64 systems enabling ACPI the kbuild symbol ACPI_IORT should always be selected in that it is a kernel layer provided to the ARM64 arch code to parse and enable ACPI firmware bindings. Make the ACPI_IORT selection explicit in ARM64 Kbuild and remove the selection from ARM_GIC_V3_ITS entry, making the ACPI_IORT selection logic clearer to follow. Acked-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> |
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Linus Torvalds
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ac3c4aa248 |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from James Hogan:
"math-emu:
- Add missing clearing of BLTZALL and BGEZALL emulation counters
- Fix BC1EQZ and BC1NEZ condition handling
- Fix BLEZL and BGTZL identification
BPF:
- Add JIT support for SKF_AD_HATYPE
- Use unsigned access for unsigned SKB fields
- Quit clobbering callee saved registers in JIT code
- Fix multiple problems in JIT skb access helpers
Loongson 3:
- Select MIPS_L1_CACHE_SHIFT_6
Octeon:
- Remove vestiges of CONFIG_CAVIUM_OCTEON_2ND_KERNEL
- Remove unused L2C types and macros.
- Remove unused SLI types and macros.
- Fix compile error when USB is not enabled.
- Octeon: Remove unused PCIERCX types and macros.
- Octeon: Clean up platform code.
SNI:
- Remove recursive include of cpu-feature-overrides.h
Sibyte:
- Export symbol periph_rev to sb1250-mac network driver.
- Fix Kconfig warning.
Generic platform:
- Enable Root FS on NFS in generic_defconfig
SMP-MT:
- Use CPU interrupt controller IPI IRQ domain support
UASM:
- Add support for LHU for uasm.
- Remove needless ISA abstraction
mm:
- Add 48-bit VA space and 4-level page tables for 4K pages.
PCI:
- Add controllers before the specified head
irqchip driver for MIPS CPU:
- Replace magic 0x100 with IE_SW0
- Prepare for non-legacy IRQ domains
- Introduce IPI IRQ domain support
MAINTAINERS:
- Update email-id of Rahul Bedarkar
NET:
- sb1250-mac: Add missing MODULE_LICENSE()
CPUFREQ:
- Loongson2: drop set_cpus_allowed_ptr()
Misc:
- Disable Werror when W= is set
- Opt into HAVE_COPY_THREAD_TLS
- Enable GENERIC_CPU_AUTOPROBE
- Use common outgoing-CPU-notification code
- Remove dead define of ST_OFF
- Remove CONFIG_ARCH_HAS_ILOG2_U{32,64}
- Stengthen IPI IRQ domain sanity check
- Remove confusing else statement in __do_page_fault()
- Don't unnecessarily include kmalloc.h into <asm/cache.h>.
- Delete unused definition of SMP_CACHE_SHIFT.
- Delete redundant definition of SMP_CACHE_BYTES"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (39 commits)
MIPS: Sibyte: Fix Kconfig warning.
MIPS: Sibyte: Export symbol periph_rev to sb1250-mac network driver.
NET: sb1250-mac: Add missing MODULE_LICENSE()
MAINTAINERS: Update email-id of Rahul Bedarkar
MIPS: Remove confusing else statement in __do_page_fault()
MIPS: Stengthen IPI IRQ domain sanity check
MIPS: smp-mt: Use CPU interrupt controller IPI IRQ domain support
irqchip: mips-cpu: Introduce IPI IRQ domain support
irqchip: mips-cpu: Prepare for non-legacy IRQ domains
irqchip: mips-cpu: Replace magic 0x100 with IE_SW0
MIPS: Remove CONFIG_ARCH_HAS_ILOG2_U{32,64}
MIPS: generic: Enable Root FS on NFS in generic_defconfig
MIPS: mach-rm: Remove recursive include of cpu-feature-overrides.h
MIPS: Opt into HAVE_COPY_THREAD_TLS
CPUFREQ: Loongson2: drop set_cpus_allowed_ptr()
MIPS: uasm: Remove needless ISA abstraction
MIPS: Remove dead define of ST_OFF
MIPS: Use common outgoing-CPU-notification code
MIPS: math-emu: Fix BC1EQZ and BC1NEZ condition handling
MIPS: r2-on-r6-emu: Clear BLTZALL and BGEZALL debugfs counters
...
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Thomas Gleixner
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7a258ff04f |
Merge branch 'linus' into irq/core
Pick up upstream fixes to avoid conflicts with pending patches. |
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Paul Burton
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3838a547fd |
irqchip: mips-cpu: Introduce IPI IRQ domain support
Introduce support for registering an IPI IRQ domain suitable for use by systems using the MIPS MT (multithreading) ASE within a single core. This will allow for such systems to be supported generically, without the current kludge of IPI code split between the MIPS arch & the malta board support code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15836/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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Linus Walleij
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6ee532e2fa |
irqchip/gemini: Refactor Gemini driver to reflect Faraday origin
The Gemini irqchip turns out to be a standard IP component from Faraday Technology named FTINTC010 after some research and new information. - Rename the driver and all symbols to reflect the new information. - Add the new compatible string "faraday,ftintc010" - Create a Kconfig symbol CONFIG_FARADAY_FTINTC010 so that SoCs using this interrupt controller can easily select and reuse it instead of hardwiring it to ARCH_GEMINI I have created a separate patch to select the new Kconfig symbol from the Gemini machine, which will be merged through the ARM SoC tree. Cc: Greentime Hu <green.hu@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Arnd Bergmann
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fa23b9d1b8 |
irqchip/mvebu-odmi: Select GENERIC_MSI_IRQ_DOMAIN
This driver uses the MSI domain but has no strict dependency on PCI_MSI, so we
may run into a build failure when CONFIG_GENERIC_MSI_IRQ_DOMAIN is disabled:
drivers/irqchip/irq-mvebu-odmi.c:152:15: error: variable 'odmi_msi_ops' has initializer but incomplete type
static struct msi_domain_ops odmi_msi_ops = {
^~~~~~~~~~~~~~
drivers/irqchip/irq-mvebu-odmi.c:155:15: error: variable 'odmi_msi_domain_info' has initializer but incomplete type
static struct msi_domain_info odmi_msi_domain_info = {
^~~~~~~~~~~~~~~
drivers/irqchip/irq-mvebu-odmi.c:156:3: error: 'struct msi_domain_info' has no member named 'flags'
.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
^~~~~
drivers/irqchip/irq-mvebu-odmi.c:156:12: error: 'MSI_FLAG_USE_DEF_DOM_OPS' undeclared here (not in a function)
.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
^~~~~~~~~~~~~~~~~~~~~~~~
drivers/irqchip/irq-mvebu-odmi.c:156:39: error: 'MSI_FLAG_USE_DEF_CHIP_OPS' undeclared here (not in a function); did you mean 'MSI_FLAG_USE_DEF_DOM_OPS'?
Selecting the option from this driver seems to solve this nicely, though I could
not find any other instance of this in irqchip drivers.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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Agustin Vega-Frias
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f20cc9b00c |
irqchip/qcom: Add IRQ combiner driver
Driver for interrupt combiners in the Top-level Control and Status Registers (TCSR) hardware block in Qualcomm Technologies chips. An interrupt combiner in this block combines a set of interrupts by OR'ing the individual interrupt signals into a summary interrupt signal routed to a parent interrupt controller, and provides read- only, 32-bit registers to query the status of individual interrupts. The status bit for IRQ n is bit (n % 32) within register (n / 32) of the given combiner. Thus, each combiner can be described as a set of register offsets and the number of IRQs managed. Signed-off-by: Agustin Vega-Frias <agustinv@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Zubair Lutfullah Kakakhel
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0547dc7885 |
microblaze/irqchip: Move intc driver to irqchip
The Xilinx AXI Interrupt Controller IP block is used by the MIPS based xilfpga platform and a few PowerPC based platforms. Move the interrupt controller code out of arch/microblaze so that it can be used by everyone Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Rich Felker
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3602ffdee9 |
irqchip/jcore: Don't show Kconfig menu item for driver
Core drivers for J-Core SoCs will be selected implicitly via CONFIG_SH_JCORE_SOC instead. Based on a corresponding change to the clocksource/timer driver requested by Daniel Lezcano. Signed-off-by: Rich Felker <dalias@libc.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-sh@vger.kernel.org Link: http://lkml.kernel.org/r/883a3d17084003e3cf21bab73ec12828fe4ff6c6.1476899495.git.dalias@libc.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
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Thomas Gleixner
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474aa3dd3e |
irqchip core changes for v4.9
- jcore: Add AIC driver - mips-gic: Use for_each_set_bit - mvebu: Add PIC driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJX5Cv8AAoJEP45WPkGe8ZnG/YP/23xxSShaURhhgmdk7vqMlp3 D4C+YZqghx3Xq+kVTH5R20FeZbQuC7DNV1B+zo75DIbCAQ0aNCYU94DIOrGDNj/S QocuWUy4oawYl730GEE7AVQL4kBK+fOwwAn7c6HjcRunNEU/IgNXwkWZLir/hpL+ KRFWXnPSocKUh50lXcGeHPrChEduT7cz7f6U/OyYzb8AgHw3zjJiWCqMaTcIGF/V 6fYsQjEuAj79UMxsuTH0Mv0vA/SzbyhtRRBIsGcP/Ket6ZW6DfdglB3SsAdxHxRa RoweK8zVorDfixjAOA/OsZ8vrjtyF2y9e/uHVXGMWfBgbXmP19QxpxtP+7u0z1Cq /L9rW0vYoQfv3tjvSon5TUOW/QMqmqvoclSTz80nRJmocEm8Za871vD53+iFOyPE sy0CsrussaooFahIl1z/kE5bugBBJKoTAnsAtfaWpTXTW+KGWOqncxsh6H9bMZUc XXbqr5TOqJk5ck9LJafLdDeVA4Cw2j7tq4wzXPnxoPwy6Dwgdjinsw8QWMbrlywR 2zGFuFlJdbRmHftFJujZ9XorTLa7978AU5K7CHr7ofaV742DH5hBRAUvBx6jTNhA 4W9UchKtEPzgzrvESVBYSj+cgvBYllewZg1XZgxDqQQ5CI2ePTKLaQwjVWiO4Q3K d9ZytcRUtuJtEWfbnyaT =DNCg -----END PGP SIGNATURE----- Merge tag 'irqchip-core-4.9' of git://git.infradead.org/users/jcooper/linux into irq/core Pull irqchip core changes for v4.9 from Jason Cooper - jcore: Add AIC driver - mips-gic: Use for_each_set_bit - mvebu: Add PIC driver |
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Alexandre TORGUE
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e072041688 |
drivers/irqchip: Add STM32 external interrupts support
The STM32 external interrupt controller consists of edge detectors that generate interrupts requests or wake-up events. Each line can be independently configured as interrupt or wake-up source, and triggers either on rising, falling or both edges. Each line can also be masked independently. Originally-from: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: arnd@arndb.de Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: bruherrera@gmail.com Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: lee.jones@linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1474387259-18926-3-git-send-email-alexandre.torgue@st.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
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Tomasz Nowicki
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3f010cf197 |
irqchip/gicv3-its: Probe ITS in the ACPI way
ITS is prepared for being initialized different than DT, therefore we can initialize it in ACPI way. We collect register base address from MADT table and pass mandatory info to firmware-agnostic ITS init call. Use here IORT lib to register ITS domain which then can be found and used on to build another PCI MSI domain in hierarchical stack domain. NOTE: Waiting for proper ITS and NUMA node relation description in IORT table, we pass around NUMA_NO_NODE to the its_probe_one init call. This means that Cavium ThunderX erratum 23144 (pass1.1 only) is not supported for ACPI boot method yet. Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Jason Cooper
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e02a9b7ce4 | Merge branch 'irqchip/mvebu64' into irqchip/core | |
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Thomas Petazzoni
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a109893bd3 |
irqchip/mvebu-pic: New driver for Marvell Armada 7K/8K PIC
The Marvell Armada 7K/8K integrates a secondary interrupt controller very originally named "PIC". It is connected to the main GIC via a PPI. Amongst other things, this PIC is used for the ARM PMU. This commit adds a simple irqchip driver for this interrupt controller. Since this interrupt controller is not needed early at boot time, we make the driver a proper platform driver rather than use the IRQCHIP_DECLARE() mechanism. Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1470408921-447-3-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Rich Felker
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981b58f66c |
irqchip/jcore-aic: Add J-Core AIC driver
There are two versions of the J-Core interrupt controller in use, aic1 which generates interrupts with programmable priorities, but only supports 8 irq lines and maps them to cpu traps in the range 17 to 24, and aic2 which uses traps in the range 64-127 and supports up to 128 irqs, with priorities dependent on the interrupt number. The Linux driver does not make use of priorities anyway. For simplicity, there is no aic1-specific logic in the driver beyond setting the priority register, which is necessary for interrupts to work at all. Eventually aic1 will likely be phased out, but it's currently in use in deployments and all released bitstream binaries. Signed-off-by: Rich Felker <dalias@libc.org> Link: https://lkml.kernel.org/r/c3b89ef74aaa6477575dbe2d410eb1d182503243.147018b6529.git.dalias@libc.org Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Linus Torvalds
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c8d0267efd |
PCI changes for the v4.8 merge window:
Enumeration
Move ecam.h to linux/include/pci-ecam.h (Jayachandran C)
Add parent device field to ECAM struct pci_config_window (Jayachandran C)
Add generic MCFG table handling (Tomasz Nowicki)
Refactor pci_bus_assign_domain_nr() for CONFIG_PCI_DOMAINS_GENERIC (Tomasz Nowicki)
Factor DT-specific pci_bus_find_domain_nr() code out (Tomasz Nowicki)
Resource management
Add devm_request_pci_bus_resources() (Bjorn Helgaas)
Unify pci_resource_to_user() declarations (Bjorn Helgaas)
Implement pci_resource_to_user() with pcibios_resource_to_bus() (microblaze, powerpc, sparc) (Bjorn Helgaas)
Request host bridge window resources (designware, iproc, rcar, xgene, xilinx, xilinx-nwl) (Bjorn Helgaas)
Make PCI I/O space optional on ARM32 (Bjorn Helgaas)
Ignore write combining when mapping I/O port space (Bjorn Helgaas)
Claim bus resources on MIPS PCI_PROBE_ONLY set-ups (Bjorn Helgaas)
Remove unicore32 pci=firmware command line parameter handling (Bjorn Helgaas)
Support I/O resources when parsing host bridge resources (Jayachandran C)
Add helpers to request/release memory and I/O regions (Johannes Thumshirn)
Use pci_(request|release)_mem_regions (NVMe, lpfc, GenWQE, ethernet/intel, alx) (Johannes Thumshirn)
Extend pci=resource_alignment to specify device/vendor IDs (Koehrer Mathias (ETAS/ESW5))
Add generic pci_bus_claim_resources() (Lorenzo Pieralisi)
Claim bus resources on ARM32 PCI_PROBE_ONLY set-ups (Lorenzo Pieralisi)
Remove ARM32 and ARM64 arch-specific pcibios_enable_device() (Lorenzo Pieralisi)
Add pci_unmap_iospace() to unmap I/O resources (Sinan Kaya)
Remove powerpc __pci_mmap_set_pgprot() (Yinghai Lu)
PCI device hotplug
Allow additional bus numbers for hotplug bridges (Keith Busch)
Ignore interrupts during D3cold (Lukas Wunner)
Power management
Enforce type casting for pci_power_t (Andy Shevchenko)
Don't clear d3cold_allowed for PCIe ports (Mika Westerberg)
Put PCIe ports into D3 during suspend (Mika Westerberg)
Power on bridges before scanning new devices (Mika Westerberg)
Runtime resume bridge before rescan (Mika Westerberg)
Add runtime PM support for PCIe ports (Mika Westerberg)
Remove redundant check of pcie_set_clkpm (Shawn Lin)
Virtualization
Add function 1 DMA alias quirk for Marvell 88SE9182 (Aaron Sierra)
Add DMA alias quirk for Adaptec 3805 (Alex Williamson)
Mark Atheros AR9485 and QCA9882 to avoid bus reset (Chris Blake)
Add ACS quirk for Solarflare SFC9220 (Edward Cree)
MSI
Fix PCI_MSI dependencies (Arnd Bergmann)
Add pci_msix_desc_addr() helper (Christoph Hellwig)
Switch msix_program_entries() to use pci_msix_desc_addr() (Christoph Hellwig)
Make the "entries" argument to pci_enable_msix() optional (Christoph Hellwig)
Provide sensible IRQ vector alloc/free routines (Christoph Hellwig)
Spread interrupt vectors in pci_alloc_irq_vectors() (Christoph Hellwig)
Error Handling
Bind DPC to Root Ports as well as Downstream Ports (Keith Busch)
Remove DPC tristate module option (Keith Busch)
Convert Downstream Port Containment driver to use devm_* functions (Mika Westerberg)
Generic host bridge driver
Select IRQ_DOMAIN (Arnd Bergmann)
Claim bus resources on PCI_PROBE_ONLY set-ups (Lorenzo Pieralisi)
ACPI host bridge driver
Add ARM64 acpi_pci_bus_find_domain_nr() (Tomasz Nowicki)
Add ARM64 ACPI support for legacy IRQs parsing and consolidation with DT code (Tomasz Nowicki)
Implement ARM64 AML accessors for PCI_Config region (Tomasz Nowicki)
Support ARM64 ACPI-based PCI host controller (Tomasz Nowicki)
Altera host bridge driver
Check link status before retrain link (Ley Foon Tan)
Poll for link up status after retraining the link (Ley Foon Tan)
Axis ARTPEC-6 host bridge driver
Add PCI_MSI_IRQ_DOMAIN dependency (Arnd Bergmann)
Add DT binding for Axis ARTPEC-6 PCIe controller (Niklas Cassel)
Add Axis ARTPEC-6 PCIe controller driver (Niklas Cassel)
Intel VMD host bridge driver
Use lock save/restore in interrupt enable path (Jon Derrick)
Select device dma ops to override (Keith Busch)
Initialize list item in IRQ disable (Keith Busch)
Use x86_vector_domain as parent domain (Keith Busch)
Separate MSI and MSI-X vector sharing (Keith Busch)
Marvell Aardvark host bridge driver
Add DT binding for the Aardvark PCIe controller (Thomas Petazzoni)
Add Aardvark PCI host controller driver (Thomas Petazzoni)
Add Aardvark PCIe support for Armada 3700 (Thomas Petazzoni)
Microsoft Hyper-V host bridge driver
Fix interrupt cleanup path (Cathy Avery)
Don't leak buffer in hv_pci_onchannelcallback() (Vitaly Kuznetsov)
Handle all pending messages in hv_pci_onchannelcallback() (Vitaly Kuznetsov)
NVIDIA Tegra host bridge driver
Program PADS_REFCLK_CFG* always, not just on legacy SoCs (Stephen Warren)
Program PADS_REFCLK_CFG* registers with per-SoC values (Stephen Warren)
Use lower-case hex consistently for register definitions (Thierry Reding)
Use generic pci_remap_iospace() rather than ARM32-specific one (Thierry Reding)
Stop setting pcibios_min_mem (Thierry Reding)
Renesas R-Car host bridge driver
Drop gen2 dummy I/O port region (Bjorn Helgaas)
TI DRA7xx host bridge driver
Fix return value in case of error (Christophe JAILLET)
Xilinx AXI host bridge driver
Fix return value in case of error (Christophe JAILLET)
Miscellaneous
Make bus_attr_resource_alignment static (Ben Dooks)
Include <asm/dma.h> for isa_dma_bridge_buggy (Ben Dooks)
MAINTAINERS: Add file patterns for PCI device tree bindings (Geert Uytterhoeven)
Make host bridge drivers explicitly non-modular (Paul Gortmaker)
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Merge tag 'pci-v4.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
"Highlights:
- ARM64 support for ACPI host bridges
- new drivers for Axis ARTPEC-6 and Marvell Aardvark
- new pci_alloc_irq_vectors() interface for MSI-X, MSI, legacy INTx
- pci_resource_to_user() cleanup (more to come)
Detailed summary:
Enumeration:
- Move ecam.h to linux/include/pci-ecam.h (Jayachandran C)
- Add parent device field to ECAM struct pci_config_window (Jayachandran C)
- Add generic MCFG table handling (Tomasz Nowicki)
- Refactor pci_bus_assign_domain_nr() for CONFIG_PCI_DOMAINS_GENERIC (Tomasz Nowicki)
- Factor DT-specific pci_bus_find_domain_nr() code out (Tomasz Nowicki)
Resource management:
- Add devm_request_pci_bus_resources() (Bjorn Helgaas)
- Unify pci_resource_to_user() declarations (Bjorn Helgaas)
- Implement pci_resource_to_user() with pcibios_resource_to_bus() (microblaze, powerpc, sparc) (Bjorn Helgaas)
- Request host bridge window resources (designware, iproc, rcar, xgene, xilinx, xilinx-nwl) (Bjorn Helgaas)
- Make PCI I/O space optional on ARM32 (Bjorn Helgaas)
- Ignore write combining when mapping I/O port space (Bjorn Helgaas)
- Claim bus resources on MIPS PCI_PROBE_ONLY set-ups (Bjorn Helgaas)
- Remove unicore32 pci=firmware command line parameter handling (Bjorn Helgaas)
- Support I/O resources when parsing host bridge resources (Jayachandran C)
- Add helpers to request/release memory and I/O regions (Johannes Thumshirn)
- Use pci_(request|release)_mem_regions (NVMe, lpfc, GenWQE, ethernet/intel, alx) (Johannes Thumshirn)
- Extend pci=resource_alignment to specify device/vendor IDs (Koehrer Mathias (ETAS/ESW5))
- Add generic pci_bus_claim_resources() (Lorenzo Pieralisi)
- Claim bus resources on ARM32 PCI_PROBE_ONLY set-ups (Lorenzo Pieralisi)
- Remove ARM32 and ARM64 arch-specific pcibios_enable_device() (Lorenzo Pieralisi)
- Add pci_unmap_iospace() to unmap I/O resources (Sinan Kaya)
- Remove powerpc __pci_mmap_set_pgprot() (Yinghai Lu)
PCI device hotplug:
- Allow additional bus numbers for hotplug bridges (Keith Busch)
- Ignore interrupts during D3cold (Lukas Wunner)
Power management:
- Enforce type casting for pci_power_t (Andy Shevchenko)
- Don't clear d3cold_allowed for PCIe ports (Mika Westerberg)
- Put PCIe ports into D3 during suspend (Mika Westerberg)
- Power on bridges before scanning new devices (Mika Westerberg)
- Runtime resume bridge before rescan (Mika Westerberg)
- Add runtime PM support for PCIe ports (Mika Westerberg)
- Remove redundant check of pcie_set_clkpm (Shawn Lin)
Virtualization:
- Add function 1 DMA alias quirk for Marvell 88SE9182 (Aaron Sierra)
- Add DMA alias quirk for Adaptec 3805 (Alex Williamson)
- Mark Atheros AR9485 and QCA9882 to avoid bus reset (Chris Blake)
- Add ACS quirk for Solarflare SFC9220 (Edward Cree)
MSI:
- Fix PCI_MSI dependencies (Arnd Bergmann)
- Add pci_msix_desc_addr() helper (Christoph Hellwig)
- Switch msix_program_entries() to use pci_msix_desc_addr() (Christoph Hellwig)
- Make the "entries" argument to pci_enable_msix() optional (Christoph Hellwig)
- Provide sensible IRQ vector alloc/free routines (Christoph Hellwig)
- Spread interrupt vectors in pci_alloc_irq_vectors() (Christoph Hellwig)
Error Handling:
- Bind DPC to Root Ports as well as Downstream Ports (Keith Busch)
- Remove DPC tristate module option (Keith Busch)
- Convert Downstream Port Containment driver to use devm_* functions (Mika Westerberg)
Generic host bridge driver:
- Select IRQ_DOMAIN (Arnd Bergmann)
- Claim bus resources on PCI_PROBE_ONLY set-ups (Lorenzo Pieralisi)
ACPI host bridge driver:
- Add ARM64 acpi_pci_bus_find_domain_nr() (Tomasz Nowicki)
- Add ARM64 ACPI support for legacy IRQs parsing and consolidation with DT code (Tomasz Nowicki)
- Implement ARM64 AML accessors for PCI_Config region (Tomasz Nowicki)
- Support ARM64 ACPI-based PCI host controller (Tomasz Nowicki)
Altera host bridge driver:
- Check link status before retrain link (Ley Foon Tan)
- Poll for link up status after retraining the link (Ley Foon Tan)
Axis ARTPEC-6 host bridge driver:
- Add PCI_MSI_IRQ_DOMAIN dependency (Arnd Bergmann)
- Add DT binding for Axis ARTPEC-6 PCIe controller (Niklas Cassel)
- Add Axis ARTPEC-6 PCIe controller driver (Niklas Cassel)
Intel VMD host bridge driver:
- Use lock save/restore in interrupt enable path (Jon Derrick)
- Select device dma ops to override (Keith Busch)
- Initialize list item in IRQ disable (Keith Busch)
- Use x86_vector_domain as parent domain (Keith Busch)
- Separate MSI and MSI-X vector sharing (Keith Busch)
Marvell Aardvark host bridge driver:
- Add DT binding for the Aardvark PCIe controller (Thomas Petazzoni)
- Add Aardvark PCI host controller driver (Thomas Petazzoni)
- Add Aardvark PCIe support for Armada 3700 (Thomas Petazzoni)
Microsoft Hyper-V host bridge driver:
- Fix interrupt cleanup path (Cathy Avery)
- Don't leak buffer in hv_pci_onchannelcallback() (Vitaly Kuznetsov)
- Handle all pending messages in hv_pci_onchannelcallback() (Vitaly Kuznetsov)
NVIDIA Tegra host bridge driver:
- Program PADS_REFCLK_CFG* always, not just on legacy SoCs (Stephen Warren)
- Program PADS_REFCLK_CFG* registers with per-SoC values (Stephen Warren)
- Use lower-case hex consistently for register definitions (Thierry Reding)
- Use generic pci_remap_iospace() rather than ARM32-specific one (Thierry Reding)
- Stop setting pcibios_min_mem (Thierry Reding)
Renesas R-Car host bridge driver:
- Drop gen2 dummy I/O port region (Bjorn Helgaas)
TI DRA7xx host bridge driver:
- Fix return value in case of error (Christophe JAILLET)
Xilinx AXI host bridge driver:
- Fix return value in case of error (Christophe JAILLET)
Miscellaneous:
- Make bus_attr_resource_alignment static (Ben Dooks)
- Include <asm/dma.h> for isa_dma_bridge_buggy (Ben Dooks)
- MAINTAINERS: Add file patterns for PCI device tree bindings (Geert Uytterhoeven)
- Make host bridge drivers explicitly non-modular (Paul Gortmaker)"
* tag 'pci-v4.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (125 commits)
PCI: xgene: Make explicitly non-modular
PCI: thunder-pem: Make explicitly non-modular
PCI: thunder-ecam: Make explicitly non-modular
PCI: tegra: Make explicitly non-modular
PCI: rcar-gen2: Make explicitly non-modular
PCI: rcar: Make explicitly non-modular
PCI: mvebu: Make explicitly non-modular
PCI: layerscape: Make explicitly non-modular
PCI: keystone: Make explicitly non-modular
PCI: hisi: Make explicitly non-modular
PCI: generic: Make explicitly non-modular
PCI: designware-plat: Make it explicitly non-modular
PCI: artpec6: Make explicitly non-modular
PCI: armada8k: Make explicitly non-modular
PCI: artpec: Add PCI_MSI_IRQ_DOMAIN dependency
PCI: Add ACS quirk for Solarflare SFC9220
arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700
PCI: aardvark: Add Aardvark PCI host controller driver
dt-bindings: add DT binding for the Aardvark PCIe controller
PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values
...
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