2 Commits

Author	SHA1	Message	Date
Chen-Yu Tsai	845d6b0ff9	clk: sunxi-ng: gate: Support common pre-dividers ... Some clock gates have a pre-divider between the source input and the gate itself. A notable example is the HSIC 12 MHz clock found on the A83T, which has the 24 MHz main oscillator as its input, and a /2 pre-divider. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>	2017-03-06 10:25:56 +01:00
Maxime Ripard	1a7e7c388d	clk: sunxi-ng: Add gate clock support ... Some clocks in the Allwinner SoCs clocks unit are just simple gates. Add support for those clocks. Since it's a feature that can also be found in more complex clocks, provide a bunch of helpers that can be reused later on. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-5-maxime.ripard@free-electrons.com	2016-07-08 18:04:38 -07:00