mirror of https://gitee.com/openkylin/linux.git
1148 Commits
| Author | SHA1 | Message | Date |
|---|---|---|---|
Linus Torvalds
|
03ffbcdd78 |
Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner:
"The irq department delivers:
- Expand the generic infrastructure handling the irq migration on CPU
hotplug and convert X86 over to it. (Thomas Gleixner)
Aside of consolidating code this is a preparatory change for:
- Finalizing the affinity management for multi-queue devices. The
main change here is to shut down interrupts which are affine to a
outgoing CPU and reenabling them when the CPU comes online again.
That avoids moving interrupts pointlessly around and breaking and
reestablishing affinities for no value. (Christoph Hellwig)
Note: This contains also the BLOCK-MQ and NVME changes which depend
on the rework of the irq core infrastructure. Jens acked them and
agreed that they should go with the irq changes.
- Consolidation of irq domain code (Marc Zyngier)
- State tracking consolidation in the core code (Jeffy Chen)
- Add debug infrastructure for hierarchical irq domains (Thomas
Gleixner)
- Infrastructure enhancement for managing generic interrupt chips via
devmem (Bartosz Golaszewski)
- Constification work all over the place (Tobias Klauser)
- Two new interrupt controller drivers for MVEBU (Thomas Petazzoni)
- The usual set of fixes, updates and enhancements all over the
place"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (112 commits)
irqchip/or1k-pic: Fix interrupt acknowledgement
irqchip/irq-mvebu-gicp: Allocate enough memory for spi_bitmap
irqchip/gic-v3: Fix out-of-bound access in gic_set_affinity
nvme: Allocate queues for all possible CPUs
blk-mq: Create hctx for each present CPU
blk-mq: Include all present CPUs in the default queue mapping
genirq: Avoid unnecessary low level irq function calls
genirq: Set irq masked state when initializing irq_desc
genirq/timings: Add infrastructure for estimating the next interrupt arrival time
genirq/timings: Add infrastructure to track the interrupt timings
genirq/debugfs: Remove pointless NULL pointer check
irqchip/gic-v3-its: Don't assume GICv3 hardware supports 16bit INTID
irqchip/gic-v3-its: Add ACPI NUMA node mapping
irqchip/gic-v3-its-platform-msi: Make of_device_ids const
irqchip/gic-v3-its: Make of_device_ids const
irqchip/irq-mvebu-icu: Add new driver for Marvell ICU
irqchip/irq-mvebu-gicp: Add new driver for Marvell GICP
dt-bindings/interrupt-controller: Add DT binding for the Marvell ICU
genirq/irqdomain: Remove auto-recursive hierarchy support
irqchip/MSI: Use irq_domain_update_bus_token instead of an open coded access
...
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Thomas Petazzoni
|
e0de91a977 |
irqchip/irq-mvebu-icu: Add new driver for Marvell ICU
The Marvell ICU unit is found in the CP110 block of the Marvell Armada 7K and 8K SoCs. It collects the wired interrupts of the devices located in the CP110 and turns them into SPI interrupts in the GIC located in the AP806 side of the SoC, by using a memory transaction. Until now, the ICU was configured in a static fashion by the firmware, and Linux was relying on this static configuration. By having Linux configure the ICU, we are more flexible, and we can allocate dynamically the GIC SPI interrupts only for devices that are actually in use. The driver was initially written by Hanna Hawa <hannah@marvell.com>. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |
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Chen-Yu Tsai
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d85da227c3 |
clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock. As such we need to be able to describe this relationship in the device tree. Export the PLL_PERIPH0 clock so we can reference it in the PRCM node. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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Chen-Yu Tsai
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c4be8c68e6 |
clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock. As such we need to be able to describe this relationship in the device tree. Export the PLL_PERIPH0 clock so we can reference it in the PRCM node. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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Linus Torvalds
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b5a53b61a2 |
Sort of on the quieter side this time, which is probably due more
to me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core, mostly
small non-critical fixes here and there as well as driver updates for new
and existing hardware support. The biggest things are the TI clk driver
rework to lay the groundwork for clkctrl support in the next merge window
and the AmLogic audio/graphics clk support.
Core:
* clk_possible_parents debugfs file so we know which parents a clk
could possibly have
* Fix to make clk rate change notifiers stop on the first failure instead
of continuing
New Drivers:
* Mediatek MT6797 SoCs
* hi655x PMIC clks
* AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
* Allwinner H5 SoCs and PRCM hardware
Updates:
* Nvidia Tegra T210 cleanups and non-critical fixes
* TI OMAP cleanups in preparation for clkctrl support
* Trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
* ZTE zx296718 SoC VGA clks
* Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
* Support for IDT VersaClock 5P49V5935
* Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Sort of on the quieter side this time, which is probably due more to
me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core,
mostly small non-critical fixes here and there as well as driver
updates for new and existing hardware support.
The biggest things are the TI clk driver rework to lay the groundwork
for clkctrl support in the next merge window and the AmLogic
audio/graphics clk support.
Core:
- clk_possible_parents debugfs file so we know which parents a clk
could possibly have
- Fix to make clk rate change notifiers stop on the first failure
instead of continuing
New Drivers:
- Mediatek MT6797 SoCs
- hi655x PMIC clks
- AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
- Allwinner H5 SoCs and PRCM hardware
Updates:
- Nvidia Tegra T210 cleanups and non-critical fixes
- TI OMAP cleanups in preparation for clkctrl support
- trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
- ZTE zx296718 SoC VGA clks
- Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
- IDT VersaClock 5P49V5935 support
- Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3
support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits)
clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
clk: ti: divider: try to fix ti_clk_register_divider
clk: mvebu: Use kcalloc() in two functions
clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
clk: nomadik: Delete error messages for a failed memory allocation in two functions
clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
clk: Improve a size determination in two functions
clk: Replace four seq_printf() calls by seq_putc()
clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
reset: mediatek: Add MT2701 ethsys reset controller include file
clk: mediatek: add mt2701 ethernet reset
clk: hi6220: Add the hi655x's pmic clock
clk: ti: fix building without legacy omap3
clk: ti: fix linker error with !SOC_OMAP4
clk: hi3620: Fix a typo in one variable name
clk: hi3620: Delete error messages for a failed memory allocation in two functions
clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
...
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Linus Torvalds
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c6778ff813 |
ARM: 64-bit DT updates
Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller
changes, but also some new platforms that are worth mentioning:
* Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook
Plus (Kevin)
* Orange Pi PC2 (Allwinner H5)
* Freescale LS2088A and LS1088A SoCs
* Expanded support for Nvidia Tegra186 (and Jetson TX2)
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Olof Johansson:
"Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
of smaller changes, but also some new platforms that are worth
mentioning:
- Rockchip RK3399 platforms for Chromebooks, including Samsung
Chromebook Plus (Kevin)
- Orange Pi PC2 (Allwinner H5)
- Freescale LS2088A and LS1088A SoCs
- Expanded support for Nvidia Tegra186 (and Jetson TX2)"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
arm64: dts: Add basic DT to support Spreadtrum's SP9860G
arm64: dts: exynos: Use - instead of @ for DT OPP entries
arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
arm64: dts: juno: add information about L1 and L2 caches
arm64: dts: juno: fix few unit address format warnings
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
...
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Linus Torvalds
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0160e00ae8 |
ARM: SoC driver updates
Driver updates for ARM SoCs. * Reset subsystem, merged through arm-soc by tradition: - Make bool drivers explicitly non-modular - New support for i.MX7 and Arria10 reset controllers * PATA driver for Palmchip BK371 (acked by Tejun) * Power domain drivers for i.MX (GPC, GPCv2) - Moved out of mach-imx for GPC - Bunch of tweaks, fixes, etc * PMC support for Tegra186 * SoC detection support for Renesas RZ/G1H and RZ/G1N * Move Tegra flow controller driver from mach directory to drivers/soc - (Power management / CPU power driver) * Misc smaller tweaks for other platforms -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZEAZuAAoJEIwa5zzehBx3jCEP/1dcXY746rQoOMUDPyWF5+SZ w0l8dHUQhu4WjNGryfb9DbyiE3d6xlvPVzr9AJeAg6c5I+iikgeogS0XHNpWCU96 FR1Ftb6zo8DIaGognBL9bK5HM7NXjd/EKBkMk0Ggs9/NRFUnakkbpdfivsl2BACx mCGo15+kbgQSQsMJtd5/KfsgY5h7lXJG0fZ8LV5E1E5BSa/AofZtKVgCKfhbd0zV gQqm7xfxtURHtucc7MYNEoKNk5rlrZhOlG6DdG0d6+rscCBrmL1I5giqm8y24+wW z+JJuk21+oVtltLz09JuX51xur3CGyJ+qNJdRPE1P1Udn7wj5zA+ew9qqJi1cgNf 63tBxooBpH6R8dGcOfjKECD6lBBqBr/Dd8ReWbMyn0XF1HMAxgpfPtExu9WcDzGu 9Fr/shUiEA3jqhbzSy6DCHugpnHPdHPyY64MqzisgOEVsituQ7MSefTIGSNusDlk K36I7j93mDAF5y2fTXqbjZKoRuu6KCySvGDXzBqGwhcNzUQk14iPwjtMDZ/l9Raj sQJCUxHntUovHs+VTCwS7ahqZyn0VRNx2bt1aJXNHKzuUovpA9/X5X9HCRZJDovB 0bCGQZ124+H/VsWvSjVtIh7oknU3vSQJPxS6KLKoi3rvywuqW562lGjCTqvjBJKD FMZ5NA8VoWXM2rgTDOyx =B43K -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs: Reset subsystem, merged through arm-soc by tradition: - Make bool drivers explicitly non-modular - New support for i.MX7 and Arria10 reset controllers PATA driver for Palmchip BK371 (acked by Tejun) Power domain drivers for i.MX (GPC, GPCv2) - Moved out of mach-imx for GPC - Bunch of tweaks, fixes, etc PMC support for Tegra186 SoC detection support for Renesas RZ/G1H and RZ/G1N Move Tegra flow controller driver from mach directory to drivers/soc - (Power management / CPU power driver) Misc smaller tweaks for other platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) soc: pm-domain: Fix the mangled urls soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0 soc: renesas: rcar-sysc: Add support for fixing up power area tables soc: renesas: Register SoC device early soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible soc: imx: gpc: add defines for domain index soc: imx: Add GPCv2 power gating driver dt-bindings: Add GPCv2 power gating driver ARM/clk: move the ICST library to drivers/clk ARM: plat-versatile: remove stale clock header ARM: keystone: Drop PM domain support for k2g soc: ti: Add ti_sci_pm_domains driver dt-bindings: Add TI SCI PM Domains PM / Domains: Do not check if simple providers have phandle cells PM / Domains: Add generic data pointer to genpd data struct soc/tegra: Add initial flowctrl support for Tegra132/210 soc/tegra: flowctrl: Add basic platform driver soc/tegra: Move Tegra flowctrl driver ARM: tegra: Remove unnecessary inclusion of flowctrl header ... |
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Linus Torvalds
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85d604902e |
ARM: Device-tree updates
Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved over
from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288 SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using arm/
and arm64/ as include prefixes. This will avoid other local hacks such as
per-file links between the two arch trees (this broke for external mirroring
of DT contents). Now they can just provide their own appropriate dt-include
hierarcy per platform.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM Device-tree updates from Olof Johansson:
"Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved
over from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288
SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology
DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more
description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using
arm/ and arm64/ as include prefixes. This will avoid other local hacks
such as per-file links between the two arch trees (this broke for
external mirroring of DT contents). Now they can just provide their
own appropriate dt-include hierarcy per platform"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (349 commits)
ARM: dts: exynos: Use - instead of @ for DT OPP entries
arm: spear6xx: add DT description of the ADC on SPEAr600
arm: spear6xx: remove unneeded pinctrl properties in spear600-evb
arm: spear6xx: switch spear600-evb to the new flash partition DT binding
arm: spear6xx: fix spaces in spear600-evb.dts
arm: spear6xx: use node labels in spear600-evb.dts
arm: spear6xx: add labels to various nodes in spear600.dtsi
ARM: dts: vexpress: fix few unit address format warnings
ARM: dts: at91: sama5d3_xplained: not all ADC channels are available
ARM: dts: at91: sama5d3_xplained: fix ADC vref
ARM: dts: at91: add envelope detector mux to the Axentia TSE-850
ARM: dts: armada-38x: label USB and SATA nodes
ARM: dts: imx6q-utilite-pro: add hpd gpio
ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply
ARM: dts: imx6qdl-sabresd: Set LDO regulator supply
ARM: dts: imx: add Gateworks Ventana GW5903 support
ARM: dts: i.MX25: add AIPS control registers
ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators
ARM: dts: imx7-colibri: remove 1.8V fixed regulator
ARM: dts: imx7-colibri: allow to disable Ethernet rail
...
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Linus Torvalds
|
2bd8040174 |
This is the bulk of GPIO changes for the v4.12 kernel cycle:
Core changes
- Return NULL from gpiod_get_optional() when GPIOLIB is disabled.
This was a much discussed change. It affects use cases where people
write drivers that might or might not be using GPIO resources.
I have decided that this is the lesser evil right now.
- Make gpiod_count() behave consistently across different hardware
descriptions.
- Fix the syntax around open drain/open source to not infer active
high/low semantics.
New drivers
- A new single-register fixed-direction framework driver for hardware
that have lines controlled by a single register that just work in
one direction (out or in), including IRQ support.
- Support the Fintek F71889A GPIO SuperIO controller.
- Support the National NI 169445 MMIO GPIO.
- Support for the X-Gene derivative of the DWC GPIO controller
- Support for the Rohm BD9571MWV-M PMIC GPIO controller.
- Refactor the Gemini GPIO driver to a generic Faraday FTGPIO driver
and replace both the Gemini and the Moxa ART custom drivers with
this driver.
Driver improvements
- A whole slew of drivers have their spinlocks chaned to raw spinlocks
as they provide irqchips, and thus we are progressing on realtime
compliance.
- Use devm_irq_alloc_descs() in a slew of drivers, getting managed
resources.
- Support for the embedded PWM controller inside the MVEBU driver.
- Debounce, open source and open drain support for the Aspeed driver.
- Misc smaller fixes like spelling and syntax and whatnot.
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Merge tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.12 kernel cycle.
Core changes:
- Return NULL from gpiod_get_optional() when GPIOLIB is disabled.
This was a much discussed change. It affects use cases where people
write drivers that might or might not be using GPIO resources. I
have decided that this is the lesser evil right now.
- Make gpiod_count() behave consistently across different hardware
descriptions.
- Fix the syntax around open drain/open source to not infer active
high/low semantics.
New drivers:
- A new single-register fixed-direction framework driver for hardware
that have lines controlled by a single register that just work in
one direction (out or in), including IRQ support.
- Support the Fintek F71889A GPIO SuperIO controller.
- Support the National NI 169445 MMIO GPIO.
- Support for the X-Gene derivative of the DWC GPIO controller
- Support for the Rohm BD9571MWV-M PMIC GPIO controller.
- Refactor the Gemini GPIO driver to a generic Faraday FTGPIO driver
and replace both the Gemini and the Moxa ART custom drivers with
this driver.
Driver improvements:
- A whole slew of drivers have their spinlocks chaned to raw
spinlocks as they provide irqchips, and thus we are progressing on
realtime compliance.
- Use devm_irq_alloc_descs() in a slew of drivers, getting managed
resources.
- Support for the embedded PWM controller inside the MVEBU driver.
- Debounce, open source and open drain support for the Aspeed driver.
- Misc smaller fixes like spelling and syntax and whatnot"
* tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (77 commits)
gpio: f7188x: Add a missing break
gpio: omap: return error if requested debounce time is not possible
gpio: Add ROHM BD9571MWV-M PMIC GPIO driver
gpio: gpio-wcove: fix GPIO IRQ status mask
gpio: DT bindings, move tca9554 from pcf857x to pca953x
gpio: move tca9554 from pcf857x to pca953x
gpio: arizona: Correct check whether the pin is an input
gpio: Add XRA1403 DTS binding documentation
dt-bindings: add exar to vendor prefixes list
gpio: gpio-wcove: fix irq pending status bit width
gpio: dwapb: use dwapb_read instead of readl_relaxed
gpio: aspeed: Add open-source and open-drain support
gpio: aspeed: Add debounce support
gpio: aspeed: dt: Add optional clocks property
gpio: aspeed: dt: Fix description alignment in bindings document
gpio: mvebu: Add limited PWM support
gpio: Use unsigned int for interrupt numbers
gpio: f7188x: Add F71889A GPIO support.
gpio: core: Decouple open drain/source flag with active low/high
gpio: arizona: Correct handling for reading input GPIOs
...
|
|
|
Linus Torvalds
|
68fed41e0f |
This is the bulk of pin control changes for the v4.12 cycle:
Core changes:
- Add bi-directional and output-enable pin configurations to
the generic bindings and generic pin controlling core.
New drivers or subdrivers:
- Armada 37xx SoC pin controller and GPIO support.
- Axis ARTPEC-6 SoC pin controller support.
- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.
- Rockchip RK3328 support.
- Renesas R-Car H3 ES2.0 support.
- STM32F469 support in the STM32 driver.
- Aspeed G4 and G5 pin controller support.
Improvements:
- A whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.
- Switch meson driver to get the GPIO ranges from the device
tree.
- Input schmitt trigger support on the Rockchip driver.
- Enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.
- Name the Qualcomm QDF2xxx GPIO lines.
- Support GMMR GPIO regions on the Intel Cherryview. This
fixes a serialization problem on these platforms.
- Pad retention support for the Samsung Exynos 5433.
- Handle suspend-to-ram in the AT91-pio4 driver.
- Pin configuration support in the Aspeed driver.
Cleanups:
- The final name of Rockchip RK1108 was RV1108 so rename the
driver and variables to stay consistent.
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Merge tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.12 cycle.
The extra week before the merge window actually resulted in some of
the type of fixes that usually arrive after the merge window already
starting to trickle in from eager developers using -next, I'm
impressed.
I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal
with the onset of Samsung patches. It works great.
Apart from that it is a boring round, just incremental updates and
fixes all over the place, no serious core changes or anything exciting
like that. The most pleasing to see is Julia Cartwrights work to audit
the irqchip-providing drivers for realtime locking compliance. It's
one of those "I should really get around to looking into that" things
that have been on my TODO list since forever.
Summary:
Core changes:
- add bi-directional and output-enable pin configurations to the
generic bindings and generic pin controlling core.
New drivers or subdrivers:
- Armada 37xx SoC pin controller and GPIO support.
- Axis ARTPEC-6 SoC pin controller support.
- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.
- Rockchip RK3328 support.
- Renesas R-Car H3 ES2.0 support.
- STM32F469 support in the STM32 driver.
- Aspeed G4 and G5 pin controller support.
Improvements:
- a whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.
- switch meson driver to get the GPIO ranges from the device tree.
- input schmitt trigger support on the Rockchip driver.
- enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.
- name the Qualcomm QDF2xxx GPIO lines.
- support GMMR GPIO regions on the Intel Cherryview. This fixes a
serialization problem on these platforms.
- pad retention support for the Samsung Exynos 5433.
- handle suspend-to-ram in the AT91-pio4 driver.
- pin configuration support in the Aspeed driver.
Cleanups:
- the final name of Rockchip RK1108 was RV1108 so rename the driver
and variables to stay consistent"
* tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl: mediatek: Add missing pinctrl bindings for mt7623
pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()
pinctrl: artpec6: Remove .owner field for driver
pinctrl: tegra: xusb: Silence sparse warnings
ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller"
pinctrl: make artpec6 explicitly non-modular
pinctrl: aspeed: g5: Add pinconf support
pinctrl: aspeed: g4: Add pinconf support
pinctrl: aspeed: Add core pinconf support
pinctrl: aspeed: Document pinconf in devicetree bindings
pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl
pinctrl: stm32: Add STM32F469 MCU support
Documentation: dt: Remove ngpios from stm32-pinctrl binding
pinctrl: stm32: replace device_initcall() with arch_initcall()
pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
pinctrl: armada-37xx: Add gpio support
pinctrl: armada-37xx: Add pin controller support for Armada 37xx
pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
pinctrl: core: Make pinctrl_init_controller() static
pinctrl: generic: Add bi-directional and output-enable
...
|
|
|
Sean Wang
|
1aa2faf52f |
pinctrl: mediatek: Add missing pinctrl bindings for mt7623
Add missing pinctrl binding these which would be used in devicetree related files. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
|
|
Arnd Bergmann
|
b6942b68f8 |
Merge branch 'for_4.12/soc-pmdomain-p2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers
Pull "Keystone mangled URLs fixed" from Santosh Shilimkar * 'for_4.12/soc-pmdomain-p2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: soc: pm-domain: Fix the mangled urls |
|
|
Santosh Shilimkar
|
7574f67eb4 |
soc: pm-domain: Fix the mangled urls
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org> |
|
|
John Crispin
|
7c2adaf110 |
reset: mediatek: Add MT2701 ethsys reset controller include file
Add the missing reset bits of the ethsys core to the mt2701-reset include file, so that we can reference them from within a devicetree file. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
|
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Stephen Boyd
|
ddc34434e4 |
Merge branch 'clk-mt6797' into clk-next
* clk-mt6797: clk: mediatek: add mt6797 clock IDs |
|
|
Mars Cheng
|
df0225a45a |
clk: mediatek: add mt6797 clock IDs
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
|
|
Stephen Boyd
|
8062b4aafc |
Allwinner clock patches for 4.12
Support for the new H5 SoC and the PRCM block found in a number of SoCs as well, plus the usual chunk of fixes and minor enhancements. -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJY5feFAAoJEBx+YmzsjxAgzicP/2zx3xYRy5C69wI5IRxAMDjg 3AGgZgVXH/ir9CHVW7oGhBo9VdgbMdTZAJCA6WKBVjpjSsRkEVeEeRMTKAPbBBll u5bFpQ2hX4WnGFlILAfXLtJJ39pEPZnHUN+ew3umR7xXMm76o7vB8Z59fd9qkgpP wXwwZPDywtLusawxDjci0Wrzek8MHkFA6WwXnlnp82CbG+tLOe+o/x9kv125x9fT td2POgaoG2FEBL1GyfqY0uzmNKs8oHwgbWmepsu5xFmmLYS4cwVHHIMAm3iOEmF+ tPZfeYxYVDY3cDfPhyj7/in3ej5SM63ZG6YSZjd2z/rXhGrcCNCmhFEwk9ie81oT uHQ6B7K4hAtV1zJ7wZZJD/vqZewOaTcb/V9S7D1bGsBLcBrswOp7yaf2ECnhSQu0 C20Vp9xFdmSTReGIpD6+HCVLYSU0DHOVx0D/+dPOTtrfJR98xiEvUPekuo9yRmuc MIBFzRJ83x9Ee5PS2jBju2V7VaGD08Q6R3JLDkCgUTaBTZq/jlNGc/9DD6llFM/E idQ6j9dJnSzU6C4QVClIxBQHJu4kGNUUeWAXqxBTEh7jUg5bnKjUXox0W44RzqPP j/ZWB60xLD/FdbaGQdxU72uFpok9Uc2fySvQqAwePe5F2j27IIMOKu/CpFmefc17 Ww+4lw2nbR3dypCxt6C7 =V49g -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock patches for 4.12 from Maxime Ripard: Support for the new H5 SoC and the PRCM block found in a number of SoCs as well, plus the usual chunk of fixes and minor enhancements. * tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Display index when clock registration fails clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks clk: sunxi-ng: mult: Support PLL lock detection clk: sunxi-ng: add support for PRCM CCUs dt-bindings: update device tree binding for Allwinner PRCM CCUs clk: sunxi-ng: sun5i: Fix mux width for csi clock clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver clk: sunxi-ng: gate: Support common pre-dividers |
|
|
Olof Johansson
|
32d8b52b90 |
Renesas ARM Based SoC Sysc Updates for v4.12
* Add support for R-Car H3 ES2.0 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJY59ObAAoJENfPZGlqN0++mmAP/iLPRVjE0DoqVVQbNeIq4pOI 0HaIU2MZH6cPN2868CBp+8/UsPQXUBtpBRdRsc7+B2gSQteFhEZ8b+tTJ007BohM YO4XSSfwEUedKoPB5N88hleGrXjvUbNBECOeD5XSOX3X9qQLDUkzpgDgfL0WPl6D gU3G7IitR2KnBTz5n8XbrdTVccZbafXutj3Sp8pTxd4Yc8ajL8MkxbwTjlGratfw sOUW1zxIv7c9eanfbYZQ3ZGNm++2w/WnqhPBTYfxcBVK95dslWjkxf7HawujeaP7 CihAakoH9QoYsrnyEMbMn4xpCJEYB8U5zaIzyOFHhGCtF5AXUrKFcn1DMpU7sORJ mu4UDUHIugGsu/RdOcOdB/dZ5GcfFtVehDLKtAGdoAwyc6eY9URAwOlOV9abOCtf qWSGHv0dKCVg5fLcuCzXMYd7DxXN1X4A0wj94S6XF5S1/wcWJaOU2uJKPSguoUzW vQt4jIM7TUUK6YAVj0xec40lXf0AuJ4FcXI/9TEnYnmqzOEwZzKzrlMv3xnqp08k jQarhWJLvN23lDAtGOorLJKOZyveXy0E3I9IJT8PgZpGmOlijSRBzhXsN1NeGsYo 663+3feI4Qe5vtu8Obv/vA0BcYHiA+AcEBwWYFAZOGGSM2IucORxX9UAu8XBmtRB FnS/AB2yrsoL9VjKgeYt =m+ef -----END PGP SIGNATURE----- Merge tag 'renesas-sysc-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Renesas ARM Based SoC Sysc Updates for v4.12 * Add support for R-Car H3 ES2.0 * tag 'renesas-sysc-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0 soc: renesas: rcar-sysc: Add support for fixing up power area tables soc: renesas: Register SoC device early base: soc: Allow early registration of a single SoC device base: soc: Let soc_device_match() return no match when called too early Signed-off-by: Olof Johansson <olof@lixom.net> |
|
|
Olof Johansson
|
a51ed6cfb2 |
Second Round of Renesas ARM Based SoC DT Updates for v4.12
Corrections: * Correct clock frequency of X2 DU clock input for r8a7791/koelsch board * Correct Z clock for r8a7792 SoC * Correct parent of SSI[0-9] clocks for r8a779[013] SoCs * Correct ethernet clock parent on r7s72100 SoC * Correct DU clock for r8a7794/silk board Cleanups: * Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs Enhancements: * Enable rtc r7s72100/genmai board * Add Z2 clock for r8a7794 SoC * Add DU clock for r8a7794 SoC * Add power-domains to SDHI for r8a7794 and r7s72100 SoCs * Add reset control properties for r8a774[35] SoCs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJY57Z+AAoJENfPZGlqN0++410QALS78C/4O3vVj3AXABGTnQBc B0cIlfmw1plyx1g0GhZJZYfZ/8bDjdw4yhu7xz0pttWSyfNZpYS7TMf2Uyf6bWtx lMP3N7HYX12y4d/TKmg/w8zNT/P5sBSuAcDwlbRMAKVJer0ztECHmPLawJesF6Vw 2n0VZZpi1A9n4riJukigbiFkRPNjmQAIDB3Rx1afXeyVtUVwImvBb3vJoZHaYJ+T MWaUQ4N+ve22HNm6k8UxJqglDxf9GO5k+SXppPwqUsZlHF41nuR5zWOWxUQl5SCQ G2OQGLcR0iXPcuiFbb3DScuVtwXlm8AgZNOEOGssukC7JkwTFvwHJWMXFBt4ZlPS yDFxTcCqyUtI4NbcsLO3eIEddzG+07V5UwWQw82LXktY2/rYn0I2jgcoAPh6zVou gkA68FaMZSp2WYMfd9EdppyrxaLGbSSi/g3BQnV3HJgYjGqwtb7QSRVM2tmeMEnp RTrAnmTYfRPm04FYyBlwmw7YaDiia5MHp4f45B2mWcXBDlYqepvxDHCyj1lX2ySL /QmVPGrQGSWEgbLhB1kKzSpI90zZBJMzNWE7GaYhb5dXZW2SpjkcpzhHxLtB2BLR xIHIlQ+RHiS0fOPFll3/wfvGDoN1H+P6nh1kz0BJFeQ7ph9iNNVnD9QOaXqePKqL rlbJMygQXSAQ6A8lNrS0 =N8Dk -----END PGP SIGNATURE----- Merge tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Second Round of Renesas ARM Based SoC DT Updates for v4.12 Corrections: * Correct clock frequency of X2 DU clock input for r8a7791/koelsch board * Correct Z clock for r8a7792 SoC * Correct parent of SSI[0-9] clocks for r8a779[013] SoCs * Correct ethernet clock parent on r7s72100 SoC * Correct DU clock for r8a7794/silk board Cleanups: * Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs Enhancements: * Enable rtc r7s72100/genmai board * Add Z2 clock for r8a7794 SoC * Add DU clock for r8a7794 SoC * Add power-domains to SDHI for r8a7794 and r7s72100 SoCs * Add reset control properties for r8a774[35] SoCs * tag 'renesas-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits) ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name ARM: dts: r8a7790: Drop _clk suffix from external CAN clock node name ARM: dts: genmai: Enable rtc and rtc_x1 clock ARM: dts: rskrza1: add rtc DT support ARM: dts: rskrza1: set rtc_x1 clock value ARM: dts: r7s72100: add rtc to device tree ARM: dts: r7s72100: add RTC_X clock inputs to device tree ARM: dts: r7s72100: add rtc clock to device tree ARM: dts: koelsch: Correct clock frequency of X2 DU clock input ARM: dts: r8a7794: Add Z2 clock ARM: dts: r8a7792: Correct Z clock ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks ARM: dts: r7s72100: fix ethernet clock parent ARM: dts: silk: Correct clock of DU1 ARM: dts: alt: Correct clock of DU1 ARM: dts: r8a7794: Correct clock of DU1 ARM: dts: r8a7794: Add DU1 clock to device tree ARM: dts: r7s72100: add power-domains to sdhi ... Signed-off-by: Olof Johansson <olof@lixom.net> |
|
|
Olof Johansson
|
912c9fbe66 |
i.MX drivers updates for 4.12:
- A series from Lucas Stach which partly rewrites the imx gpc driver
to support multiple power domains, and moves the related code from
imx platform into drivers folder.
- A series from Dong Aisheng which fixes the issues with Lucas' code
changes and improves things.
- Add workaround for i.MX6QP hardware erratum ERR009619 that is PRE
clocks may be stalled during the power up sequencing of the PU power
domain.
- Add imx-gpcv2 driver to support power domains managed by GPCv2 IP
block found on i.MX7 series of SoCs.
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Merge tag 'imx-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers
i.MX drivers updates for 4.12:
- A series from Lucas Stach which partly rewrites the imx gpc driver
to support multiple power domains, and moves the related code from
imx platform into drivers folder.
- A series from Dong Aisheng which fixes the issues with Lucas' code
changes and improves things.
- Add workaround for i.MX6QP hardware erratum ERR009619 that is PRE
clocks may be stalled during the power up sequencing of the PU power
domain.
- Add imx-gpcv2 driver to support power domains managed by GPCv2 IP
block found on i.MX7 series of SoCs.
* tag 'imx-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
soc: imx: gpc: add defines for domain index
soc: imx: Add GPCv2 power gating driver
dt-bindings: Add GPCv2 power gating driver
soc: imx: gpc: remove unnecessary readable_reg callback
dt-bindings: imx-gpc: correct the DOMAIN_INDEX using
soc: imx: gpc: keep PGC_X_CTRL name align with reference manual
soc: imx: gpc: fix comment when power up domain
soc: imx: gpc: fix imx6sl gpc power domain regression
soc: imx: gpc: fix domain_index sanity check issue
soc: imx: gpc: fix the wrong using of regmap cache
soc: imx: gpc: fix gpc clk get error handling
soc: imx: move PGC handling to a new GPC driver
dt-bindings: add multidomain support to i.MX GPC DT binding
Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson
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08fd8c9567 |
ARM64: DT: Hisilicon SoC DT updates for 4.12
- Reset the hi6220 mmc hosts to avoid hang - Add the binding for the hi3798cv200 SoC and the poplar board - Add basic dts files to support the hi3798cv200 poplar board - Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board - Add driver strength MACRO for the hi3660 SoC - Add the pinctrl dtsi file for hikey960 board to configure the pins -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJY66cBAAoJEAvIV27ZiWZcSAAP/3qvcWDNVwc7Rg5JIcbvBP09 mBbcutrHmFVi5Swd3yuTyNErRFliVsdDV3dwanxlXOojqYgE4WpJQFKtXr8obQUa q3yk+gzMIS3+P18dJPU+SFsCwLDaUF4PkiRm3vd4Oc6fgPfqCbWfYcS6jOhbBdzD GWAMp6j/vn3Br3RSFe2NgH43kv2H4efEh0lrKj3wk2mCDF3s69PaMGPLgCfeV1F0 pYwyO/2v4TWuJkO8U7g1XyvK6LRO49mWDKdqhP0hZpr3DJP7T5u9E4bxScBwG2GY ENURvZpl3Kd1thfR9+7FkwNg0Z7Y9hVNI5763JzLusd6pw1y2jDU9oEESpuVi1FH 9dwqloiLuonYSPvAM9XS84CXnguFoqjndf7Z3d9yliS86GRn4g5B5t20rlLtSE+4 o+IcLQy6z6CpDHugTzav3oBsscckEiWsmX0X6Jym23+buzFcHWOPOQldIUUSDDoq 9oct1AxBrQA9F9KspaiWRy38Bwi8qRT5FT+BfBai3y45FeEKdRFUghIwdeqm4F2v 1JulIiPelHUtELAcAEJFRVQzgfSVuGuXCAHVHpgXE018UnNvhfl3/VtUtvLI71wf jukY2JIJsG9r/NHR1uZU8LGN70bNUjHXwuF0R/zh2zwZT+mDgxEe5zOlCbQyYJbt uqVy7+asSKcbOLabW/Ae =5zO6 -----END PGP SIGNATURE----- Merge tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi into next/dt64 ARM64: DT: Hisilicon SoC DT updates for 4.12 - Reset the hi6220 mmc hosts to avoid hang - Add the binding for the hi3798cv200 SoC and the poplar board - Add basic dts files to support the hi3798cv200 poplar board - Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board - Add driver strength MACRO for the hi3660 SoC - Add the pinctrl dtsi file for hikey960 board to configure the pins * tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi: arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board arm64: dts: hisi: add SAS nodes for the hip07 SoC arm64: dts: hisi: add RoCE nodes for the hip07 SoC arm64: dts: hisi: add network related nodes for the hip07 SoC arm64: dts: hisi: add mbigen nodes for the hip07 SoC arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board arm64: dts: hi6220: Reset the mmc hosts Signed-off-by: Olof Johansson <olof@lixom.net> |
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Olof Johansson
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fe8fee6901 |
ARM SOC PM domain support for 4.12
Dave Gerlach (5):
PM / Domains: Add generic data pointer to genpd data struct
PM / Domains: Do not check if simple providers have phandle cells
dt-bindings: Add TI SCI PM Domains
soc: ti: Add ti_sci_pm_domains driver
ARM: keystone: Drop PM domain support for k2g
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Merge tag 'arm-soc-pmdomain' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers
ARM SOC PM domain support for 4.12
Dave Gerlach (5):
PM / Domains: Add generic data pointer to genpd data struct
PM / Domains: Do not check if simple providers have phandle cells
dt-bindings: Add TI SCI PM Domains
soc: ti: Add ti_sci_pm_domains driver
ARM: keystone: Drop PM domain support for k2g
* tag 'arm-soc-pmdomain' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
ARM: keystone: Drop PM domain support for k2g
soc: ti: Add ti_sci_pm_domains driver
dt-bindings: Add TI SCI PM Domains
PM / Domains: Do not check if simple providers have phandle cells
PM / Domains: Add generic data pointer to genpd data struct
Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson
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dd85108475 |
Amlogic 64-bit DT updates for v4.12
- pinctrl: new pins for audio - clocks: more clocks exposed for GFX, audio - new board: Khadas Vim (S905X) - new board: HwaCom AmazeTV (S905X) - ethernet phy: add GPIO resets -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJY5DPWAAoJEFk3GJrT+8ZlieEP/0bGQcMBnjgLIGh49pMDqiUz 1RAmVBeo/1yeq2WjI8a3VsN5W4fuHysH7DWTxI1GA7f9wVblyMBQTqvg2R8tfEVe EAS444Fj6xUzEYmWoBNETHmxWT40o+80B7BYm7zGrRqeQ0QMo7yAWBKHmmJ0nmNv qb/dLqTLbldRwh+5gLvgaH1UK2PdsNE+UHWThP6CPXIBe1WIxggmwDt0ItBlO17S wnBHjh1jzAroS51WVRc2aL0xmBrHgi20BtVxCg7jbQk6I4zDafk59pu1+Xuwaoiv CMWySeQq1wj0uOZ4OtkeTIgd8VuBt8ovcHIB/kpJEmJy8C2d2dkjuBD2IC7Qo3d7 9p3NfE6E1vZZdT4//8i0sVQMX2OEiVWJfM/2hBlV4OLEQ+RR2U5gvUHBxJcnuC1B RHbK/OqZ7GyQZOG5O7OWiF4hG4dOFCCsbkleMcbAlm5BUvLaI6QUTufuQrsNzzvb c3dAuLldsNwBvpSqxYr1mKQ2YNh2M47DSgdut8qDaaPYx6LU4HcCZEVTe2q9Hn1h 46cERmJoVOW40WEjYK/Nv+TpUNKzwF7Bz6fA7dsqb0ehEaHPFWvjD2mpCij60hvc J5dxZDQT8Y1lIkOcLRBdXYFp/NOVQoIAwfGSHleoHzclshILvV/O8hevsZpKFTKh ywM7owJLUAkDDYLIbNxS =/FCW -----END PGP SIGNATURE----- Merge tag 'amlogic-dt64-redo' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64 Amlogic 64-bit DT updates for v4.12 - pinctrl: new pins for audio - clocks: more clocks exposed for GFX, audio - new board: Khadas Vim (S905X) - new board: HwaCom AmazeTV (S905X) - ethernet phy: add GPIO resets * tag 'amlogic-dt64-redo' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (41 commits) ARM64: dts: meson-gx: Add support for HDMI output ARM64: dts: meson-gx: Add shared CMA dma memory pool ARM64: dts: meson-gxbb-odroidc2: Enable SARADC node dt-bindings: clock: gxbb-clkc: Add GXL compatible variant clk: meson-gxbb: Expose GP0 dt-bindings clock id clk: meson-gxbb: Add MALI clock IDS dt-bindings: clk: gxbb: expose i2s output clock gates ARM64: dts: meson-gxl: add spdif output pins ARM64: dts: meson-gxl: add i2s output pins ARM64: dts: meson-gxbb: add spdif output pins ARM64: dts: meson-gxbb: add i2s output pins ARM64: dts: meson-gxbb: Add USB Hub GPIO hog ARM: dts: meson8b: Add gpio-ranges properties ARM: dts: meson8: Add gpio-ranges properties ARM64: dts: meson-gxl: Add gpio-ranges properties ARM64: dts: meson-gxbb: Add gpio-ranges properties ARM64: dts: meson-gx: Add Mali nodes for GXBB and GXL ARM64: dts: meson-gxl: Add missing pinctrl pins groups ARM64: dts: meson-gx: Prepend GX generic compatible like other nodes ARM64: dts: meson-gx: empty line cleanup ... Signed-off-by: Olof Johansson <olof@lixom.net> |
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Olof Johansson
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ed50c4855e |
STM32 DT updates for v4.12, round 1
Highlights: ---------- - ADD RTC support on STM32F746 MCU - Enable RTC on STM32F746 Eval board - Enable clocks on STM32F746 MCU - Enable DMA, pwm1 and pwm3 on STM32F429I Eval - Add support of STM32H743 MCU and his Eval board - Enable USB HS and FS on STM32F469 Disco board -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJY4n6WAAoJEH+ayWryHnCFaXYQAKmOBcBrU2RiZt/tn02lhEJI /BKTjFUBg9CCSMqT8xJvDtCJ3YLUwxqo4HhkvKnTZh7AQ1mSTdVScKrB0Le83271 IOoAFBmCZCn9ShSgclBPiold1q5i7g/hZRagQwNwXHdQXt8GZxhpVzaYgZj7EtQ4 B5ikmQCT9KagPSiY4M6X1pzRPRmqcN6alAYsIO8SoHrFpBXm8/TWqspn5pPhojIM 4oWbGEwAxLR4J86TA2Eu+Yp/8FvGX8+W59tFbarlBPloKueHADZ72MfrTZ72vXf6 y4s4JGctDOiLqRFBR6Pp3i8/F4d2pxtd7GsWHR12Mw8lQGHHkKZWs20vri+s6HiT qkjKWXdV4mwYis4vUB997NOYClbqTbURcUt7uRvFrDXD2gg3TnRGkP5WynEX8njS cnRhJ+1rS3iC2rvNtRGE9aadRRtxXVqVQ1HA2EeBeNGpVgFFPbdhPpt2ZDhC2PLf FRYQnxxVAngionqxNGytwKTHXSsVYufMINPyUZWxqUXN083+HAWemJCUTd6cC1ia I781iAjQDWyQzrG8jQtsEXPT2rSdrouVzu0CG642EDuU81CkAWz8vBkrjPj9m+9g fcd8RhRQTvcz0rePNBq/OLRojA7bVsDBBikAJJh6tCnwil8oJlaJ5DSbORe8J8Ez DlOoNIKk1byGfN6LrxKz =l7eq -----END PGP SIGNATURE----- Merge tag 'stm32-dt-for-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into next/dt STM32 DT updates for v4.12, round 1 Highlights: ---------- - ADD RTC support on STM32F746 MCU - Enable RTC on STM32F746 Eval board - Enable clocks on STM32F746 MCU - Enable DMA, pwm1 and pwm3 on STM32F429I Eval - Add support of STM32H743 MCU and his Eval board - Enable USB HS and FS on STM32F469 Disco board * tag 'stm32-dt-for-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: dt-bindings: Document the STM32 USB OTG DWC2 core binding ARM: dts: stm32: Enable USB HS in FS mode (embedded phy) on stm32f429-disco ARM: dts: stm32: Enable USB FS on stm32f469-disco ARM: dts: stm32: Add USB FS support for STM32F429 MCU ARM: dts: stm32: Add STM32H743 MCU and STM32H743i-EVAL board ARM: dts: stm32: Enable pwm1 and pwm3 on stm32f429i-eval ARM: dts: stm32: Enable dma by default on stm32f4 adc ARM: dts: stm32: enable RTC on stm32746g-eval ARM: dts: stm32: Add RTC support for STM32F746 MCU ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f746 dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include file ARM: dts: stm32: Enable clocks for STM32F746 MCU Signed-off-by: Olof Johansson <olof@lixom.net> |
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Michael Turquette
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0d7a5328db |
Amlogic clock driver updates for v4.12
- meson8: add some new PLLs - new clocks for Mali - misc fixes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJY5CeGAAoJEFk3GJrT+8Zlp8MP/01Po8BB0Hamo3SGIckzHIXn 4yYHnX4kYIGAHw4E1jki0Kz/3TxUSpUm4LWkcYloesPxnXipy2rlYJDhoFF1+QBM A/Y6Tx9G6sTEmk/20HDzof7N1DzfGAdj+NJd3IMXaOIbP8XFBXgdRktB2kSUu0ZM YPvlh5EjkWVhE5I+JqIfxSqAHW9+DOf17rhmch1wEXXMuVbtqPhm/DFd9+Ux+4WF VoQ/dP0QLv0tszruJeI/bEqjgMGe+0feZt49aOpGuFfqVUP4tBs0fwOdjg6ELCrZ Spw5GAewa7delQP8ihnC7n4wiV77k/qulReh4jExCt8s8L8nbkOL1naQlClMJfEb RkoHC4MH0xxc9Q+J2l00DkHR7DgM2BTEUcmPvXkr+WBGJ+fN9gb3iIfJx9uY3DsD W4iCkY+oAB7y4/lfa1LoImbGrrm9PmpXZR24TAkynaL2EOiQ7BtDuZsIFqu53VTn O6UCIiKYlCtXrTzbpP/z6kbQ/8oASVE1hk1rfYSNpLU05KgCBFfS6pZWQDC8hJJv UhK1nfxBrzIxQ130g9oJqFU5uwqheZJ4DLLBo751JLPfAPBI5tftxkHUOYWFA1+s uoHZSDnKNiwnS+krjo2kFREF3etY/Fqp98OP2GYuP5H+MPsL1mIFxX/y/MBsDGwo rH2TqHIyoKSPX5sIvS8I =Tz8Z -----END PGP SIGNATURE----- Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into clk-next Same great taste as the previous pull request, but now with 50% less DT bikeshedding! Amlogic clock driver updates for v4.12 - meson8: add some new PLLs - new clocks for Mali - misc fixes. |
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Michael Turquette
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72be2d5f4a |
clk: tegra: Changes for v4.12-rc1
This contains a bunch of fixes and cleanups, mostly to the Tegra210 clock driver. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAljmyG4THHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zof0WD/wIcN4MZ0oOQ3GzCc0Ou0o4NIsyb6xK rETS84l0hNvzuHvaII9NNdnnqONtJfj1J9bqire16zulNmEmtbwgxsvL25DPcLh1 SaYwEyfE44u3TFnx24bAPP31dn9BhPBZOq/Xvs2prjGnmaCDMF/9vY5H4ej6lIuV 6JZYGzqmDy930DBrJ/13nUDzQuhdXky/f7iFHevFHK/yWOVNLPsA6bOrUVJU/1O4 3vAsKJOpbKIYFAR6EltpgB+WhI++0VOnwGCLMwB8eEjQWPIr38qz2kkkLJYy77DC xS58/T4akY/5Hi+gtHK1WyjMxeQsck4fMFCZkl0KqyHRHAHZKmmoIQc+DBVg+FeM AwplwmgW4Mxlk2D3oaO64Vuuu7tVdTmhJSPAtrl5TJLDgx/FTJjIOauWTLmvp9sl wYNHQ7QS/0kkmr+jgo3HxyQfxgm8PHsSzDoDB6VYPCNad0pFMSQATXD9rrppHudh RtHVtgGv2uX/fg4VJzYK/WdkkvCUG/UQQt+eEzZlGqCGj3t28NTqZPSM7YVwggGW nG/SVqV4wlQpSZuUgdKjANmnDaBiksA5/txhTmly37Sv3woI/aWV0THTFjZhsM4o FYGcv6d1tlX57pfC1WboYNVHg7mC6c2R+Ibvjmrrnt8WgfOQTzrNmK8UsqaLiV9h Fonu4UOyF0yX2Q== =fDsq -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull Tegra clk driver updates from Thierry Reding: This contains a bunch of fixes and cleanups, mostly to the Tegra210 clock driver. * tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits) clk: tegra: Don't reset PLL-CX if it is already enabled clk: tegra: Add missing Tegra210 clocks clk: tegra: Propagate clk_out_x rate to parent clk: tegra: Fix build warnings on Tegra20/Tegra30 clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on clk: tegra: Add SATA seq input control clk: tegra: Add Tegra210 special resets clk: tegra: Rework pll_u clk: tegra: Implement reset control reset clk: tegra: Fix disable unused for clocks sharing enable bit clk: tegra: Handle UTMIPLL IDDQ clk: tegra: Add aclk clk: tegra: Add super clock mux/divider clk: tegra: Define Tegra210 DMIC clocks clk: tegra: Fix constness for peripheral clocks clk: tegra: Define Tegra210 DMIC sync clocks clk: tegra: Add CEC clock clk: tegra: Fix type for m field clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation clk: tegra: Don't warn for PLL defaults unnecessarily ... |
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Michael Turquette
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5579836026 |
General rockchip clock changes for 4.12. Contains some new clock-ids
as well as fixups of the clock-ids on rk3368 timers, which were unused and completely wrong (more and differently named timers). Also there is one new clock on rk3328 using the muxgrf type, a fix for pll enablement which should wait for the pll to lock before continuing, some more critical clocks and the rename of the rk1108 to rv1108, as the soc seems to have been using a preliminary name before its actual release. The plan is to have the driver changes (pinctrl, clk) go through the respective maintainer trees and once everything landed in mainline do the rename of the devicetree files. With the dts-include change in the clock rename, we also keep everything compiling and thus bisectability. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljY7X0QHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgRKaCACXoa3hjtS3CSqyJZQyMPPQ0Oda7bblrubR CE4GmuoZTnX/mUENFEmY7R+k0Np7b6ijPgdiFNpeZo0bpXAdi6bNjerG/QdRPV/P yP9usSk/8Tx/kY7vnSNTve5QiIJDUoWKGY8fn7ped+GmM7Qeb3/QbWR4N/fL4vVD nSZnKDO7yGMxLqWL0/QzZyiLzXl1ViEkPWFTedMf3cm0A48p8M/K5jinfMvl9I+o 6e2TIsc2zn6vRKuoGhjqcaRxhtRRV9c2O8wVAcA6BLo/kk3pA9ZTU3QJPsqEcN6A BTbANYfXiQF6i+Xp1YJHcE2lNQ/sWZOTQtLqY9SL5WzMETMTETT5 =In5R -----END PGP SIGNATURE----- Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: General rockchip clock changes for 4.12. Contains some new clock-ids as well as fixups of the clock-ids on rk3368 timers, which were unused and completely wrong (more and differently named timers). Also there is one new clock on rk3328 using the muxgrf type, a fix for pll enablement which should wait for the pll to lock before continuing, some more critical clocks and the rename of the rk1108 to rv1108, as the soc seems to have been using a preliminary name before its actual release. The plan is to have the driver changes (pinctrl, clk) go through the respective maintainer trees and once everything landed in mainline do the rename of the devicetree files. With the dts-include change in the clock rename, we also keep everything compiling and thus bisectability. * tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: add pll_wait_lock for pll_enable clk: rockchip: rename RK1108 to RV1108 dt-bindings: rk1108-cru: rename RK1108 to RV1108 clk: rockchip: mark some rk3368 core-clks as critical clk: rockchip: export SCLK_TIMERXX id for timers on rk3368 clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328 clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs clk: rockchip: fix up rk3368 timer-ids clk: rockchip: add rk3328 clk_mac2io_ext ID clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399 |
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Michael Turquette
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0d4ae36062 |
clk: renesas: Updates for v4.12 (take two)
- Add support for the Clock Pulse Generator / Module Standby and
Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
differs from ES1.x in some areas.
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Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the Clock Pulse Generator / Module Standby and
Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
differs from ES1.x in some areas.
- Add IMR clocks for R-Car H3 and M3-W,
- Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0,
- Small fixes and cleanups.
* tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Add support for fixing up clock tables
clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
clk: renesas: r8a7796: Reformat core clock table
clk: renesas: r8a7795: Reformat core clock table
clk: renesas: r8a7796: Correct name of watchdog clock
clk: renesas: r8a7795: Correct name of watchdog clock
clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
clk: renesas: r8a7796: Add IMR clocks
clk: renesas: r8a7795: Add IMR clocks
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Leo Yan
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b0459491ca |
clk: hi6220: add debug APB clock
The debug APB clock is absent in hi6220 driver, so this patch is to add support for it. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> |
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Wang Xiaoyin
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5a7e4774fd |
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
Extend drive strength levels of the pins for Hi3660 Soc. Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> |
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Geert Uytterhoeven
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fcb8708726 |
soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
Power area A2VC0 was removed in revision ES2.0, cfr. R-Car Gen3 Hardware
User's Manual rev. 0.53E.
Hence remove it from the power area table when not running on ES1.x.
This is in line with the goal to:
1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
for now,
2. Make it clear which code supports ES1.x, so it can easily be
identified and removed later, when production SoCs are deemed
ubiquitous.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Andrey Smirnov
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2d9eb1dd58 |
dt-bindings: Add GPCv2 power gating driver
Add DT bindings for power domain driver for GPCv2 IP block found in i.MX7 SoCs. Cc: yurovsky@gmail.com Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Dong Aisheng <dongas86@gmail.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> |
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Laxman Dewangan
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4c0facddb7 |
gpio: core: Decouple open drain/source flag with active low/high
Currently, the GPIO interface is said to Open Drain if it is Single Ended and active LOW. Similarly, it is said as Open Source if it is Single Ended and active HIGH. The active HIGH/LOW is used in the interface for setting the pin state to HIGH or LOW when enabling/disabling the interface. In Open Drain interface, pin is set to HIGH by putting pin in high impedance and LOW by driving to the LOW. In Open Source interface, pin is set to HIGH by driving pin to HIGH and set to LOW by putting pin in high impedance. With above, the Open Drain/Source is unrelated to the active LOW/HIGH in interface. There is interface where the enable/disable of interface is ether active LOW or HIGH but it is Open Drain type. Hence decouple the Open Drain with Single Ended + Active LOW and Open Source with Single Ended + Active HIGH. Adding different flag for the Open Drain/Open Source which is valid only when Single ended flag is enabled. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
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Neil Armstrong
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7d33d60b0c |
clk: meson-gxbb: Expose GP0 dt-bindings clock id
This patch exposes the GP0 PLL clock id in the dt bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-5-git-send-email-narmstrong@baylibre.com |
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Neil Armstrong
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5c65eec3d9 |
clk: meson-gxbb: Add MALI clock IDS
Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490177935-9646-2-git-send-email-narmstrong@baylibre.com |
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Jerome Brunet
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28f6c58367 |
dt-bindings: clk: gxbb: expose i2s output clock gates
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com |
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Chris Brandt
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929ded3dd7 |
ARM: dts: r7s72100: add rtc clock to device tree
Add the realtime clock functional clock source. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
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Dave Gerlach
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7cc119f29b |
dt-bindings: Add TI SCI PM Domains
Add a generic power domain implementation, TI SCI PM Domains, that will hook into the genpd framework and allow the TI SCI protocol to control device power states. Also, provide macros representing each device index as understood by TI SCI to be used in the device node power-domain references. These are identifiers for the K2G devices managed by the PMMC. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org> |
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Icenowy Zheng
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cdb8b80b60 |
clk: sunxi-ng: add support for PRCM CCUs
SoCs after A31 has a clock controller module in the PRCM part. Support the clock controller module on H3/5 and A64 now. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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Peter De Schrijver
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88da44c5ed |
clk: tegra: Add missing Tegra210 clocks
iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp and adsp neon were not modelled. dp2 wasn't modelled for Tegra210. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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Geert Uytterhoeven
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7b39e985cf |
ARM: dts: r8a7792: Correct Z clock
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
fixed divider.
This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.
Hence:
- Remove the Z clock output from the cpg_clocks node, as this implied
a programmable clock,
- Add the Z clock as a fixed factor clock,
- Let the first CPU node point to the new Z clock,
- Remove the Z clock index from the bindings (this definition was used
by r8a7792.dtsi only, and was not a contract between DT and driver).
Fixes:
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Geert Uytterhoeven
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89f1b1c614 |
clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as
listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3
Hardware User's Manual rev. 0.53E.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Geert Uytterhoeven
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1764f8081f |
ARM: dts: r8a7794: Add DU1 clock to device tree
Add the missing module clock for the second channel of the display unit. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
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Herbert Xu
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2e6d603e51 |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux
Merging 4.11-rc3 to pick up md5 removal from /dev/random. |
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Gabriel Fernandez
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156fdf11ae |
dt-bindings: mfd: Add STM32F7 RCC numeric constants into DT include file
This patch lists STM32F7's RCC numeric constants. It will be used by clock and reset drivers, and DT bindings. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> |
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Andy Yan
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7e2a9035c1 |
clk: rockchip: rename RK1108 to RV1108
Rockchip finally named the SOC as RV1108, so change it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> [include rename in rk1108.dtsi to prevent compile errors] Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
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Olof Johansson
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8855e14d61 |
Renesas ARM Based SoC DT Updates for v4.12
Cleanup: * Drop superfluous status update for frequency override on various boards * Always use status "okay" to enable devices on porger board * Add INTC-SYS clock to device tree of various SoCs * Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs * Remove unit-address and reg from integrated cache on various SoCs * Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS * Fix SCIFB0 dmas indentation on r8a774[35] SoCs Enhancements: * Add watchdog timer to r7s72100 SoC * Update sdhi clock bindings on r7s72100 SoC -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYz5TPAAoJENfPZGlqN0++JQYQAJ9qo4FOHP2XNttgK6b1jSg4 zSsjRats9bHX6Rs1dhT5KP7BatpH8kgLoJEqQThXWEq3qDNvDrWMd99yoOF8q1A5 tnpcFpzFZDf58J1PR0bPyWSZC6prLyV63Zinx6ZyTVDGm83gXk7TjfPRk7MqkPbr DP0spMO/5UXKPD6gE9hShz2WWCh6ZWvj6yUg+7ddjIYYYJwg+3MnNL+IE2H5BBaD VLlrxW5VrFdN1oxL+SpkB8DfcgTawJSTMw2pHzSqLT88s9ADAwW3IZeklpySztuk CEuxpi+0AouXzMfL4kJB4HTCXxOTGSpQVYEzUEWCID92eXyoBj08qghU21WKk87p 9OJZRd3xeZczN3ssfSVTLUp0rUrnS2Zyc3QOFRrA7gNLiykmNgurWrXT8e3yE9wa Z0Htb7WhUBlq77TTjDb46FMKCSdVcb2CbK2qtbyqdtRmsDB0+51DKG3bOsWTMWJW EMgWj4PsYcjBr+27q/8DbQXigX4c6jb3p/s6ouelEiN5ov78pwiNtBMBjiMxo1GI Pb4aWlKBDOxx4/JeBIn3pWKozbFIajPK6RYlHzd0g3SKFvjcEPlzqslsJTlye5ay CKHantmnzlIf+iJSdkthtD9ETIWhp0BvgmJ+BgwuffRpeaGjsXggkQjxGQBgRY3/ s7OWxr+5HMd+1Egj3Tg7 =2cA1 -----END PGP SIGNATURE----- Merge tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Renesas ARM Based SoC DT Updates for v4.12 Cleanup: * Drop superfluous status update for frequency override on various boards * Always use status "okay" to enable devices on porger board * Add INTC-SYS clock to device tree of various SoCs * Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs * Remove unit-address and reg from integrated cache on various SoCs * Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS * Fix SCIFB0 dmas indentation on r8a774[35] SoCs Enhancements: * Add watchdog timer to r7s72100 SoC * Update sdhi clock bindings on r7s72100 SoC * tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits) ARM: dts: silk: Drop superfluous status update for frequency override ARM: dts: alt: Drop superfluous status update for frequency override ARM: dts: gose: Drop superfluous status update for frequency override ARM: dts: porter: Drop superfluous status update for frequency override ARM: dts: koelsch: Drop superfluous status updates for frequency overrides ARM: dts: lager: Drop superfluous status update for frequency override ARM: dts: marzen: Drop superfluous status update for frequency override ARM: dts: bockw: Drop superfluous status update for frequency override ARM: dts: porter: Always use status "okay" to enable devices ARM: dts: r8a7793: Add INTC-SYS clock to device tree ARM: dts: r8a7793: Tidyup Audio-DMAC channel for DVC ARM: dts: r8a7791: Tidyup Audio-DMAC channel for DVC ARM: dts: r8a7794: Add INTC-SYS clock to device tree ARM: dts: r8a7792: Add INTC-SYS clock to device tree ARM: dts: r8a7791: Add INTC-SYS clock to device tree ARM: dts: r8a7790: Add INTC-SYS clock to device tree ARM: dts: r8a73a4: Add INTC-SYS clock to device tree ARM: dts: r7s72100: Add watchdog timer ARM: dts: r8a7790: Tidyup Audio-DMAC channel for DVC ARM: dts: r8a7794: Remove unit-address and reg from integrated cache ... Signed-off-by: Olof Johansson <olof@lixom.net> |
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Olof Johansson
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a618a7349f |
Reset controller changes for v4.12
- make reset drivers with bool Kconfig options explicitly non-modular - fix uniphier non-static symbol warnings - fix socfpga nr_resets property - new drivers for the Arria10 and i.MX7 system reset controllers - fix sunxi 64-bit compilation -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEBsBxhV1FaKwXuCOBUMKIHHCeYOsFAljJUToXHHAuemFiZWxA cGVuZ3V0cm9uaXguZGUACgkQUMKIHHCeYOvFnxAA8ImyPCzDDMtgGo9zMRId4ICH /YbbYrc5Gp3vDJJnJYVD0KCOT4174yinvHxrxpmjiftcZWcQRNH881uFJpgmXUjW zT7SapC0REWMx/DQzcR/Gh0smiehU1hVi+PSosNNqwbpZZrlxOAgGSoFYw87pBtJ gSOwTfUWlSEVMBtsQpTeO7cUzc5HvxuIvu/SMORi3xP1nukv8WIDuSGGFAWv235D OQOe101hQBO64yyW1J2X6+UMH+fHgmVT9qhqT6uJgYfR57pO17vX1aF/GEP9GV9R /vja0Y8hMNyvbc9CcJJQjR6BfXIOjrCYdDs+9nV4znYAcQpLJN5wfB6kDzogpH4S 3vgIsqT0OHYCdcXahuPuzDtE9zJ3oktyZT3MPyOsIkCwxGt5IJKRF9XGEGF3E/Sl 0yRpC45riac+8vuNJHnOe2qjRmx+zkAioyTPmYwPihwb1rLTYUtnqjat3egG1z0q UZvCpOcuQ9X/cAo+IIZW6IhDf6cqWEPks3pGinJ5XZ66qoeW5UMJz8v+i7c2F0oK LFLedERgaergvpAShiSeZTlXFkWQAJvGzDoCbpYTeQHELPV/ZJn88rJGP2DJ4/l1 7Sy5lyjFWtZqvfsBnoMniYc1XG2v5kztzAp9pZFEzBMHEVgCyJla5PxF7rDb+U/k tzeSfwd3DUkT8qtB1K4= =5xmN -----END PGP SIGNATURE----- Merge tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux into next/drivers Reset controller changes for v4.12 - make reset drivers with bool Kconfig options explicitly non-modular - fix uniphier non-static symbol warnings - fix socfpga nr_resets property - new drivers for the Arria10 and i.MX7 system reset controllers - fix sunxi 64-bit compilation * tag 'reset-for-4.12-1' of git://git.pengutronix.de/git/pza/linux: reset: sunxi: fix for 64-bit compilation reset: Add Altera Arria10 SR Reset Controller dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets reset: Add i.MX7 SRC reset driver reset-socfpga: Fix nr_resets property reset: uniphier: fix non static symbol warnings reset: pistachio: make it explicitly non-modular reset: ath79: make it explicitly non-modular reset: oxnas: make it explicitly non-modular reset: meson: make it explicitly non-modular Signed-off-by: Olof Johansson <olof@lixom.net> |
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Peter De Schrijver
|
68d724cedc |
clk: tegra: Add Tegra210 special resets
Tegra210 has 2 special resets which don't follow the normal pattern: DVCO and ADSP. Add them in this patch. Changelog: v2: add DT bindings file Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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Peter De Schrijver
|
24c3ebef1a |
clk: tegra: Add aclk
This clock clocks the ADSP Cortex-A9. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |