This is a preparing step for adding serial flash support.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
We can not assume parallel flash is always present, there are boards
with *serial* flash and probably some without flash at all.
Define some bits by the way.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Reviewed-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This patch adds support the the BCM5354 SoC.
It has a PMU and a constant not configurable clock.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Explicitely enable shared interrupt 2 for any core that didn't get a dedicated IRQ
anymore (fallthrough case) and for EXTIF cores to make gpio interrupts work.
Also remove a bogus comment.
Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
The current ssb irq setup in ssb_mipscore_init has the problem that it
configures some device on some irq without checking that the irq is not
taken by an other device.
For example in my case PCI host is on irq 0 and IPSEC on irq 3.
The current code:
- store in dev->irq that IPSEC irq is 3 + 2
- do a set_irq 0->3 on PCI host
But now IPSEC irq is not routed anymore to the mips code and dev->irq is
wrong. This causes a problem described in [1].
This patch tries to solve the problem by making set_irq configure the
device we want to take the irq on the shared irq0. The previous example
becomes:
- store in dev->irq that IPSEC irq is 3 + 2
- do a set_irq 0->3 on PCI host:
- irq 3 is already taken by IPSEC. do a set_irq 3->0 on IPSEC
I also added some code to print the irq configuration after irq setup to
allow easier debugging. And I add extra checking in ssb_mips_irq to report
device without irq or device with not routed irq.
[1] http://www.danm.de/files/src/bcm5365p/REPORTED_DEVICES
Signed-off-by: Matthieu CASTET <castet.matthieu@free.fr>
Acked-by : Michael Buesch <mb@bu3sch.de>
Tested-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This fixes assignment of the interrupt vectors on the SSB MIPS core.
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This adds the Gigabit Ethernet driver for the SSB
Gigabit Ethernet core. This driver actually is a frontend to
the Tigon3 driver. So the real work is done by tg3.
This device is used in the Linksys WRT350N.
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Fix a null pointer check in ssb mipscore init
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Acked-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
SSB is an SoC bus used in a number of embedded devices. The most
well-known of these devices is probably the Linksys WRT54G, but there
are others as well. The bus is also used internally on the BCM43xx
and BCM44xx devices from Broadcom.
This patch also includes support for SSB ID tables in modules, so
that SSB drivers can be loaded automatically.
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Hauke Mehrtens