Commit Graph

3 Commits

Author SHA1 Message Date
Jyri Sarha bcc5a6f5fc drm/tilcdc: Add blue-and-red-crossed devicetree property
Add "blue-and-red-wiring"-device tree property and update devicetree
binding document.

The red and blue components are reversed between 24 and 16 bit modes
on am335x LCDC output pins. To get 24 RGB format the red and blue
wires has to be crossed and this in turn causes 16 colors output to be
in BGR format. With straight wiring the 16 color is RGB and 24 bit is
BGR.

The new property describes whether the red and blue wires are crossed
or not. If the property is not present or its value is not recognized
the legacy mode is assumed. The legacy configuration supports RGB565,
RGB888 and XRGB8888 formats. However, depending on wiring, the red and
blue colors are swapped in either 16 or 24-bit color modes.

For more details see section 3.1.1 in AM335x Silicon Errata:
http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2016-09-01 22:32:11 +03:00
Jyri Sarha e0e344e620 drm/tilcdc: Change tilcdc_crtc_page_flip() to tilcdc_crtc_update_fb()
Change tilcdc_crtc_page_flip() to tilcdc_crtc_update_fb(). The
function is not used as a page_flip() callback anymore so it is only
confusing to call it that. The function should only be used by dummy
primary plane commit() callback.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-08-08 23:05:19 +03:00
Jyri Sarha b961c48b05 drm/tilcdc: Add dummy primary plane implementation
Add dummy primary plane implementation. LCDC does not really have
planes, only simple framebuffer that is mandatory. This primary plane
implementation has the necessary checks for implementing simple
framebuffer trough DRM plane abstraction. For setting the actual
framebuffer the implementation relies on a CRTC side function.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
2016-08-08 23:05:00 +03:00