3 Commits

Author	SHA1	Message	Date
Palmer Dabbelt	8286d51a6c	RISC-V: Comment on why {,cmp}xchg is ordered how it is ... This is another memory model FIXME. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>	2017-11-28 14:03:29 -08:00
Palmer Dabbelt	4650d02ad2	RISC-V: Remove unused arguments from ATOMIC_OP ... Our atomics are generated from a complicated series of preprocessor macros, each of which is slightly different from the last. When writing the macros I'd accidentally left some unused arguments floating around. This patch removes the unused macro arguments. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>	2017-11-28 13:53:24 -08:00
Palmer Dabbelt	fab957c11e	RISC-V: Atomic and Locking Code ... This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>	2017-09-26 15:26:45 -07:00