Commit Graph

9 Commits

Author SHA1 Message Date
Linus Torvalds 9b6d351a75 ARM: SoC DT updates for 3.14
DT and DT-conversion-related changes for various ARM platforms. Most
 of these are to enable various devices on various boards, etc, and not
 necessarily worth enumerating.
 
 New boards and systems continue to come in as new devicetree files that
 don't require corresponding C changes any more, which is indicating that
 the system is starting to work fairly well.
 
 A few things worth pointing out:
 
 * ST Ericsson ux500 platforms have made the major push to move over to fully
   support the platform with DT.
 * Renesas platforms continue their conversion over from legacy platform devices
   to DT-based for hardware description.
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC DT updates from Olof Johansson:
 "DT and DT-conversion-related changes for various ARM platforms.  Most
  of these are to enable various devices on various boards, etc, and not
  necessarily worth enumerating.

  New boards and systems continue to come in as new devicetree files
  that don't require corresponding C changes any more, which is
  indicating that the system is starting to work fairly well.

  A few things worth pointing out:

   * ST Ericsson ux500 platforms have made the major push to move over
     to fully support the platform with DT
   * Renesas platforms continue their conversion over from legacy
     platform devices to DT-based for hardware description"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (327 commits)
  ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync
  ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6
  ARM: dts: sirf: add lost minigpsrtc device node
  ARM: dts: sirf: add clock, frequence-voltage table for CPU0
  ARM: dts: sirf: add lost bus_width, clock and status for sdhci
  ARM: dts: sirf: add lost clocks for cphifbg
  ARM: dts: socfpga: add pl330 clock
  ARM: dts: socfpga: update L2 tag and data latency
  arm: sun7i: cubietruck: Enable the i2c controllers
  ARM: dts: add support for EXYNOS4412 based TINY4412 board
  ARM: dts: Add initial support for Arndale Octa board
  ARM: bcm2835: add USB controller to device tree
  ARM: dts: MSM8974: Add MMIO architected timer node
  ARM: dts: MSM8974: Add restart node
  ARM: dts: sun7i: external clock outputs
  ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style
  ARM: dts: sun7i: Add pin muxing options for clock outputs
  ARM: dts: sun7i: Add rtp controller node
  ARM: dts: sun5i: Add rtp controller node
  ARM: dts: sun4i: Add rtp controller node
  ...
2014-01-23 18:45:38 -08:00
Maxime Ripard 81ee429ffd ARM: sun6i: dt: Add IP needed to bring up the additional cores
Add the PRCM and CPU configuration units needed for SMP in the A31 DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-12-16 21:15:12 +01:00
Maxime Ripard 6f97dc8d46 ARM: sun6i: dt: Fix interrupt trigger types
The Allwinner A31 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A31 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Cc: stable@vger.kernel.org # 3.12+
Signed-off-by: Olof Johansson <olof@lixom.net>
2013-12-11 17:15:24 -08:00
Maxime Ripard 24a661e994 ARM: sun6i: Add the reset controller to the DTSI
The A31 has a reset controller IP that maintains a few other IPs in
reset, among which we can find the UARTs, high speed timers or the I2C.
Now that we have support for them, add the reset controllers to the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
2013-11-22 21:36:56 +01:00
Maxime Ripard 439d9f5801 ARM: sun6i: Fix the APB2 clock gates register size
The APB2 clocks gates are only a 32 bits register wide, and not 2 as set
currently in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-10-05 15:36:10 +02:00
Maxime Ripard 98096560eb ARM: sun6i: Enable clock support in the DTSI
Now that the clock driver has support for the A31 clocks, we can add
them to the DTSI and start using them in the relevant hardware blocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-26 10:51:18 +02:00
Maxime Ripard ab4238cd05 ARM: sun6i: Add UART0 muxing options
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-22 00:19:16 +02:00
Maxime Ripard 140e1721d1 ARM: sunxi: dt: Add PIO controller to A31 DTSI
The A31 has a different set of pins than the one found on the A10 and
A13. Now that we have support for the A31 pin set in the pinctrl driver,
we can enable it in the DTSI with its own compatible.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-22 00:19:16 +02:00
Maxime Ripard 8aed3b3158 ARM: sunxi: Add Allwinner A31 DTSI
The Allwinner A31 SoC is a multimedia SoC powered by 4 Cortex-A7 and a
PowerVR GPU.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-08-16 23:18:22 +02:00