Commit Graph

5 Commits

Author SHA1 Message Date
Arnd Bergmann 013e2b722a drm/tegra: Mark Tegra186 display hub PM functions __maybe_unused
The newly introduced driver has optional suspend/resume functions,
causing a warning when CONFIG_PM is disabled:

drivers/gpu/drm/tegra/hub.c:749:12: error: 'tegra_display_hub_resume' defined but not used [-Werror=unused-function]
drivers/gpu/drm/tegra/hub.c:733:12: error: 'tegra_display_hub_suspend' defined but not used [-Werror=unused-function]

This marks them __maybe_unused to shut up the warnings.

Fixes: c4755fb906 ("drm/tegra: Add Tegra186 display hub support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21 14:52:37 +01:00
Thierry Reding ab7d3f5826 drm/tegra: Implement zpos property
Implement the standard zpos property for planes on Tegra124 and later.
Earlier generations have a different blending unit that needs different
programming.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21 14:52:35 +01:00
Thierry Reding 1087fac18b drm/tegra: dc: Use direct offset to plane registers
Traditionally, windows were accessed indirectly, through a register
selection window that required a global register to be programmed with
the index of the window to access. Since the global register could be
written from modesetting functions as well as the interrupt handler
concurrently, accesses had to be serialized using a lock. Using direct
accesses to the window registers the lock can be avoided.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21 14:52:34 +01:00
Thierry Reding 511c7023cf drm/tegra: dc: Support more formats
Also, split up formats into per-SoC lists because not all generations
support all of them. Note that the list is now exhaustive for all RGB
formats, but not for YUV and indexed formats.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21 14:52:29 +01:00
Thierry Reding c4755fb906 drm/tegra: Add Tegra186 display hub support
The display architecture has changed in several significant ways with
the new Tegra186 SoC. Shared between all display controllers is a set
of common resources referred to as the display hub. The hub generates
accesses to memory and feeds them into various composition pipelines,
each of which being a window that can be assigned to arbitrary heads.

Atomic state is subclassed in order to track the global bandwidth
requirements and select and adjust the hub clocks appropriately. The
plane code is shared to a large degree with earlier SoC generations,
except where the programming differs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 14:16:37 +01:00