Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and
sleep states and enable them in board evm dts file.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As usual, this is the largest branch, though this time a little under
half of the total changes with 307 individual non-merge changesets.
The largest changes are the addition of new machines, in particular
the Tegra based Chromebook, the Renesas r8a7794 SoC, and DT support
for the old i.MX1 platform.
Other changes include
- at91: various sam9 and sama5 updates
- exynos: much extended Peach Pi/Pit (Chromebook 2) support
- keystone: new peripherals
- meson: added DT for meson6 SoC
- mvebu: new device support for Armada 370/375
- qcom: improved support for IPQ8064 and MSM8x60
- rockchip: much improved support for rk3288
- shmobile: lots of updates all over the place
- sunxi: dts license change
- sunxi: more a23 device support
- vexpress: CLCD DT description
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAVDWVG2CrR//JCVInAQJmARAAnU2I4VpJHlBeHC4CYr/GdRq0NqiFvQ38
7N/zevUI4l150DtejltbOX71JGM9vD3hq8VXZYBCEpTbG4el9PzAq28Fomtt4tmC
PGbczQY8ZMvY1/MOT3XLZAd3TSUL0TZRt97t9bdLif6QyPafel5o2pd8D2OG7h+L
Awtyk9LobT9jU3muFX3ZUfB3Gg2sNKphZjox9Le3gVjGd6g5teEqqMAehK2Y7ArJ
kixrKck4vgduDdZe59o2yApAUsfIQv/joqu68jv3MUQrKmk4s543+rIdGDuLF5bz
mEo7qtMXujoNaF3CyLYNEF2ZExIOJDdtmrwjHY8oKIFtIeI/faIJmeSChwa6794t
Njj5bbnL0Pt61l4gUSFk2hUFo28gpiEB+Mm0R4E1hdoG15Iv6E+lpy44EmEmfz1c
9h0sATNGUrz18IrUk7jI1WwIaEJUwkbZ+8wKuWtvH+Z+mFA4ZlDykVcnVuELixpb
vKmI3kcmEw2RsJjkYq3LcgXXQevE4mHRR1ow59yXTY6OR1LmVb7odKUwbrweofQO
eytVb1deMeYXrBXT5/j6WmrlyDbYcuGsjO4WidT+zwYUiAMCE6bTpNwUWqumVEUv
LjCBaN6BRIb89EBwt4xIvIu7ir9hNNRZnD8aa4afSzIYxknzZy73pjjT2+wu7jbU
m15TwYyQG4E=
=2Sq1
-----END PGP SIGNATURE-----
Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Arnd Bergmann:
"As usual, this is the largest branch, though this time a little under
half of the total changes with 307 individual non-merge changesets.
The largest changes are the addition of new machines, in particular
the Tegra based Chromebook, the Renesas r8a7794 SoC, and DT support
for the old i.MX1 platform.
Other changes include
- at91: various sam9 and sama5 updates
- exynos: much extended Peach Pi/Pit (Chromebook 2) support
- keystone: new peripherals
- meson: added DT for meson6 SoC
- mvebu: new device support for Armada 370/375
- qcom: improved support for IPQ8064 and MSM8x60
- rockchip: much improved support for rk3288
- shmobile: lots of updates all over the place
- sunxi: dts license change
- sunxi: more a23 device support
- vexpress: CLCD DT description"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (308 commits)
ARM: DTS: meson: update DTSI to add watchdog node
ARM: dts: keystone-k2l: fix mdio io start address
ARM: dts: keystone-k2e: fix mdio io start address
ARM: dts: keystone-k2e: update usb1 node for dma properties
ARM: dts: keystone: fix io range for usb_phy0
Revert "Merge tag 'hix5hd2-dt-for-3.18' of git://github.com/hisilicon/linux-hisi into next/dt"
Revert "ARM: dts: hix5hd2: add wdg node"
ARM: dts: add rk3288 i2s controller
ARM: vexpress: Add CLCD Device Tree properties
ARM: bcm2835: add I2S pinctrl to device tree
ARM: meson: documentation: add bindings documentation
ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS
ARM: dts: mt6589: Change compatible string for GIC
ARM: dts: mediatek: Add compatible property for aquaris5
ARM: dts: mt6589-aquaris5: Add boot argument earlyprintk
ARM: dts: mt6589: Fix typo in GIC unit address
ARM: dts: Build dtb for Mediatek board
ARM: dts: keystone: fix bindings for pcie and usb clock nodes
ARM: dts: keystone: k2l: Fix chip selects for SPI devices
ARM: dts: keystone: add dsp gpio controllers nodes
...
The nand timings were scaled down by 2 to account for
the 2x rate returned by clk_get_rate(gpmc_fclk).
As the clock data got fixed by [1], revert back to actual
timings (i.e. scale them up by 2).
Without this NAND doesn't work on dra7-evm.
[1] - commit dd94324b98
ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates
Fixes: ff66a3c86e ("ARM: dts: dra7: add support for parallel NAND flash")
Cc: <stable@vger.kernel.org> [3.16]
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Mark rxd as wakeupcapable for 115200n8 no hardware-flow control
configuration. If h/w flow control is being used, then rts/cts
appropriately should be used.
Signed-off-by: Nishanth Menon <nm@ti.com>
DRA7 evm REV G and later boards uses a vtt regulator for DDR3
termination and this is controlled by gpio7_11. This gpio is
configured in boot loader. gpio7_11, which is only available only on
Pad A22, in previous boards, is connected only to an unused pad on
expansion connector EXP_P3 and is safe to be muxed as GPIO on all
DRA7-evm versions (without a need to spin off another dts file).
Since gpio7_11 is used to control VTT and should not be reset or kept
in idle state during boot up else VTT will be disconnected and DDR
gets corrupted. So, as part of this change, mark gpio7 as no-reset and
no-idle on init.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
While auditing the various pin ctrl configurations using the following
command:
grep PIN_ arch/arm/boot/dts/dra7-evm.dts|(while read line;
do
v=`echo "$line" | sed -e "s/\s\s*/|/g" | cut -d '|' -f1 |
cut -d 'x' -f2|tr [a-z] [A-Z]`;
HEX=`echo "obase=16;ibase=16;4A003400+$v"| bc`;
echo "$HEX ===> $line";
done)
against DRA75x/74x NDA TRM revision S(SPRUHI2S August 2014),
documentation errors were found for spi1 pinctrl. Fix the same.
Fixes: 6e58b8f1da ("ARM: dts: DRA7: Add the dts files for dra7 SoC and dra7-evm board")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The 8th NAND partition should be named "NAND.u-boot-env.backup1"
instead of "NAND.u-boot-env". This is to be consistent with other
TI boards as well as u-boot.
CC: Pekon Gupta <pekon@pek-sem.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The I2C3 pins are taken from pads E21 (GPIO6_14) and
F20 (GPIO6_15). Use the right pinmux register and mode.
Also set the I2C3 bus frequency to a safer 400KHz than
3.4Mhz.
CC: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- Document and use new cadence serial binding
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iEYEABECAAYFAlPI73sACgkQykllyylKDCGYzQCggc3g80f6R008+SNKlrN0Wuy+
b9kAnjqTO0Q0kDf4PlI/a5EVsfPmOzoS
=Bo6W
-----END PGP SIGNATURE-----
Merge tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx into next/dt
Merge "Xilinx Zynq changes for v3.17" from Michal Simek:
arm: Xilinx Zynq dt patches for v3.17
- Document and use new cadence serial binding
* tag 'zynq-dt-for-3.17' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: DT: Migrate UART to Cadence binding
tty: cadence: Document DT binding
+ Linux 3.16-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
The ldousb_reg regulator provides power to the USB1 and USB2
High Speed PHYs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
After clarification from the hardware team it was found that
this 1.8V PHY supply can't be switched OFF when SoC is Active.
Since the PHY IPs don't contain isolation logic built in the design to
allow the power rail to be switched off, there is a very high risk
of IP reliability and additional leakage paths which can result in
additional power consumption.
The only scenario where this rail can be switched off is part of Power on
reset sequencing, but it needs to be kept always-on during operation.
This patch is required for proper functionality of USB, SATA
and PCIe on DRA7-evm.
CC: Rajendra Nayak <rnayak@ti.com>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA7xx platform has in-build GPMC and ELM h/w engines which can be used
for accessing externel NAND flash device. This patch:
- adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines
- adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm
*Important*
On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch
So following board settings are required for NAND device detection:
SW5.9 (GPMC_WPN) = LOW
SW5.1 (NAND_BOOTn) = HIGH
Signed-off-by: Minal Shah <minalkshah@gmail.com>
Signed-off-by: Pekon Gupta <pekon@ti.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add USB pinmux information and USB modes
for the USB controllers.
CC: Benoît Cousson <bcousson@baylibre.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
These add device tree entry for qspi controller driver on dra7-evm.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA722 is part of DRA72x family which are single core cortex A15 devices
with most infrastructure IPs otherwise same as whats on the DRA74x family.
So move the cpu nodes into dra74x.dtsi and dra72x.dtsi respectively.
Also add a minimal dra72-evm dts file.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: linux-doc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Arnd Bergmann <arnd@arndb.de>
[tony@atomide.com: updated for Makefile sorting]
Signed-off-by: Tony Lindgren <tony@atomide.com>
"ti,dra752" is neither documented nor correct, since the device is actually a
dra742 device as rightly documented in dt bindings.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add mmc2 dt node to dra7-evm board
and model eMMC vcc as fixed regulator.
Signed-off-by: Balaji T K <balajitk@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add mmc1 dt node to dra7-evm board.
Input for ldo1 regulator is controlled by gpio 5 of pcf8575 chip (0x21)
on i2c1 bus. When dt support for gpio-pcf857x is available, input supply
will be modelled as cascaded regulator.
Signed-off-by: Balaji T K <balajitk@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add DT nodes for TPS659038 PMIC on DRA7 boards.
It is based on top of:
http://comments.gmane.org/gmane.linux.ports.arm.omap/102459.
Documentation:
- Documentation/devicetree/bindings/mfd/palmas.txt
- Documentation/devicetree/bindings/regulator/palmas-pmic.txt
Boot Tested on DRA7 d1 Board.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
[bcousson@baylibre.com: Fix indentation and changelog]
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add minimal device tree source needed for DRA7 based SoCs.
Also add a board dts file for the dra7-evm (based on dra752)
which contains 1.5G of memory with 1G interleaved and 512MB
non-interleaved. Also added in the board file are pin configuration
details for i2c, mcspi and uart devices on board.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Mugunthan V N