Commit Graph

13 Commits

Author SHA1 Message Date
Linus Walleij bc71c0961c ARM: ux500: core U9540 support
This adds support for the U9540 variant of the U8500 series. This
is an application processor without internal modem. This is the
most basic part with ASIC ID, CPU-related fixes, IRQ list, register
ranges, timer, UART, and L2 cache setup. This is based on a patch
by Michel Jaouen which was rewritten to fit with the latest 3.3
kernel.

ChangeLog v1->v2: deleted the irqs-db9540.h file since we expect to
  migrate to using Device Tree for getting the IRQs to devices.
ChangeLog v2->v3: introduced a fixed virtual offset for the ROM
  as suggested by Arnd Bergmann.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sebastien Pasdeloup <sebastien.pasdeloup-nonst@stericsson.com>
Signed-off-by: Michel Jaouen <michel.jaouen@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-02 00:25:13 +02:00
Lee Jones eda413c228 ARM: ux500: export System-on-Chip information ux500 via sysfs
Here we make use of the new System-On-Chip bus driver to export
vital SoC information out to userspace via sysfs. This patch
provides a data structure of strings to populate the base
nodes found in:

/sys/devices/soc[0|1|2|...]/[family|machine|revision|soc_id].

It also adds one more node as requested by ST-Ericsson.
'process' depicts the way in which the silicon was manufactured.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2012-02-13 06:31:38 +00:00
Linus Walleij c15def1cc3 ARM: ux500: remove support for early silicon revisions
The DB8500 ED (Early Drop) and V1 are only available inside of
ST-Ericsson or partners, we have actively replaced and scrapped
these prototypes. All Nova products on the open market (such as
the Snowball board) are based on V2 and later ASIC variants.
So let us focus on supporting the silicon that will be used and
delete this to get a clear overview.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-12-19 00:35:07 +01:00
Linus Walleij ca2ea4e8d4 ARM: ux500: update register files
A few new addresses for newly supported peripherals and SRAM base
offsets.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-12-19 00:35:07 +01:00
Mattias Wallin 7ed00af7a9 ARM: ux500: add support for clocksource DBX500 PRCMU
This patch adds support for the DBX500 PRCMU clocksource
to ux500 platforms.

Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.co>
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-22 15:43:20 +02:00
Linus Walleij 326474067f mach-ux500: update the DB8500 register file
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-05-24 22:11:43 +02:00
Lucas De Marchi 25985edced Fix common misspellings
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
2011-03-31 11:26:23 -03:00
Mattias Wallin fcbd458e95 ARM: ux500: prcmu db8500 v2 support
This patch adds support for db8500 chip version 2.
The TCDM memory address of the PRCMU is changed and
dynamic detection of that is added.

Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
2010-12-08 13:14:13 +01:00
Linus Walleij f946738ca8 ARM: 6331/1: ux500 cpu/SoC version macros v2
This patch adds support for checking if the digital baseband (DB)
System-on-Chip (aka "cpu) ASIC hardware version is 1.0, 1.1 or
2.0. We print the result in the bootlog, the functions are then
used for runtime decisions based on hardware version.

Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-09-02 15:46:19 +01:00
Linus Walleij f41855929c DMAENGINE: ste_dma40: support older silicon
This makes sure the DMA40 driver will also work on the oldest
silicon revisions that have the on-chip memory on another location
in the DB8500 and also requires explicit suspend before starting
or resuming a logical channel.

Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
[added parenthesis to the definition of U8500_DMA_LCPA_BASE_ED]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-06-22 18:06:42 -07:00
Jonas Aaberg 5aa12e8c9c DMAENGINE: ste_dma40: arch updates for LCLA and LCPA
This follows on the patch to allocate LCLA dynamically: the
on-chip memory is needed for other things so now that that
we're using it dynamically we can remove the LCLA resource
altogether and free up some ESRAM memory.

Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-06-22 18:01:55 -07:00
Linus Walleij 7b8ddb06e5 DMAENGINE: DMA40 U8500 platform configuration
This completes the DMA40 support with the platform-specific
configuration for U8500/DB8500.

Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Reviewed-by: Alessandro Rubini <rubini@unipv.it>
Cc: STEricsson_nomadik_linux@list.st.com
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
[fixed up dma40_{tx|rx}_map declaration/initialization]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2010-05-27 15:21:26 -07:00
Rabin Vincent c9c0957286 ARM: 6078/1: ux500: add per-SoC register definitions
Split up all the hardware register definitions previously found in
hardware.h into per-SoC files db8500-regs.h and db5500-regs.h.  Rename a
couple of macros to prepare for sharing code between the variants.

Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-05-04 17:50:01 +01:00