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Merge tag 's3c24xx-dma' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim, this branch adds device-tree support to the DMA controller
on the older Samsung SoCs. It also adds support for one of the missing SoCs
in the family (2410).
The driver has been Ack:ed by Vinod Koul, but is merged through here due
to dependencies with platform code.
* tag 's3c24xx-dma' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C24XX: add dma pdata for s3c2410, s3c2440 and s3c2442
dmaengine: s3c24xx-dma: add support for the s3c2410 type of controller
ARM: S3C24XX: Fix possible dma selection warning
ARM: SAMSUNG: set s3c24xx_dma_filter for s3c64xx-spi0 device
ARM: S3C24XX: add platform-devices for new dma driver for s3c2412 and s3c2443
dmaengine: add driver for Samsung s3c24xx SoCs
ARM: S3C24XX: number the dma clocks
+ Linux 3.12-rc3
Signed-off-by: Olof Johansson <olof@lixom.net>
- remove unnecessary config options and header inclusions
- use CONFIG_ARCH_S3C64XX instead of PLAT_S3C64XX
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Merge tag 'samsung-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
From Kukjin Kim:
Samsung Cleanup for v3.13
- remove unnecessary config options and header inclusions
- use CONFIG_ARCH_S3C64XX instead of PLAT_S3C64XX
* tag 'samsung-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: remove CONFIG_MACH_EXYNOS[4, 5]_DT config options
ARM: EXYNOS: remove unnecessary header inclusions from exynos4/5 dt machine file
ARM: S3C64XX: Kill CONFIG_PLAT_S3C64XX
ASoC: samsung: Use CONFIG_ARCH_S3C64XX to check for S3C64XX support
s3c-camif: Use CONFIG_ARCH_S3C64XX to check for S3C64XX support
gpio: samsung: Use CONFIG_ARCH_S3C64XX to check for S3C64XX support
ARM: S3C64XX: Move if ARCH_S3C64XX statement into mach-s3c64xx
Signed-off-by: Olof Johansson <olof@lixom.net>
and adding SSP/SPI devices to the device tree.
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Merge tag 'ux500-dt-for-v3.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
From Linus Walleij:
Five incremental device tree patches around the clock handling,
and adding SSP/SPI devices to the device tree.
* tag 'ux500-dt-for-v3.13-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: register all SSP and SPI blocks
ARM: ux500: fix I2C4 clock bit
ARM: ux500: fix clock for GPIO blocks 6 and 7
clk: ux500: fix erroneous bit assignment
ARM: ux500: fix clock for GPIO block 8
Signed-off-by: Olof Johansson <olof@lixom.net>
This DT series sees the introduction of the cubietruck DT, plus the addition of
the i2c controller for the A20 based boards, and of the Security ID found in
all the Allwinner SoCs but the A31.
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Merge tag 'sunxi-dt-for-3.13' of https://github.com/mripard/linux into next/dt
From Maxime Ripard:
Allwinner sunXi SoCs device tree changes for 3.13
This DT series sees the introduction of the cubietruck DT, plus the addition of
the i2c controller for the A20 based boards, and of the Security ID found in
all the Allwinner SoCs but the A31.
* tag 'sunxi-dt-for-3.13' of https://github.com/mripard/linux:
ARM: sunxi: dts: Add support for the cubieboard3, the CubieTruck
ARM: sun7i: olinuxino-micro: Enable the I2C controllers
ARM: sun7i: cubieboard2: Enable the I2C controllers
ARM: sun7i: Add the pin muxing options for the I2C controllers
ARM: sun7i: Enable the I2C controllers
ARM: sunxi: dt: Add sunxi-sid to dts for sun4i, sun5i and sun7i
Signed-off-by: Olof Johansson <olof@lixom.net>
* pm-cpufreq: (167 commits)
cpufreq: create per policy rwsem instead of per CPU cpu_policy_rwsem
intel_pstate: Add Baytrail support
intel_pstate: Refactor driver to support CPUs with different MSR layouts
cpufreq: Implement light weight ->target_index() routine
PM / OPP: rename header to linux/pm_opp.h
PM / OPP: rename data structures to dev_pm equivalents
PM / OPP: rename functions to dev_pm_opp*
cpufreq / governor: Remove fossil comment
cpufreq: exynos4210: Use the common clock framework to set APLL clock rate
cpufreq: exynos4x12: Use the common clock framework to set APLL clock rate
cpufreq: Detect spurious invocations of update_policy_cpu()
cpufreq: pmac64: enable cpufreq on iMac G5 (iSight) model
cpufreq: pmac64: provide cpufreq transition latency for older G5 models
cpufreq: pmac64: speed up frequency switch
cpufreq: highbank-cpufreq: Enable Midway/ECX-2000
exynos-cpufreq: fix false return check from "regulator_set_voltage"
speedstep-centrino: Remove unnecessary braces
acpi-cpufreq: Add comment under ACPI_ADR_SPACE_SYSTEM_IO case
cpufreq: arm-big-little: use clk_get instead of clk_get_sys
cpufreq: exynos: Show a list of available frequencies
...
Conflicts:
drivers/devfreq/exynos/exynos5_bus.c
* pm-cpuidle:
ARM: AT91: DT: pm: Select ram controller standby based on DT
ARM: AT91: pm: Factorize standby function
ARM: at91: cpuidle: Move driver to drivers/cpuidle
ARM: at91: cpuidle: Convert to platform driver
ARM: ux500: cpuidle: fix section mismatch
ARM: zynq: cpuidle: convert to platform driver
ARM: zynq: cpuidle: Remove useless compatibility string
drivers: cpuidle: rename ARM big.LITTLE driver config and makefile entries
ARM: EXYNOS: convert cpuidle driver to be a platform driver
intel_idle: mark some functions with __init tag
intel_idle: mark states tables with __initdata tag
intel_idle: shrink states tables
Currently, the prototype of cpufreq_drivers target routines is:
int target(struct cpufreq_policy *policy, unsigned int target_freq,
unsigned int relation);
And most of the drivers call cpufreq_frequency_table_target() to get a valid
index of their frequency table which is closest to the target_freq. And they
don't use target_freq and relation after that.
So, it makes sense to just do this work in cpufreq core before calling
cpufreq_frequency_table_target() and simply pass index instead. But this can be
done only with drivers which expose their frequency table with cpufreq core. For
others we need to stick with the old prototype of target() until those drivers
are converted to expose frequency tables.
This patch implements the new light weight prototype for target_index() routine.
It looks like this:
int target_index(struct cpufreq_policy *policy, unsigned int index);
CPUFreq core will call cpufreq_frequency_table_target() before calling this
routine and pass index to it. Because CPUFreq core now requires to call routines
present in freq_table.c CONFIG_CPU_FREQ_TABLE must be enabled all the time.
This also marks target() interface as deprecated. So, that new drivers avoid
using it. And Documentation is updated accordingly.
It also converts existing .target() to newly defined light weight
.target_index() routine for many driver.
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Russell King <linux@arm.linux.org.uk>
Acked-by: David S. Miller <davem@davemloft.net>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rjw@rjwysocki.net>
Since Operating Performance Points (OPP) functions are specific
to device specific power management, be specific and rename opp.h
to pm_opp.h
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Since Operating Performance Points (OPP) data structures are specific
to device specific power management, be specific and rename opp_* data
structures in OPP library with dev_pm_opp_* equivalent.
Affected structures are:
struct opp
enum opp_event
Minor checkpatch warning resulting of this change was fixed as well.
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Since Operating Performance Points (OPP) functions are specific to
device specific power management, be specific and rename opp_*
accessors in OPP library with dev_pm_opp_* equivalent.
Affected functions are:
opp_get_voltage
opp_get_freq
opp_get_opp_count
opp_find_freq_exact
opp_find_freq_floor
opp_find_freq_ceil
opp_add
opp_enable
opp_disable
opp_get_notifier
opp_init_cpufreq_table
opp_free_cpufreq_table
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This patch moves the handling of the chip's enable pin from the board
code into the driver. It also updates all board-code files using the
driver to incorporate this change.
This is needed for device tree support of the enable pin.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Bryan Wu <cooloney@gmail.com>
There's really only one bugfix in this branch, which is a fix for timers on
the integrator platform. Since Linus Walleij is resurrecting support for
the platform it seems valuable to get the fix into 3.12 even though the
regression has been around a while.
The rest are a handful of maintainers updates. If you prefer to hold those
until 3.13 then just merge the first patch on the branch which is the fix.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"There's really only one bugfix in this branch, which is a fix for
timers on the integrator platform. Since Linus Walleij is
resurrecting support for the platform it seems valuable to get the fix
into 3.12 even though the regression has been around a while.
The rest are a handful of maintainers updates. If you prefer to hold
those until 3.13 then just merge the first patch on the branch which
is the fix"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
MAINTAINERS: Add maintainers entry for Rockchip SoCs
MAINTAINERS: Tegra updates, and driver ownership
MAINTAINERS: ARM: mvebu: add Sebastian Hesselbarth
ARM: integrator: deactivate timer0 on the Integrator/CP
This branch includes:
* SoC fuse values are used as device randomness at boot.
* Initial support for the Tegra124 SoC is added. When coupled with an
appropriate clock driver, which should also be merged for 3.13, we are
able to boot to user-space using an initrd.
* The powergate code gains support for Tegra114.
This branch is based on previous pull request tegra-for-3.13-cleanup.
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Merge tag 'tegra-for-3.13-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: core SoC support changes for 3.13
This branch includes:
* SoC fuse values are used as device randomness at boot.
* Initial support for the Tegra124 SoC is added. When coupled with an
appropriate clock driver, which should also be merged for 3.13, we are
able to boot to user-space using an initrd.
* The powergate code gains support for Tegra114.
This branch is based on previous pull request tegra-for-3.13-cleanup.
* tag 'tegra-for-3.13-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: Add Tegra114 powergate support
ARM: tegra: Constify list of CPU domains
ARM: tegra: Remove duplicate powergate defines
ARM: tegra: add LP1 support code for Tegra124
ARM: tegra: re-calculate the LP1 data for Tegra30/114
ARM: tegra: enable CPU idle for Tegra124
ARM: tegra: make tegra_resume can work with current and later chips
ARM: tegra: CPU hotplug support for Tegra124
ARM: tegra: add PMC compatible value for Tegra124
ARM: tegra: add Tegra124 SoC support
ARM: tegra: add fuses as device randomness
ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order
ARM: tegra: make tegra_init_fuse() __init
ARM: tegra: remove much of iomap.h
ARM: tegra: move resume vector define to irammap.h
ARM: tegra: delete gpio-names.h
ARM: tegra: delete stale header content
ARM: tegra: remove common.c
ARM: tegra: split tegra_pmc_init() in two
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This is similar to what it is done on X86: biovecs are prevented from merging
otherwise every dma requests would be forced to bounce on the swiotlb buffer.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Changes in v7:
- remove the extra autotranslate check in biomerge.c.
Introduce xen_dma_map_page, xen_dma_unmap_page,
xen_dma_sync_single_for_cpu and xen_dma_sync_single_for_device.
They have empty implementations on x86 and ia64 but they call the
corresponding platform dma_ops function on arm and arm64.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Changes in v9:
- xen_dma_map_page return void, avoid page_to_phys.
Final conversions to configfs for mass storage, acm_ms, and
multi gadgets.
MUSB should now work out of the box on AM335x-based boards
(beagle bone white and black) with DMA thanks to Sebastian's
work.
We can now enable VERBOSE_DEBUG on builds of drivers/usb/gadget/
by selecting CONFIG_USB_GADGET_VERBOSE.
s3c-hsotg got quite a few non-critical fixes but also learned
a few new tricks (isochronous transfers, multi count support).
The Marvel USB3 Controller driver got a memory leak fix.
devm_usb_get_phy() learned not to return NULL, ever.
Other than these patches, we have the usual set of cleanups
ranging from removal of unnecessary *_set_drvdata() to using
SIMPLE_DEV_PM_OPS.
Signed-of-by: Felipe Balbi <balbi@ti.com>
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Merge tag 'usb-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
Felipe writes:
usb: patches for v3.13
Final conversions to configfs for mass storage, acm_ms, and
multi gadgets.
MUSB should now work out of the box on AM335x-based boards
(beagle bone white and black) with DMA thanks to Sebastian's
work.
We can now enable VERBOSE_DEBUG on builds of drivers/usb/gadget/
by selecting CONFIG_USB_GADGET_VERBOSE.
s3c-hsotg got quite a few non-critical fixes but also learned
a few new tricks (isochronous transfers, multi count support).
The Marvel USB3 Controller driver got a memory leak fix.
devm_usb_get_phy() learned not to return NULL, ever.
Other than these patches, we have the usual set of cleanups
ranging from removal of unnecessary *_set_drvdata() to using
SIMPLE_DEV_PM_OPS.
Signed-of-by: Felipe Balbi <balbi@ti.com>
dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables and list the dividers explicitly.
I believe the same issue is there for other dpll4_mx_ck clocks, but as
I'm not familiar with them, I didn't touch them.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Set CLK_SET_RATE_PARENT flag for dss1_alwon_fck_3430es2,
dss1_alwon_fck_3430es1 and dpll4_m4x2_ck so that the DSS's fclk can be
configured without the need to get the parent's parent of the fclk.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Set CLK_SET_RATE_PARENT flag for dss_dss_clk so that the DSS's fclk can
be configured without the need to get the parent of the fclk.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Several architectures open code effectively the same code block for
finding and mapping PCI irqs. This patch consolidates it down to a
single function.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Replace some instances of of_irq_map_one()/irq_create_of_mapping() and
of_irq_to_resource() by the simpler equivalent irq_of_parse_and_map().
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
[grant.likely: resolved conflicts with core code renames]
Signed-off-by: Grant Likely <grant.likely@linaro.org>
This patch extends the DT selftest code with some test cases for the
interrupt parsing functions.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
All the callers of irq_create_of_mapping() pass the contents of a struct
of_phandle_args structure to the function. Since all the callers already
have an of_phandle_args pointer, why not pass it directly to
irq_create_of_mapping()?
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
struct of_irq and struct of_phandle_args are exactly the same structure.
This patch makes the kernel use of_phandle_args everywhere. This in
itself isn't a big deal, but it makes some follow-on patches simpler.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The OF irq handling code has been overloading the term 'map' to refer to
both parsing the data in the device tree and mapping it to the internal
linux irq system. This is probably because the device tree does have the
concept of an 'interrupt-map' function for translating interrupt
references from one node to another, but 'map' is still confusing when
the primary purpose of some of the functions are to parse the DT data.
This patch renames all the of_irq_map_* functions to of_irq_parse_*
which makes it clear that there is a difference between the parsing
phase and the mapping phase. Kernel code can make use of just the
parsing or just the mapping support as needed by the subsystem.
The patch was generated mechanically with a handful of sed commands.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Acked-by: Michal Simek <monstr@monstr.eu>
Acked-by: Tony Lindgren <tony@atomide.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
DMA mapping permissions were being derived from pgprot_kernel directly
without using PAGE_KERNEL. This causes them to be marked with executable
permission, which is not what we want. Fix this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Conflicts:
drivers/net/usb/qmi_wwan.c
include/net/dst.h
Trivial merge conflicts, both were overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
Architectures which support CONFIG_PARPORT_PC should select
ARCH_MIGHT_HAVE_PC_PARPORT.
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: linux-arm-kernel@lists.infradead.org
The CODEC power supplies should be looked up on the Arizona device as
they will be created here by device tree also update the only user of
non-device tree bindings.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
The Armada 370/XP SoC has a clock provider called "Core Divider",
that is derived from a fixed 2 GHz PLL clock.
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Armada 370/XP SoCs have a 2 GHz fixed PLL that is used to feed
other clocks. This commit adds a DT representation of this clock
through a fixed-clock compatible node.
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add OPP table to OMAP5/DRA7
Add support for Newflow NanoBone board
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Merge tag 'for_3.13_super_late/dts_signed' of git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt into omap-for-v3.13/dt
Add a lot of N900 nodes
Add OPP table to OMAP5/DRA7
Add support for Newflow NanoBone board
When the omap5-evm.dts file has been renamed to omap5-uevm.dts and the sEVM
support got deprecated in favor of uEVM (or Panda5) the content was not
validated.
Panda5 does not have support for digital microphones so remove the pinmux
section for it.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
When the omap5-evm.dts file has been renamed to omap5-uevm.dts and the sEVM
support got deprecated in favor of uEVM (or Panda5) the content was not
validated.
On uEVM the twl6040 reset GPIO is from gpio5_141 and not via gpio5_145, which
was the case in sEVM.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
This patch adds support for Nokia N900 TLV320AIC3X chips.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add RX51_LCD_RESET_GPIO pin mux information to
display.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
This patch adds supports for Nokia N900 NAND memory.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add regulator names and voltage information to
the Nokia N900 DTS file.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
The twl4030.dtsi is missing some regulators. This patch adds
the missing ones and orders the regulators alphabetically.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add device tree node for the GPIO keys provided by the
N900 board. This is a simple conversion of the existing
board code.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add pin muxing support for the Nokia N900 i2c controllers.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Pull networking fixes from David Miller:
"Sorry I let so much accumulate, I was in Buffalo and wanted a few
things to cook in my tree for a while before sending to you. Anyways,
it's a lot of little things as usual at this stage in the game"
1) Make bonding MAINTAINERS entry reflect reality, from Andy
Gospodarek.
2) Fix accidental sock_put() on timewait mini sockets, from Eric
Dumazet.
3) Fix crashes in l2tp due to mis-handling of ipv4 mapped ipv6
addresses, from François CACHEREUL.
4) Fix heap overflow in __audit_sockaddr(), from the eagle eyed Dan
Carpenter.
5) tcp_shifted_skb() doesn't take handle FINs properly, from Eric
Dumazet.
6) SFC driver bug fixes from Ben Hutchings.
7) Fix TX packet scheduling wedge after channel change in ath9k driver,
from Felix Fietkau.
8) Fix user after free in BPF JIT code, from Alexei Starovoitov.
9) Source address selection test is reversed in
__ip_route_output_key(), fix from Jiri Benc.
10) VLAN and CAN layer mis-size netlink attributes, from Marc
Kleine-Budde.
11) Fix permission checks in sysctls to use current_euid() instead of
current_uid(). From Eric W Biederman.
12) IPSEC policies can go away while a timer is still pending for them,
add appropriate ref-counting to fix, from Steffen Klassert.
13) Fix mis-programming of FDR and RMCR registers on R8A7740 sh_eth
chips, from Nguyen Hong Ky and Simon Horman.
14) MLX4 forgets to DMA unmap pages on RX, fix from Amir Vadai.
15) IPV6 GRE tunnel MTU upper limit is miscalculated, from Oussama
Ghorbel.
16) Fix typo in fq_change(), we were assigning "initial quantum" to
"quantum". From Eric Dumazet.
17) Set a more appropriate sk_pacing_rate for non-TCP sockets, otherwise
FQ packet scheduler does not pace those flows properly. Also from
Eric Dumazet.
18) rtlwifi miscalculates packet pointers, from Mark Cave-Ayland.
19) l2tp_xmit_skb() can be called from process context, not just softirq
context, so we must always make sure to BH disable around it. From
Eric Dumazet.
20) On qdisc reset, we forget to purge the RB tree of SKBs in netem
packet scheduler. From Stephen Hemminger.
21) Fix info leak in farsync WAN driver ioctl() handler, from Dan
Carpenter and Salva Peiró.
22) Fix PHY reset and other issues in dm9000 driver, from Nikita
Kiryanov and Michael Abbott.
23) When hardware can do SCTP crc32 checksums, we accidently don't
disable the csum offload when IPSEC transformations have been
applied. From Fan Du and Vlad Yasevich.
24) Tail loss probing in TCP leaves the socket in the wrong congestion
avoidance state. From Yuchung Cheng.
25) In CPSW driver, enable NAPI before interrupts are turned on, from
Markus Pargmann.
26) Integer underflow and dual-assignment in YAM hamradio driver, from
Dan Carpenter.
27) If we are going to mangle a packet in tcp_set_skb_tso_segs() we must
unclone it. This fixes various hard to track down crashes in
drivers where the SKBs ->gso_segs was changing right from underneath
the driver during TX queueing. From Eric Dumazet.
28) Fix the handling of VLAN IDs, and in particular the special IDs 0
and 4095, in the bridging layer. From Toshiaki Makita.
29) Another info leak, this time in wanxl WAN driver, from Salva Peiró.
30) Fix race in socket credential passing, from Daniel Borkmann.
31) WHen NETLABEL is disabled, we don't validate CIPSO packets properly,
from Seif Mazareeb.
32) Fix identification of fragmented frames in ipv4/ipv6 UDP
Fragmentation Offload output paths, from Jiri Pirko.
33) Virtual Function fixes in bnx2x driver from Yuval Mintz and Ariel
Elior.
34) When we removed the explicit neighbour pointer from ipv6 routes a
slight regression was introduced for users such as IPVS, xt_TEE, and
raw sockets. We mix up the users requested destination address with
the routes assigned nexthop/gateway. From Julian Anastasov and
Simon Horman.
35) Fix stack overruns in rt6_probe(), the issue is that can end up
doing two full packet xmit paths at the same time when emitting
neighbour discovery messages. From Hannes Frederic Sowa.
36) davinci_emac driver doesn't handle IFF_ALLMULTI correctly, from
Mariusz Ceier.
37) Make sure to set TCP sk_pacing_rate after the first legitimate RTT
sample, from Neal Cardwell.
38) Wrong netlink attribute passed to xfrm_replay_verify_len(), from
Steffen Klassert.
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (152 commits)
ax88179_178a: Add VID:DID for Samsung USB Ethernet Adapter
ax88179_178a: Correct the RX error definition in RX header
Revert "bridge: only expire the mdb entry when query is received"
tcp: initialize passive-side sk_pacing_rate after 3WHS
davinci_emac.c: Fix IFF_ALLMULTI setup
mac802154: correct a typo in ieee802154_alloc_device() prototype
ipv6: probe routes asynchronous in rt6_probe
netfilter: nf_conntrack: fix rt6i_gateway checks for H.323 helper
ipv6: fill rt6i_gateway with nexthop address
ipv6: always prefer rt6i_gateway if present
bnx2x: Set NETIF_F_HIGHDMA unconditionally
bnx2x: Don't pretend during register dump
bnx2x: Lock DMAE when used by statistic flow
bnx2x: Prevent null pointer dereference on error flow
bnx2x: Fix config when SR-IOV and iSCSI are enabled
bnx2x: Fix Coalescing configuration
bnx2x: Unlock VF-PF channel on MAC/VLAN config error
bnx2x: Prevent an illegal pointer dereference during panic
bnx2x: Fix Maximum CoS estimation for VFs
drivers: net: cpsw: fix kernel warn during iperf test with interrupt pacing
...
Add DT OPP table for DRA7xx family of devices. This data is decoded by
OF with of_init_opp_table() helper function.
The data is based on DRA75x, DRA74x Data Manual revision F (Sept 2013).
TODO: add OPP_HIGH after AVS-Class0 is functional
NOTE: The voltage and frequency values work well only on NOM samples
and it is mandatory to use ABB/AVS Class 0 support for all OPPs.
Clock nodes are pending clock node alignment.
[nm@ti.com: cleanups and rebase to latest]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add DT OPP table for OMAP54xx family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
The data is based on OMAP543x ES2.0 DM Operating Condition Addendum
Version 0.6(April 2013)
NOTE: The voltage and frequency values work well only on NOM samples
and are supposed to work properly only with ABB/AVS for ALL OPPs.
TODO: Add SPEED BIN OPP after ABB and AVS support so the cpufreq works
on all samples seamlessly. Clock node is pending alignment for clock
dts conversion
[nm@ti.com: sync to latest and fixes]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
regulator smps123 supply from Palmas PMIC powers CPU0 on OMAP5uEVM.
Based on a patch by J Keerthy <j-keerthy@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
With OMAP3+ and AM33xx supported SoC having defined CPU device tree
entries with operating-points and clock nodes defined, we can now use
the SoC generic cpufreq-cpu0 driver by registering appropriate device.
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM335x, AM43xx, OMAP5 and DRA7 have missing late init hook. Introduce
SoC specific hook with a call to OMAP2+ generic lateinit hook. This
allows the generic late initializations such as cpufreq hooks to be
active.
Based on out-of-tree patches that need to be introduced in
mainline, this introduction allows us to provide the foundation for
further SoC specific features as they are developed.
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP3+ supports both device tree and non-device tree boot.
Device tree bindings for OMAP3+ is supposed to be added via dts following:
Documentation/devicetree/bindings/power/opp.txt
Since we now have device tree entries for OMAP3+ cpu OPPs,
The current code wrongly adds duplicate OPPs. So, dont register OPPs
when booting using device tree.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The KVM PSCI code blindly assumes that vcpu_id and MPIDR are
the same thing. This is true when vcpus are organized as a flat
topology, but is wrong when trying to emulate any other topology
(such as A15 clusters).
Change the KVM PSCI CPU_ON code to look at the MPIDR instead
of the vcpu_id to pick a target CPU.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Now that the KVM/arm code knows about affinity, remove the hard
limit of 4 vcpus per VM.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
The L2CTLR register contains the number of CPUs in this cluster.
Make sure the register content is actually relevant to the vcpu
that is being configured by computing the number of cores that are
part of its cluster.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
In order to be able to support more than 4 A7 or A15 CPUs,
we need to fix the MPIDR computing to reflect the fact that
both A15 and A7 can only exist in clusters of at most 4 CPUs.
Fix the MPIDR computing to allow virtual clusters to be exposed
to the guest.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Correct mcspi pin descriptions to match corresponding node name and
add chip select number to be consistent with OMAP5 TRM.
Signed-off-by: Eric Witcher <ewitcher@mindspring.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Control module is not usb specific.
Changes the label to usb_ctrl_mod.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
am33xx has a INTC_PENDING_IRQ3 register that is not checked for pending
interrupts. This patch adds AM33XX to the ifdef of SOCs that have to
check this register.
Cc: stable@vger.kernel.org
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM43x has 224 interrupts and 7 banks, make it as maximum values. Keep
default values as earlier, if am43x is detected, update interrupts and
banks accordingly.
Also AM43x has only one cpu, ensure that clearing bitmask at wakeupgen
is done only for the single existing cpu, existing code assumes that
there are two cpu's.
If bitmask is cleared in wakeupgen for the nonexistent second cpu,
an imprecise abort happens as soon as Kernel switches to user space.
It was rootcaused by Sekhar Nori <nsekhar@ti.com>.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
NanoBone Specification:
-----------------------
CPU:
TI AM335x
Memory:
256MB DDR3
128MB NOR flash
128KB FRAM
Ethernet:
2 x 10/100 connected to SMSC LAN8710 PHY
USB:
1 x USB2.0 Type A
I2C:
2Kbit EEPROM (Microchip 24AA02)
RTC (Maxim DS1338)
GPIO Expander (Microchip MCP23017)
Expansion connector:
6 x UART
1 x MMC/SD
1 x USB2.0
Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Looks like omap3 is still relying on hwmod data for some basic
device tree information. Let's add the information to omap3.dtsi
so we can remove the related hwmod data once omap3 is DT only.
Acked-by: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Provide alias to allow ordering the i2c devices correctly.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Currently, on OMAP5, i2c1 and i2c5 defer probe due to pinctrl
dependencies. This changes the i2c ID each bus is registered with in
i2c-dev interface. As a result of this, many userspace tools break and
there is no consistent manner to fix the same if the i2c dev interface
have no consistent numbering.
Since this could happen for other OMAP derivatives, provide i2c alias
for all OMAP3+ SoCs to allow ordering the i2c devices correctly.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Add nodes for McASP0 and McASP1 for AM43xx.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Several configurations are selecting errata 798181 without SMP
being selected. This causes a warning from Kconfig:
warning: (ARCH_HIGHBANK && ARCH_KEYSTONE && SOC_OMAP5 && ARCH_TEGRA_114_SOC) selects ARM_ERRATA_798181 which has unmet direct dependencies (CPU_V7 && SMP)
The dependencies are compile time dependencies; select violates these,
resulting in:
arch/arm/kernel/built-in.o: In function `setup_processor':
psci.c:(.init.text+0x808): undefined reference to `erratum_a15_798181_init'
at build time. Fix this by fixing the select statements for Tegra and
Highbank.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The imx6sl low power mode implementation inherits imx6q/dl one,
and pm-imx6q.c can just work for imx6sl with some minor updates.
Let's enable imx6sl suspend support by reusing pm-imx6q.c and use
cpu_is_imxXX() to handle the those minor differences between imx6sl
and imx6q/dl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
There is a defect in imx6 LPM design. When SW tries to enter low power
mode with following sequence, the chip will enter low power mode before
A9 CPU execute WFI instruction:
1. Set CCM_CLPCR[1:0] to 2'b00;
2. ARM CPU enters WFI;
3. ARM CPU wakeup from an interrupt event, which is masked by GPC or not
visible to GPC, such as interrupt from local timer;
4. Set CCM_CLPCR[1:0] to 2'b01 or 2'b10;
5. ARM CPU execute WFI.
Before the last step, the chip will enter WAIT mode if CCM_CLPCR[1:0] is
set to 2'b01, or enter STOP mode if CCM_CLPCR[1:0] is set to 2'b10.
The patch implements a recommended workaround for this issue.
1. SW triggers irq #32(IOMUX) to be always pending manually by setting
IOMUX_GPR1_GINT bit;
2. SW should then unmask it in GPC before setting CCM LPM;
3. SW should mask it right after CCM LPM is set (bit0-1 of CCM_CLPCR).
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The WB and RBC configuration calls are currently made from
imx6q_set_lpm() for WAIT_CLOCKED and WAIT_UNCLOCKED mode with a simple
state tracking. This becomes unnecessary since we can make the calls
from imx6q_pm_enter() directly now for suspend.
More importantly, the current call of imx6q_enable_wb() from
imx6q_set_lpm() is buggy. The CLPCR register bits configured by
imx6q_enable_wb() will get lost, because imx6q_set_lpm() caches the same
register and write it back at the end of the function. That's why the
imx6dl suspend/resume does not work currently - the wakeup from suspend
triggers a reset on imx6dl.
Moves the WB and RBC calls into imx6q_pm_enter() to save the state
tracking and fixes above bug, so that suspend/resume can start working
on imx6dl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The LPM (Low Power Mode) code that currently sits in imx6q clock driver
will be reused by imx6sl. Let's move it into pm-imx6q.c, so that we
can keep clock driver SoC specific and reuse pm-imx6q.c on imx6sl.
In order to avoid adding another ioremap for CCM block,
imx6q_pm_set_ccm_base() is created to let clock driver set up ccm_base
for pm code.
During the move, the unused CCGR macros get removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since commit 70dc8a4 (checkpatch: warn when using extern with function
prototypes in .h files), we will get checkpatch warning when updating
common.h following the existing convention which has extern for function
prototypes.
Let's change the convention to not use extern with function prototypes
in this header.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
From hotplug stress test result, resetting core during enable/disable
operation can improve cpu hotplug stability. So let's set
SRC reset bit in imx_enable_cpu() for the core when its enable bit is
accessed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
When imx_cpu_die() is being called, the cpu should never return from the
call but just in WFI and wait for hardware to take it down. So let's
do cpu_do_idle() repeatly in the call. Doing this help improve the
relibility of hotplug operation.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This is very useful for detecting 'circular locking dependency' issues.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Having CONFIG_DEBUG_GPIO=y leads to several debug messages polluting kernel log:
[ 0.580325] of_get_named_gpio_flags: can't parse gpios property of node '/regulators/3p3v[0]'
[ 0.581185] 3P3V: 3300 mV
[ 0.584827] of_get_named_gpio_flags exited with status 124
[ 0.585852] vddio-sd0: 3300 mV
[ 0.590023] of_get_named_gpio_flags exited with status 79
[ 0.590770] fec-3v3: 3300 mV
[ 0.594805] of_get_named_gpio_flags exited with status 105
[ 0.595491] usb0_vbus: 5000 mV
[ 0.599687] of_get_named_gpio_flags exited with status 104
[ 0.600380] usb1_vbus: 5000 mV
[ 0.604463] of_get_named_gpio_flags exited with status 126
[ 0.605153] lcd-3v3: 3300 mV
[ 0.608970] of_get_named_gpio_flags exited with status 77
Turn this option off, as these messages are not really useful for normal usage.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The imx6q_restart() works fine with normal reboot but will run into
problem with emergency reboot like sysrq-b. In that case, of_iomap()
gets called from interrupt context and hence triggers the BUG_ON in
__get_vm_area_node().
Actually, since commit c1e31d1 (ARM: imx: create
mxc_arch_reset_init_dt() for DT boot), imx6q/dl should try to use
mxc_restart() by calling mxc_arch_reset_init_dt() beforehand, where
things like of_iomap() can be done.
The patch updates mxc_restart() a little bit to get it work for imx6q/dl
and kill imx6q_restart() completely.
Reported-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As mx53 is a dt-only SoC, we should retrieve the iomuxc base address from the
device tree, instead of using the old MX53_IO_ADDRESS method.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As mx53 is a dt-only SoC, we should retrieve the tzic base address from the
device tree, instead of using the old MX53_IO_ADDRESS method.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As mx53 is a dt-only SoC, we should retrieve the gpt base address and irq
from the device tree, instead of using the old MX53_IO_ADDRESS method.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The IS_ERR() macro is defined in the linux/err.h header file, so include
it explicitly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6 has two general-purpose LVDS clocks that can be driven
from a variety of sources. This patch adds a mux and a gate for
both of these clocks.
Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The patch enables soc bus infrastructure and adds a function
imx_soc_device_init() to report soc info via soc device interface for
imx6qdl and imx6sl. With the support, user space can get soc related
info by looking at sysfs like below.
$ cat /sys/devices/soc0/machine
Freescale i.MX6 Quad SABRE Smart Device Board
$ cat /sys/devices/soc0/family
Freescale i.MX
$ cat /sys/devices/soc0/soc_id
i.MX6Q
$ cat /sys/devices/soc0/revision
1.2
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add imx6sl support into imx_init_revision_from_anatop(), so that it can
be used to initialize cpu type and revision on imx6sl.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The patch creates a common function imx_init_revision_from_anatop() by
merging imx6q_init_revision() and imx_anatop_get_digprog(), so that any
SoC that encodes revision info in anatop can use it to initialize
revision.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It calls imx_set_soc_revision() to set up soc revision in
imx6q_init_revision(), and replaces all the occurrences of
imx6q_revision() with common helper imx_get_soc_revision().
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Similar to what we do for cpu type, the patch adds helper functions
imx_set_soc_revision() and imx_get_soc_revision() to maintain
imx_soc_revision in cpu.c.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add low-level debug support for vybrid, so that earlyprintk can be
enabled for debugging early boot issue.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This flag is a NOOP since 2.6.35 and can be removed.
This is an update for 3.11 of a patch already sent for 3.10
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Config iomux-gpr1 to select clock source for fec system clock.
Clear gpr1[14], gpr1[18-17] bit to select the fec clock source
from internal anatop PLL.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
There's a pll4_audio_div clock, an extra divider for pll4, missing
in current clock tree, thus add it.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
EXYNOS is now Device Tree (DT) only platform so it makes no sense to have
config options responsible for enabling platform specific DT support.
Moreover the kernel image won't even link if neither CONFIG_MACH_EXYNOS4_DT
nor CONFIG_MACH_EXYNOS5_DT config option is enabled (linker fails with "no
machine record defined" error).
Remove CONFIG_MACH_EXYNOS[4,5]_DT config options and just use the standard
CONFIG_ARCH_EXYNOS[4,5] ones instead.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
s3c2410 and s3c2442 share the same dma channels while s3c2440 has
slight differences. But on all three the reachable sources per dma
channel has constraints attached and thus encodes the usable
combinations using the S3C24XX_DMA_CHANREQ macro.
This also fixes the warning about s3c2410_dma_resource being unused
as reported by Olof Johansson.
Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Currently the s3c sound support selects CONFIG_S3C2410_DMA on s3c24xx
architectures while the generic dma config is enabled by CONFIG_S3C24XX_DMA.
With the way the Kconfig options are layed out currently it is possible
to enable Samsung sound support without enabling the necessary dma support
resulting in warnings like
warning: (SND_SOC_SAMSUNG && SND_S3C24XX_I2S && SND_S3C2412_SOC_I2S &&
SND_SOC_SAMSUNG_SMDK2443_WM9710 && SND_SOC_SAMSUNG_LN2440SBC_ALC650)
selects S3C2410_DMA which has unmet direct dependencies (ARCH_S3C24XX &&
S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442))
Therefore bring the s3c2410 dma support in line with the way the other
s3c24xx SoCs handle this by having the SoC dma-support selected if the generic
s3c dma support is enabled and have the sound support depend on S3C24XX_DMA
on these arches. The s3c2442 is using the same dma descriptors and therefore
also selected S3C2410_DMA.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The generic PHY framewrok expects different properties than the
old USB PHY framework. Supply those properties.
Fixes USB OTG port on beagle after the Generic PHY framework was
merged in greg/usb-next. [1]
[1] - https://lkml.org/lkml/2013/9/27/581
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
AM335x EVM-SK have only support for audio playback (stereo jack on the
board) via tlv320aic3106 codec connected to McASP1.
Enable the support for audio playback on the board:
- McASP1 configuration
- tlv320aic3106 configuration
- Machine driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
This patch adds a second tuple to reg property. The new property tuple
describes the memory location for data port registers mapped trough
L3 bus on am33xx. The both property tuples are named accordingly in
the reg-names property.
Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Darren Etheridge <detheridge@ti.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
-> Adding pinmux for cpsw, i2c0.
-> Enabling the modules that are present in AM4372 EPOS EVM
These modules are tested on AM4372 EPOS EVM.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Populate nodes for l2-cache-controller, EDMA, mailbox,
mmc, sham.
Update as well DT properties for epwmss, aes, des.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Added dr_mode property in dwc3 and set its default mode to device.
Signed-off-by: George Cherian <george.cherian@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
smps10 should be enabled only in the case of host mode. So stop
doing always_on, boot_on from smps10_out1. The driver will enable
it in host mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Do not reset GPIO1 at boot-up because GPIO 7 in GPIO1 block is used on
OMAP4460 PandaBoard-ES to select voltage register in TPS62361 which
supplies VDD_MPU.
Without this, OMAP4460 PandaBoard-ES boards fail to boot-up because
MPU voltage switches over to VSET0 voltage value (boot voltage) which
is not sufficient to operate the device at OPP100.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Do not reset GPIO0 at boot-up because GPIO0 is used
on AM335x EVM-SK to control VTT regulators on DDR3.
Without this EVM-SK boards fail to boot-up because
of DDR3 corruption.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
On OMAP we have co-processor IPs, memory controllers,
GPIOs which control regulators and power switches to
PMIC, and SoC internal Bus IPs, some or most of which
should either not be reset or idled or both at init.
(In some cases there are erratas which prevent an IP
from being reset)
Have a way to pass this information from DT.
Update the am33xx/omap4 and omap5 dtsi files with the
new bindings for modules which either should not be
idled. reset or both. A later patch would cleanup the
same information that exists today as part of the hwmod
data files.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
The generic PHY framewrok expects different properties than the
old USB PHY framework. Supply those properties.
Fixes USB OTG port on GAT04 and N900 after the Generic PHY framework was
merged in greg/usb-next. [1]
[1] - https://lkml.org/lkml/2013/9/27/581
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
The arm arch timers frequency are now programmed in the CNTFREQ
per-cpu register by the timer code using the secure API [1].
So remove the redundant entry from the dts.
[1] http://marc.info/?l=linux-omap&m=138139106312786&w=2
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Generate ep93xx_defconfig by doing:
make ep93xx_defconfig
make savedefconfig
mv defconfig arch/arm/configs/ep93xx_defconfig
No function change. This just refreshes the ep93xx_defconfig to make it
easier and cleaner when adding new entries.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Ryan Mallon <rmallon@gmail.com>
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Olof Johansson <olof@lixom.net>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In order for ASID macro to be used as expression passed to
inline asm as 'r' operand it needs to give 32 bit unsigned result,
not unsigned 64bit expression.
Otherwise when 64bit ASID is passed to inline assembler statement
as 'r' operand (32bit) compiler behavior is not well specified.
For example when __flush_tlb_mm function compiled in big endian
case, and ASID is passed to tlb_op macro directly, 0 will be passed
as 'mcr 15, 0, r4, cr8, cr3, {2}' argument in r4, unless ASID
macro changed to produce 32 bit result.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
In big endian mode mcpm_entry_point is first function
that called on secondaries CPU. First it should switch
CPU into big endian code.
[ben.dooks@codethink.co.uk: merge fix patch from Victor into this]
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
In case of BE8 kernel data is in BE order whereas code stays in LE
order. Move sigreturn_codes to separate .S file and use proper
assembler mnemonics for these code snippets. In this case compiler
will take care of proper instructions byteswaps for BE8 case.
Change assumes that sufficiently Thumb-capable tools are used to
build kernel.
Problem was discovered during ltp testing of BE system: all rt_sig*
tests failed. Tested against the same tests in both BE and LE modes.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Fix inline asm for atomic64_xxx functions in arm atomic.h. Instead of
%H operand specifiers code should use %Q for least significant part
of the value, and %R for the most significant part of the value. %H
always returns the higher of the two register numbers, and therefore
it is not endian neutral. %H should be used with ldrexd and strexd
instructions.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
The arch_kgdb_breakpoint() function uses an inline assembly directive
to assemble a specific instruction using .word. This means the linker
will not treat is as an instruction, and therefore incorrectly swap
the endian-ness if running BE8.
As noted, this code means that kgdb is really only usable on arm32
kernels, and should be made dependant on not being a thumb2 kernel
until fixed. However this is not something to be added to this patch.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Currently BUG() uses .word or .hword to create the necessary illegal
instructions. However if we are building BE8 then these get swapped
by the linker into different illegal instructions in the text. This
means that the BUG() macro does not get trapped properly.
Change to using <asm/opcodes.h> to provide the necessary ARM instruction
building as we cannot rely on gcc/gas having the `.inst` instructions
which where added to try and resolve this issue (reported by Dave Martin
<Dave.Martin@arm.com>).
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Use <asm/opcodes.h> to correctly transform instruction byte ordering
into in-memory ordering.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
The <hardware/coresight.h> needs to take into account the endian-ness
of the processor when reading and writing data, so change to using
the readl/writel relaxed variants from the raw ones.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
To avoid having to make every text section swap the instruction order
of all instructions, make sure modules are built also built with --be8
(as is the current kernel final link).
If we do not do this, we would end up having to swap all instructions
when loading a module, instead of just the instructions that we are
applying ELF relocations to.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
When in BE8 mode, our instructions are not in the same ordering as the
data, so use <asm/opcodes.h> to take this into account.
Note, also requires modules to be built --be8
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
The trap handler needs to take into account the endian configuration of
the system when loading instructions. Use <asm/opcodes.h> to provide the
necessary conversion functions.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
If we are in BE8 mode, we must deal with the instruction stream being
in LE order when data is being loaded in BE order. Ensure the data is
swapped before processing to avoid thre following:
Change to using <asm/opcodes.h> to provide the necessary conversion
functions to change the byte ordering.
This stops the following warning messages from the kernel on a fault:
Unhandled fault: alignment exception (0x001) at 0xbfa09567
Alignment trap: not handling instruction 030091e8 at [<80333e8c>]
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Apart from a xgmac driver issue, the highbank seems to work correctly in
big-endian mode. Allow the selection of big-endian in the system.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Rob Herring <rob.herring@calxeda.com>
The smp_scu driver needs to use the relaxed readl/write accessors
to avoid any issues with the endian mode the processor core is in.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Ensure the twd driver uses the correct calls to access the hardware
to ensure that we do not end up with data in the wrong endian format.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
The PL01X debug code needs to take into account which endian mode the
processor is running in. If it is big-endian, ensure the data is swapped
appropriately.
Note, we could do this slightly more efficiently if we have an macro to
do the necessary swap for the bits used by test.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
If we are booting in LE and compiled for BE8, then add code to
set the state to bE8. Since the instruction stream is always LE,
we do not need to do anything special to the instruction.
Also ensure that the secondary processors are started in the same mode.
Note, we do add about 20 bytes to the kernel image, but it seems easier
to do this than adding another configuration to change.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
The fixup_pv_table assumes that the instructions are in the same
endian configuration as the data, but when the CPU is running in
BE8 the instructions stay in little-endian format.
Make sure if CONFIG_CPU_ENDIAN_BE8 is set that we do all the
alterations to the instructions taking in to account the LDR/STR
will be swapping the data endian-ness.
Since the code is only modifying a byte, we avoid dual-swapping
the data, and just change the bits we clear and ORR in (in the
case where the code is not thumb2).
For thumb2, we add the necessary rev16 instructions to ensure that
the instructions are processed in the correct format, as it was
easier than re-writing the code to contain a mask and shift.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Add ARM_BE8() helper to wrap any code conditional on being
compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert
existing places where this is to use it.
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
The Kconfig for arch/arm/mach-ixp4xx has a local definition
of ARCH_SUPPORTS_BIG_ENDIAN which could be used elsewhere.
This means that if IXP4xx is selected and this symbol is
selected eleswhere then an warning is produced.
Clean the following error up by making the symbol be
selected by the main ARCH_IXP4XX definition and have a
common definition in arch/arm/mm/Kconfig
warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX)
warning: (ARCH_xxx) selects ARCH_SUPPORTS_BIG_ENDIAN which has unmet direct dependencies (ARCH_IXP4XX)
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
OMAP3 PM core requires IVA2 bootmode to be set to idle during init. Currently,
a direct register write is used for this. Add a new ctrl API for this purpose
instead.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
OMAP3 PM code for off-mode currently saves the scratchpad contents for CM
registers within OMAP control module driver. However, as we are separating
CM code into its own driver, this must be moved also. This patch adds a
new API for saving the CM scratchpad contents and uses this from the high
level scratchpad save function.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
McBSP driver require special hacks to enable/disable the autoidle feature
for its interface clock for the proper function of the sidetone hardware.
Currently the driver just writes CM registers directly, which should be
avoided. Thus, changed the driver to use the new deny/allow_autoidle
clock API calls.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some drivers require direct access to the autoidle functionality of the
interface clocks. Added clock APIs for these, so that the drivers do not
need to access CM registers directly.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Users of the CM funtionality should not access the CM registers directly
by themselves. Thus, added new CM driver APIs for the OMAP2 specific
functionalities which support the existing direct register accesses, and
changed the platform code to use these. This is done in preparation
for moving the CM code into its own individual driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Extend the list of power gates found on Tegra114. Note that there are
now holes in the list, so perhaps a simple array is no longer the best
data structure to represent it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
There's no need to modify these at runtime, it is static data and never
needs to change.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Instead of duplicating powergate defines, reuse the ones from the
include/linux/tegra-powergate.h header file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
need to update the difference of the register address, then we can
continue to share the code.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch re-calculates the LP1 data of tegra30/114_sdram_pad_address
to base on its label not rely on others. This can make easier to
maintain if some other Tegra chips keep re-using these codes in the
future. And change the name of tegra30_sdram_pad_save to
tegra_sdram_pad_save to make it more common to other chips.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The CPUIdle function of Tegra124 is identical to Tegra114, so we share
the same driver with Tegra114.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Because the CPU0 was the first up and the last down core when cluster
power up/down or platform suspend. So only CPU0 needs the rest of the
functions to reset flow controller and re-enable SCU and L2. We also
move the L2 init function for Cortex-A15 to there. The secondery CPU
can just call cpu_resume.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The procedure of CPU hotplug for Tegra124 is same with Tegra114. We
re-use the same function with it.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The PMC HW is not identical to the existing Tegra SoC. Hence add to it.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add Tegra124 SoC support that base on CortexA15MP Core. And enable the
SMP function that can re-use the same procedure with Tegra114.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Various fuses on Tegra include information that's unique to an individual
chip, or a subset of chips. Call add_device_randomness() with this data
to perturb the initial state of the random pool.
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
omap3 boards.
Note that that these are based on a merge of the
following for the dependencies:
- v3.12-rc5 for fixes to pinctrl mask
- omap-for-v3.13/dt-signed to avoid pointless merge conflicts
- omap-for-v3.13/quirk-signed for legacy pdata handling
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Merge tag 'omap-for-v3.13/board-removal-signed-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren:
Changes needed to drop legacy booting support for some
omap3 boards.
Note that that these are based on a merge of the
following for the dependencies:
- v3.12-rc5 for fixes to pinctrl mask
- omap-for-v3.13/dt-signed to avoid pointless merge conflicts
- omap-for-v3.13/quirk-signed for legacy pdata handling
* tag 'omap-for-v3.13/board-removal-signed-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (125 commits)
ARM: OMAP2+: remove legacy support for IGEP boards
ARM: OMAP2+: Remove legacy support for zoom platforms
ARM: OMAP2+: Remove legacy booting support for omap3 EVM
ARM: OMAP2: delete board-rm680
ARM: dts: add minimal DT support for Nokia N950 & N9 phones
ARM: dts: Add basic support for zoom3
ARM: dts: Add basic support for TMDSEVM3730 (Mistral AM/DM37x EVM)
ARM: dts: Add common support for omap3-evm
ARM: dts: Shared file for omap GPMC connected smsc911x
+Linux 3.12-rc5
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Commit f8e7ba66 (ARM: OMAP1: fix incorrect placement of
__initdata tag) fixed things but we started seeing section
warnings. Looks like I missed those in my automatic
build scripts:
Section mismatch in reference from the variable omap7xx_gpio6 to the (unknown reference) .init.data:(unknown)
Section mismatch in reference from the variable omap7xx_gpio6 to the (unknown reference) .init.data:(unknown)
Section mismatch in reference from the variable omap7xx_gpio5 to the (unknown reference) .init.data:(unknown)
...
Fix the issue by removing __initdata for the resources.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Device Tree support for IGEP boards in mainline is almost
finished. The only remaining bits are support for the
Marvell SD8686 wifi + BT and TFP410 DVI chips.
Adding support for these should be straightforward so let's
not block OMAP3 moving to Device Tree only boot and remove
the board file for IGEP boards.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We now have pretty decent device tree based support for
zoom platforms. It's not complete, but basics work for
me so adding more features should be quite trivial.
Looks like also 3630 sdp is zoom based, and looking
at it's board file should also be trivial to support
with the device tree based booting.
Patches are welcome if people are still using these.
Signed-off-by: Tony Lindgren <tony@atomide.com>
We now have pretty decent support with the device tree
based booting. Patches to add more features are welcome.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Delete board file for Nokia RM-680/RM-696 (N950/N9). DT-based booting
should be used for further development on this HW.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add minimal DT support for Nokia N950 & N9 phones. The same functionality
that is provided by the current board file should work: serial console,
USB, OneNAND and MMC.
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
I've tested serial, MMC, smsc911x and wl12xx on zoom3. As my
omap is an early ES revision, I have not been able to test
off-idle on this one. But anyways, I'd say we have enough
device tree support for the zoom to be able to drop the
board-zoom files. Patches are welcome to add further features
to this .dts file.
Signed-off-by: Tony Lindgren <tony@atomide.com>
The imx6sl iomuxc syscon is compatible to imx6q, so let's add
compatible string 'fsl,imx6q-iomuxc-gpr' for imx6sl iomuxc syscon node.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
- addition of sound for at91sam9n12
- a little fix for MMC vs. SPI on at91sam9g20ek
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Merge tag 'at91-dt' of git://github.com/at91linux/linux-at91 into next/dt
From Nicolas Ferre:
First DT series for 3.13
- addition of sound for at91sam9n12
- a little fix for MMC vs. SPI on at91sam9g20ek
* tag 'at91-dt' of git://github.com/at91linux/linux-at91:
ARM: at91: remove pinctrl conflict between mmc and SPI for at91sam9g20ek
ARM: at91: add sound support on at91sam9n12ek board
ARM: at91: enable ssc on at91sam9n12ek board
ARM: at91: enable wm8904 on at91sam9n12ek board
ARM: at91: add ssc dma parameter for at91sam9n12
ARM: at91: add at91sam9n12 ssc clock in look up table
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- a little non-urgent fix
- addition of DT files to MAINTAINERS
- more important, the splitting of .dtsi files
that allows to precisely choose the peripherals
that are present for a particular SoC.
It is useful for upcoming move to common cloks.
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Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
From Nicolas Ferre:
First cleanup series for 3.13
- a little non-urgent fix
- addition of DT files to MAINTAINERS
- more important, the splitting of .dtsi files
that allows to precisely choose the peripherals
that are present for a particular SoC.
It is useful for upcoming move to common cloks.
* tag 'at91-cleanup' of git://github.com/at91linux/linux-at91:
MAINTAINERS: Add patterns for DTS files for AT91
ARM: at91: remove init_machine() as default is suitable
ARM: at91/dt: split sama5d3 peripheral definitions
ARM: at91/dt: split sam9x5 peripheral definitions
ARM: at91: cam60: fix incorrect placement of __initdata tag
This will be the last new set of hwmod data for any SoC
as future SoCs will use a driver and device tree based
approach. But before that can be dealt with, we need to
first sort out the pending driver/clk issues.
Queued by Paul Walmsley <paul@pwsan.com>:
Add hwmod and PRCM data for the TI AM43xx family of SoCs.
Under normal circumstances, these patches would not be merged.
The hwmod and PRCM data should be moved out either to DT data or
to drivers/. Also, the current implementation trades off lines
of diff by dynamically rewriting static data at runtime, which is
a bad practice - it causes future maintenance headaches.
However, after speaking with my upstream, it sounds like it's
better to merge these patches in their current state, due to long
term considerations.
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/am43xx_support_v3.13/20131015213706/
Due to the lack of an AM43xx board and any available public
documentation, it's impossible for me to review or test that
platform in any meaningful way. But at least the tests above
verify that the patches don't affect existing platforms -
particularly AM33xx.
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Merge tag 'omap-for-v3.13/am43xx-hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
Changes needed for am43xx for the hwmod data.
This will be the last new set of hwmod data for any SoC
as future SoCs will use a driver and device tree based
approach. But before that can be dealt with, we need to
first sort out the pending driver/clk issues.
Queued by Paul Walmsley <paul@pwsan.com>:
Add hwmod and PRCM data for the TI AM43xx family of SoCs.
Under normal circumstances, these patches would not be merged.
The hwmod and PRCM data should be moved out either to DT data or
to drivers/. Also, the current implementation trades off lines
of diff by dynamically rewriting static data at runtime, which is
a bad practice - it causes future maintenance headaches.
However, after speaking with my upstream, it sounds like it's
better to merge these patches in their current state, due to long
term considerations.
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/am43xx_support_v3.13/20131015213706/
Due to the lack of an AM43xx board and any available public
documentation, it's impossible for me to review or test that
platform in any meaningful way. But at least the tests above
verify that the patches don't affect existing platforms -
particularly AM33xx.
* tag 'omap-for-v3.13/am43xx-hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2: hwmod: Add qspi data for am437x.
ARM: OMAP2+: hwmod: Add USB hwmod data for AM437x.
ARM: OMAP2+: AM43x PRCM init
ARM: OMAP2+: AM43x: PRCM kbuild
ARM: OMAP2+: hwmod: AM43x operations
ARM: OMAP2+: hwmod: AM43x support
ARM: OMAP2+: CM: AM43x clockdomain data
ARM: OMAP2+: PM: AM43x powerdomain data
ARM: OMAP2+: PRCM: AM43x definitions
ARM: OMAP2+: hwmod: AM335x: remove static register offs
ARM: OMAP2+: hwmod: AM335x: runtime register update
ARM: OMAP2+: hwmod: AM335x/AM43x: move common data
ARM: OMAP2+: CM: cm_inst offset s16->u16
Signed-off-by: Kevin Hilman <khilman@linaro.org>
These MMC and SPI buses can't be configured at the same time because they
share the same traces on the EK board.
Reported-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
From Heiko Stübner:
Support for the RK3188 SoC, basic RK3188 based Radxa Rock board
and RK3066a based BQ Curie2 tablet.
* rockchip/boards:
ARM: rockchip: add support for rk3188 and Radxa Rock board
ARM: rockchip: add dts for bqcurie2 tablet
ARM: rockchip: enable arm-global-timer
ARM: rockchip: move shared dt properties to common source file
and fix for the selection of the TWD.
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Merge tag 'v3.13-rockchip-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes-non-critical
From Heiko Stübner:
Romoval of obsolete (never used) dt properties
and fix for the selection of the TWD.
* tag 'v3.13-rockchip-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: remove obsolete rockchip,config properties
ARM: rockchip: fix wrong use of non-existent CONFIG_LOCAL_TIMERS
This adds the SSP and SPI blocks to the device tree and makes
them active. Only this way can their clocks be properly gated
off at boot.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The PCLK for I2C4 is controlled by bit 10 in the PCKEN registers
while the KCLK is controlled by bit 9 on the KCKEN, it's
one of these odd assymetric things. Correct the PCLK bit to 10.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The clock assignment in the device tree for GPIO blocks 6
and 7 was incorrect, indicating this was managed by bit 1 on
PRCC 2 while it was in fact bit 11 on PRCC 2.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The clock assignment in the device tree for GPIO block 8 was
incorrect, indicating this was managed by bit 1 on PRCC 6
while it was in fact bit 1 on PRCC 5.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
add a pinctrl for ECSPI1. This pinctrl can be used in the imx6sl-evk board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The pwm-node is missing its #pwm-cells property. The pwm-framework will
complain about this.
Add the missing property.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Support transparent huge pages in KVM/ARM and KVM/ARM64. The
transparent_hugepage_adjust is not very pretty, but this is also how
it's solved on x86 and seems to be simply an artifact on how THPs
behave. This should eventually be shared across architectures if
possible, but that can always be changed down the road.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Support huge pages in KVM/ARM and KVM/ARM64. The pud_huge checking on
the unmap path may feel a bit silly as the pud_huge check is always
defined to false, but the compiler should be smart about this.
Note: This deals only with VMAs marked as huge which are allocated by
users through hugetlbfs only. Transparent huge pages can only be
detected by looking at the underlying pages (or the page tables
themselves) and this patch so far simply maps these on a page-by-page
level in the Stage-2 page tables.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
From Stephen Warren:
* tegra/dt:
ARM: tegra: Use symbolic names for gr3d clocks
ARM: tegra: Mark Tegra30 display controller compatible with Tegra20
ARM: tegra: add GPIO controller to tegra124.dtsi
ARM: tegra: enable LP1 suspend mode for Venice2
ARM: tegra: enable Tegra RTC as default for Tegra124
ARM: tegra: add Venice2 board support
ARM: tegra: Add initial device tree for Tegra124
ARM: tegra: add vcc supply for nct1008 to Cardhu
ARM: tegra: add DT entry for nct1008 to Dalmore
ARM: tegra: use dt-binding header for key code
ARM: tegra: add palmas pincontrol to Dalmore device tree
Signed-off-by: Kevin Hilman <khilman@linaro.org>
AT91 ADC hardware integrate touch screen support. So this patch add touch
screen support for at91 adc iio driver.
To enable touch screen support in adc, you need to add the dt parameters:
1. which type of touch are used? (4 or 5 wires), sample period time.
2. correct pressure detect threshold value.
In the meantime, since touch screen will use a interal period trigger of adc,
so it is conflict to other hardware triggers. Driver will disable the hardware
trigger support if touch screen is enabled.
This driver has been tested in AT91SAM9X5-EK and SAMA5D3x-EK.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
CC: devicetree@vger.kernel.org
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This branch mainly removes dead code and defines that were useful only
when booting using board files. A few other misc cleanups are also
included.
This branch is based on previous pull request
tegra-for-3.13-deps-for-arm-init-time-cleanup.
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Merge tag 'tegra-for-3.13-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup
ARM: tegra: cleanup for 3.13
This branch mainly removes dead code and defines that were useful only
when booting using board files. A few other misc cleanups are also
included.
This branch is based on previous pull request
tegra-for-3.13-deps-for-arm-init-time-cleanup.
* tag 'tegra-for-3.13-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order
ARM: tegra: make tegra_init_fuse() __init
ARM: tegra: remove much of iomap.h
ARM: tegra: move resume vector define to irammap.h
ARM: tegra: delete gpio-names.h
ARM: tegra: delete stale header content
ARM: tegra: remove common.c
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- convert Calxeda cpuidle driver to a platform driver and to use PSCI
- convert highbank smp_ops and suspend to PSCI
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Merge tag 'highbank-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next/soc
From Rob Herring:
Highbank platform updates for 3.13
- convert Calxeda cpuidle driver to a platform driver and to use PSCI
- convert highbank smp_ops and suspend to PSCI
* tag 'highbank-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
dts: calxeda: add ARM PSCI binding
ARM: highbank: adapt to use ARM PSCI calls
ARM: PSCI: remove unnecessary include of arm-gic.h
cpuidle: calxeda: add support to use PSCI calls
ARM: highbank: cpuidle: convert to platform driver
cpuidle: calxeda: add cpu_pm_enter/exit calls
Update comments to reflect what is really going on and add the TWE bit
to the comments in kvm_arm.h.
Also renames the function to kvm_handle_wfx like is done on arm64 for
consistency and uber-correctness.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
On an (even slightly) oversubscribed system, spinlocks are quickly
becoming a bottleneck, as some vcpus are spinning, waiting for a
lock to be released, while the vcpu holding the lock may not be
running at all.
This creates contention, and the observed slowdown is 40x for
hackbench. No, this isn't a typo.
The solution is to trap blocking WFEs and tell KVM that we're
now spinning. This ensures that other vpus will get a scheduling
boost, allowing the lock to be released more quickly. Also, using
CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT slightly improves the performance
when the VM is severely overcommited.
Quick test to estimate the performance: hackbench 1 process 1000
2xA15 host (baseline): 1.843s
2xA15 guest w/o patch: 2.083s
4xA15 guest w/o patch: 80.212s
8xA15 guest w/o patch: Could not be bothered to find out
2xA15 guest w/ patch: 2.102s
4xA15 guest w/ patch: 3.205s
8xA15 guest w/ patch: 6.887s
So we go from a 40x degradation to 1.5x in the 2x overcommit case,
which is vaguely more acceptable.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
- dove
- add audio devices
- fix bad properties of si5351 clkout2 for CuBox
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Merge tag 'dt-3.13-3' of git://git.infradead.org/linux-mvebu into next/dt
From Jason Cooper:
mvebu dt changes for v3.13 (round 3)
- dove
- add audio devices
- fix bad properties of si5351 clkout2 for CuBox
* tag 'dt-3.13-3' of git://git.infradead.org/linux-mvebu:
ARM: Dove: fix bad properties of the si5351 clkout2 used by Cubox audio
ARM: Dove: Add the audio device to the Cubox DT
ARM: Dove: Add the audio devices in DT
Some small cleanups for MSM. Removes extraneous irq definitions that
aren't used on DT targets, moves the single existing board file to
board-dt.c in antipication of additional targets, and renames the
existing DT files to have a common 'qcom' prefix.
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Merge tag 'msm-cleanup-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/cleanup
From David Brown:
General cleanups for MSM for 3.13
Some small cleanups for MSM. Removes extraneous irq definitions that
aren't used on DT targets, moves the single existing board file to
board-dt.c in antipication of additional targets, and renames the
existing DT files to have a common 'qcom' prefix.
* tag 'msm-cleanup-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm:
ARM: msm: Rename msm devicetrees to have standard 'qcom' prefix
ARM: msm: Create a common board-dt and config ARCH_MSM_DT
ARM: msm: Remove irqs-*.h files for DT based targets
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- Fix up the LED support
- Update the Integrator defconfig
- Remove ATAG boot path
- Move some stuff over to the device tree
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Merge tag 'integrator-for-v3.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/soc
From Linus Walleij:
Integrator patches for the v3.13 kernel cycle:
- Fix up the LED support
- Update the Integrator defconfig
- Remove ATAG boot path
- Move some stuff over to the device tree
* tag 'integrator-for-v3.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: integrator: core module registers from compatible strings
ARM: integrator: use devm_ioremap() to remap CM
cpufreq: probe the Integrator cpufreq driver from DT
ARM: integrator: move CM base into device tree
ARM: integrator: decommission the <mach/irqs.h> header
ARM: integrator: delete non-devicetree boot path
ARM: integrator: print the Linux IRQ in LL_DEBUG code
ARM: integrator: get the LM interrupts from DT
ARM: integrator: update defconfig
ARM: integrator: get the CM control register by proxy
Signed-off-by: Kevin Hilman <khilman@linaro.org>
clockevents_config_and_register is superior compared to setting
shift/mult and {min,max}_delta_ns by hand.
Tested-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
[nsekhar@ti.com: fix an alignment related checkpatch warning]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Commit 05849c9381 (ARM: tegra30: convert
device tree files to use CLK defines) updated the Tegra30 device tree to
use symbolic clock names but forgot to update this node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Under normal circumstances, these patches would not be merged.
The hwmod and PRCM data should be moved out either to DT data or
to drivers/. Also, the current implementation trades off lines
of diff by dynamically rewriting static data at runtime, which is
a bad practice - it causes future maintenance headaches.
However, after speaking with my upstream, it sounds like it's
better to merge these patches in their current state, due to long
term considerations.
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/am43xx_support_v3.13/20131015213706/
Due to the lack of an AM43xx board and any available public
documentation, it's impossible for me to review or test that
platform in any meaningful way. But at least the tests above
verify that the patches don't affect existing platforms -
particularly AM33xx.
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Merge tag 'for-v3.13/am43xx-support' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.13/hwmod
Add hwmod and PRCM data for the TI AM43xx family of SoCs.
Under normal circumstances, these patches would not be merged.
The hwmod and PRCM data should be moved out either to DT data or
to drivers/. Also, the current implementation trades off lines
of diff by dynamically rewriting static data at runtime, which is
a bad practice - it causes future maintenance headaches.
However, after speaking with my upstream, it sounds like it's
better to merge these patches in their current state, due to long
term considerations.
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/am43xx_support_v3.13/20131015213706/
Due to the lack of an AM43xx board and any available public
documentation, it's impossible for me to review or test that
platform in any meaningful way. But at least the tests above
verify that the patches don't affect existing platforms -
particularly AM33xx.
The display controller found on Tegra30 SoCs is backwards-compatible
with the one on Tegra20 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
We will use that in the later patch to find the kvm ops handler
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Move non-dt selection to ioremap_registers init which is only called not
non-dt board.
So we can support sam9n12/sam9x5/sama5d3 too.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Detect presence of second bank. So we do not need to have on function per SoC
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
As the cpuidle driver code has no more the dependency with the pm code, the
'standby' callback being passed as a parameter to the device's platform data,
we can move the cpuidle driver in the drivers/cpuidle directory.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Conflicts:
drivers/cpuidle/Kconfig.arm
drivers/cpuidle/Makefile
Using the platform driver model is a good way to separate the cpuidle specific
code from the low level pm code. It allows to remove the dependency between
these two components.
The platform_device is located in the pm code and a 'set' function has been
added to set the standby function from the AT91_SOC_START initialization
function. Each SoC with a cpuidle driver will set the standby function in the
platform_data field at init time. Then pm code will register the cpuidle
platform device.
The cpuidle driver will register the platform_driver and use the device's
platform_data as a standby callback in the idle path.
The at91_pm_enter function contains a { if then else } based on cpu_is_xx
similar to what was in cpuidle. This is considered dangerous when adding a new
SoC. Like the cpuidle driver, a standby ops is defined and assigned when the
SoC init function specifies what is its standby function and reused in the
at91_pm_enter's 'case' block.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Generic PHY drivers are used to handle the MIPI CSIS and MIPI DSIM
DPHYs so we can remove now unused code at arch/arm/plat-samsung.
In case there is any board file for S5PV210 platforms using MIPI
CSIS/DSIM (not any upstream currently) it should use the generic
PHY API to bind the PHYs to respective PHY consumer drivers and
a platform device for the PHY provider should be defined.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Since 883a106b08 (ARM: default
machine descriptor for multiplatform) we can remove the SoC-specific
callback init_machine() to use the default code.
This cleans up the code and reduces the number of lines.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This patch splits the sama5d3 SoCs definition:
- a common base for all sama5d3 SoCs (sama5d3.dtsi)
- several optional peripheral definitions which will be included by sama5d3
specific SoCs (sama5d3_'periph name'.dtsi)
- sama5d3 specific SoC definitions (sama5d3x.dtsi)
This provides a better representation of the real hardware (drop unneed
dt nodes) and avoids peripheral id conflict (which is not the case for
current sama5d3 SoCs, but could be if other SoCs of this family are
released).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
[nicolas.ferre@atmel.com: add more "sama5d3?" compatibility strings]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This patch splits the sam9x5 peripheral definitions into:
- a common base for all sam9x5 SoCs (at91sam9x5.dtsi)
- several optional peripheral definitions which will be included by specific
sam9x5 SoCs (at91sam9x5_'periph name'.dtsi)
This provides a better representation of the real hardware (drop unneeded
dt nodes) and avoids future peripheral id conflict (lcdc and isi both use
peripheral id 25).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Merge tag 'kvm-arm-for-3.13-1' of git://git.linaro.org/people/cdall/linux-kvm-arm into next
Updates for KVM/ARM including cpu=host and Cortex-A7 support
This augments the core machine code for the Integrator platforms
to get their references to the core module device nodes by
using compatible strings instead of predefined node names
and rename the CP syscon node to be simply "syscon".
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In the PCIv3 driver, use devm_ioremap() instead of just ioremap()
when remapping the system controller in the PCIv3 driver, so
the mapping will be automatically released on probe failure.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This moves the core module (CM) control base into the device
tree. It is a simple memory range of 0x200 bytes. Move the
cm header down into the machine directory and unexport the
cm_control() symbol as no modules are using it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Device Tree boot path now supports everything the ATAG
boot can provide, and the two are equivalent. This deletes
the ATAG boot path from the Integrator/AP and
Integrator/CP platforms to move them on to the future.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The static HW irqs have no meaning in the interrupt handler
and does not correlate to the /proc/interrupts IRQ numbers
anymore, print the Linux IRQ number instead.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The OF/DT boot path needs to get the LM (Logical Module)
IRQs from the device tree for coherency. This augments the
DT syscon node to contain these IRQs and alter the DT LM
code to get them from there.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This updates the integrator defconfig, apart from the usual
re-shuffling of symbols due to restructuring of the kernel Kconfig
this will also:
- Enable IM-PD1 so all hardware is enabled out-of-the-box
- Enable the LEDs class and heartbeat trigger, so that the
LED driver in plat-versatile/ is compiled.
- Enale some debug code like the CLK debug.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The CM_CTRL register was accessed directly from the LED driver,
which does not work now that we get the base for the register
from the device tree. Add an accessor function to do this and
make the LED driver compile again.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The GPIO API defines 0 as being a valid GPIO number, so this field needs
to be initialized explicitly.
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The GPIO API defines 0 as being a valid GPIO number, so this field needs
to be initialized explicitly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The GPIO API defines 0 as being a valid GPIO number, so this field needs
to be initialized explicitly.
A special case is the Palm Tungsten|C board. Since it doesn't use any
quirks that would require the existing .init() or .exit() hooks it can
simply use the new enable_gpio field.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The GPIO API defines 0 as being a valid GPIO number, so this field needs
to be initialized explicitly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
One bug fix and three reverts. The reverts back out the slightly
controversial feeding the entire device tree into the random pool and
the reserved-memory binding which isn't fully baked yet. Expect the
reserved-memory patches at least to resurface for v3.13. The bug fixes
removes a scary but harmless warning on SPARC that was introduced in the
v3.12 merge window. v3.13 will contain a proper fix that makes the new
code work on SPARC.
On the plus side, the diffstat looks *awesome*. I love removing lines of code.
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Merge tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux
Pull device tree fixes and reverts from Grant Likely:
"One bug fix and three reverts. The reverts back out the slightly
controversial feeding the entire device tree into the random pool and
the reserved-memory binding which isn't fully baked yet. Expect the
reserved-memory patches at least to resurface for v3.13.
The bug fixes removes a scary but harmless warning on SPARC that was
introduced in the v3.12 merge window. v3.13 will contain a proper fix
that makes the new code work on SPARC.
On the plus side, the diffstat looks *awesome*. I love removing lines
of code"
* tag 'devicetree-for-linus' of git://git.secretlab.ca/git/linux:
Revert "drivers: of: add initialization code for dma reserved memory"
Revert "ARM: init: add support for reserved memory defined by device tree"
Revert "of: Feed entire flattened device tree into the random pool"
of: fix unnecessary warning on missing /cpus node
Pull DMA-mapping fix from Marek Szyprowski:
"A bugfix for the IOMMU-based implementation of dma-mapping subsystem
for ARM architecture"
* 'fixes-for-v3.12' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping:
ARM: dma-mapping: Always pass proper prot flags to iommu_map()
CONFIG_CPU_FREQ_TABLE will be always enabled when cpufreq framework is used, as
cpufreq core depends on it. So, we don't need this CONFIG option anymore as it
is not configurable. Remove CONFIG_CPU_FREQ_TABLE and update its users.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Most of the CPUFreq drivers do similar things in .exit() and .verify() routines
and .attr. So its better if we have generic routines for them which can be used
by cpufreq drivers then.
This patch uses these generic routines in the sa11x0 driver.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Revision 0 of Exynos4210 SoC (used on Universal C210 board) requires
'secure' PL330 MDMA1 address (0x12840000) instead of 'non-secure' one
(0x12850000). Fix it by overriding the default PL330 MDMA1 address in
exynos4210-universal_c210.dts.
This is a Device Tree (DT) version of commit 91280e7 ("ARM: EXYNOS:
PL330 MDMA1 fix for revision 0 of Exynos4210 SOC") and fixes recent
regression caused by conversion to DT-only setup on ARM EXYNOS.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos cpufreq drivers does not support device tree based regulator
lookup, so it can get the VDD ARM regulator only by its name. To get
cpufreq working for now, this patch works this around by renaming the
regulator in board dts files to vdd_arm, which is the name expected by
the driver.
This fixes a regression introduced by dropping support of board file
based bootup of Exynos 4210 boards that rendered cpufreq inoperable on
Trats and Origen boards.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch removes '_' from "early_prink" on Exynos5440 dts
files in according to kernel-parameters document.
Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com>
Reviewed-by: Sachin Kamat <sachin.kamat@linaro.org>
Tested-by: Jungseok Lee <jays.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Corrects an obvious typo in the Arndale pinctrl descriptions in DT.
The samsung-pinctrl driver uses the correct name.
Signed-off-by: Al Stone <al.stone@linaro.org>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The Tegra124 GPIO controller is identical to Tegra30, so copy the
DT node from tegra30.dtsi to tegra124.dtsi.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
This reverts commit 10bcdfb8ba. There is
no consensus on the bindings for the reserved memory, so the code for
handing it will be reverted.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Grant Likely <grant.likely@linaro.org>
n900 secure mode changes. Note that the n900 secure mode changes
will still be needed for device tree based booting also.
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Merge tag 'omap-for-v3.13/board-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/boards
From Tony Lindgren:
Platform data changes for omaps for the display subsystem and
n900 secure mode changes. Note that the n900 secure mode changes
will still be needed for device tree based booting also.
* tag 'omap-for-v3.13/board-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (508 commits)
ARM: OMAP2+: display: Create omap_vout device inside omap_display_init
ARM: OMAP2+: display: Create omapvrfb and omapfb devices inside omap_display_init
ARM: OMAP2+: display: Create omapdrm device inside omap_display_init
ARM: OMAP2+: drm: Don't build device for DMM
RX-51: Add support for OMAP3 ROM Random Number Generator
ARM: OMAP3: RX-51: ARM errata 430973 workaround
ARM: OMAP3: Add secure function omap_smc3() which calling instruction smc #1
+Linux 3.12-rc4
Signed-off-by: Kevin Hilman <khilman@linaro.org>
counter on newer omaps, and to fail early for omap5 es1.0
SoCs that don't have any support merged for them in the
mainline tree.
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Merge tag 'omap-for-v3.13/soc-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
SoC related changes for omaps to support the realtime
counter on newer omaps, and to fail early for omap5 es1.0
SoCs that don't have any support merged for them in the
mainline tree.
* tag 'omap-for-v3.13/soc-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Fix build error for realtime counter init if not enabled
ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register
ARM: OMAP5: id: Remove ES1.0 support
ARM: OMAP2+: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Some OMAP hwmod changes for 3.13. Significant changes here include:
- support for moving some of the hwmod flags to DT data
- support for the SSI, hardware spinlock, USB host/TLL, and RNG IP
blocks for various OMAPs
- a fix that again decouples hwmod data changes from unrelated DT data
patchsets
Basic test logs are available at:
http://www.pwsan.com/omap/testlogs/prcm_fixes_v3.13/20131009094936/
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Merge tag 'omap-for-v3.13/hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
omap hwmod related changes via Paul Walmsley <paul@pwsan.com>:
Some OMAP hwmod changes for 3.13. Significant changes here include:
- support for moving some of the hwmod flags to DT data
- support for the SSI, hardware spinlock, USB host/TLL, and RNG IP
blocks for various OMAPs
- a fix that again decouples hwmod data changes from unrelated DT data
patchsets
Basic test logs are available at:
http://www.pwsan.com/omap/testlogs/prcm_fixes_v3.13/20131009094936/
* tag 'omap-for-v3.13/hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP5: hwmod: add missing ocp2scp hwmod data
ARM: AM33xx: hwmod: Add RNG module data
ARM: OMAP2+: hwmod: Extract no-idle and no-reset info from DT
ARM: OMAP2+: hwmod: cleanup HWMOD_INIT_NO_RESET usage
ARM: AM33xx: hwmod_data: add the sysc configuration for spinlock
ARM: OMAP5: hwmod data: Add spinlock data
ARM: OMAP5: hwmod data: Add USB Host and TLL modules
ARM: OMAP2+: hwmod data: Add SSI information
ARM: OMAP2+: hwmod: check for module address space during init
Add the minimal DTS support for DRA7xx based SoC core.
Add the initial support for N900 and gta04 phones.
Enable USB3 on OMAP5 evm board.
Add support for cryto accelerators
Add new IGEP AQUILA board
Add AM33XX EDMA support
Update HSUSB node to use the reset-gpios fmwk
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Merge tag 'omap-for-v3.13/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren:
omap device tree related changes via Benoit Cousson <bcousson@baylibre.com>:
Add the minimal DTS support for DRA7xx based SoC core.
Add the initial support for N900 and gta04 phones.
Enable USB3 on OMAP5 evm board.
Add support for cryto accelerators
Add new IGEP AQUILA board
Add AM33XX EDMA support
Update HSUSB node to use the reset-gpios fmwk
* tag 'omap-for-v3.13/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (58 commits)
ARM: dts: dra7-evm: Add mmc2 node for eMMC support
ARM: dts: dra7-evm: Add mmc1 node for micro-sd support
ARM: dts: omap5-uevm: mark TWL6037 as system-power-controller
ARM: dts: omap3-igep0020: use standard constant for IRQ flags
ARM: dts: omap3-igep0020: Add HS USB Host support
ARM: dts: omap3-igep: Add USB OTG support
ARM: dts: AM33XX beagle black: add pinmux and hdmi node to enable display
ARM: dts: AM33XX: Add LCDC info into am335x-evm
ARM: dts: AM437X: Add DES node
ARM: dts: AM437X: Add AES node
ARM: dts: AM33XX: Fix AES interrupt number
ARM: dts: AM33XX: Add AES data and documentation
ARM: dts: AM33XX: Add SHAM data and documentation
ARM: dts: OMAP4: Add DES3DES node
ARM: dts: OMAP4: Add AES node
ARM: dts: am335x-evm[sdk]: switch mmc1 to 4-bit mode
ARM: dts: am335x-bone-common: correct mux mode for cmd line
ARM: dts: AM33XX: Add support for IGEP AQUILA EXPANSION board.
ARM: dts: AM33XX: Add support for IGEP COM AQUILA
ARM: dts: am335x-boneblack: move fixed regulator to board level
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- Always build in board-generic, and add pdata quirks and auxdata
support for it so we have all the pdata related quirks
in the same place.
- Merge of the drivers/pinctrl changes that are needed for PM
to continue working on omap3 and also needed for other omaps
eventually. The three pinctrl related patches have been acked
by Linus Walleij and are pulled into both the pinctrl tree
and this branch.
- Few defconfig related changes for drivers needed.
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Merge tag 'omap-for-v3.13/quirk-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
From Tony Lindgren:
Changes needed to prepare for making omap3 device tree only:
- Always build in board-generic, and add pdata quirks and auxdata
support for it so we have all the pdata related quirks
in the same place.
- Merge of the drivers/pinctrl changes that are needed for PM
to continue working on omap3 and also needed for other omaps
eventually. The three pinctrl related patches have been acked
by Linus Walleij and are pulled into both the pinctrl tree
and this branch.
- Few defconfig related changes for drivers needed.
* tag 'omap-for-v3.13/quirk-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (523 commits)
ARM: configs: omap2plus_defconfig: enable dwc3 and dependencies
ARM: OMAP2+: Add WLAN modules and of_serial to omap2plus_defconfig
ARM: OMAP2+: Run make savedefconfig on omap2plus_defconfig to shrink it
ARM: OMAP2+: Add minimal 8250 support for GPMC
ARM: OMAP2+: Use pdata quirks for wl12xx for omap3 evm and zoom3
ARM: OMAP: Move DT wake-up event handling over to use pinctrl-single-omap
ARM: OMAP2+: Add support for auxdata
pinctrl: single: Add support for auxdata
pinctrl: single: Add support for wake-up interrupts
pinctrl: single: Prepare for supporting SoC specific features
ARM: OMAP2+: igep0020: use display init from dss-common
ARM: OMAP2+: pdata-quirks: add legacy display init for IGEPv2 board
+Linux 3.12-rc4
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Olof Johansson