In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
WARN_ON causes a backtrace to get logged which is only useful for
kernel bugs. For signalling a firmware bug dev_warn(dev, FW_BUG "...")
should be used.
This fixes users running userspace software to monitor kernel oopses
getting a false positive bug-report every boot because of the wrong
use of WARN_ON.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- Switch the generic pin config argument from 16 to 24 bits,
only use 8 bits for the configuration type. We might need to
encode more information about a certain setting than we need
to encode different generic settings.
- Add a cross-talk API to the pin control GPIO back-end,
utilizing pinctrl_gpio_set_config() from GPIO drivers that
want to set up a certain pin configuration in the back-end.
This also includes the .set_config() refactoring of the
GPIO chips, so that they pass a generic configuration for
things like debouncing and single ended (typically open
drain). This change has also been merged in an immutable
branch to the GPIO tree.
- Take hogs with a delayed work, so that we finalize probing
a pin controller before trying to get any hogs.
- For pin controllers putting all group and function definitions
into the device tree, we now have generic code to deal with
this and it is used in two drivers so far.
- Simplifications of the pin request conflict check.
- Make dt_free_map() optional.
Updates to drivers:
- pinctrl-single now use the generic helpers to generate dynamic
group and function tables from the device tree.
- Texas Instruments IOdelay configuration driver add-on to
pinctrl-single.
- i.MX: use radix trees to store groups and functions, use the new
generic group and function helpers to manage them.
- Intel: add support for hardware debouncing and 1K pull-down.
New subdriver for the Gemini Lake SoC.
- Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.
- Aspeed: use syscon cross-dependencies to set up related bits in
the LPC host controller and display controller.
- Aspeed: finalize G4 and G5 support. Fix mux configuration on
GPIOs. Add banks Y, Z, AA, AB and AC.
- AMD: support additional GPIO.
- STM32: set this controller to strict muxing mode.
STM32H743 MCU support.
- Allwinner sunxi: deep simplifications on how to support
subvariants of SoCs without adding to much SoC-specific data
for each subvariant, especially for sun5i variants. New driver
for V3s SoCs. New driver for the H5 SoC. Support A31/A31s
variants with the new variant framework.
- Mvebu: simplifications to use a MMIO and regmap abstraction.
New subdrivers for the 98DX3236, 98DX5241 SoCs.
- Samsung Exynos: delete Exynos4415 support. Add crosstalk to the
SoC driver to access regmaps. Add infrastructure for pin-bank
retention control. Clean out the pin retention control from
arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly
in the Samsung pin control driver(s).
- Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.
- Qualcomm: use raw spinlock variants: this makes the qualcomm
driver realtime-safe.
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Merge tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Pin control bulk changes for the v4.11 kernel cycle.
Core changes:
- Switch the generic pin config argument from 16 to 24 bits, only use
8 bits for the configuration type. We might need to encode more
information about a certain setting than we need to encode
different generic settings.
- Add a cross-talk API to the pin control GPIO back-end, utilizing
pinctrl_gpio_set_config() from GPIO drivers that want to set up a
certain pin configuration in the back-end.
This also includes the .set_config() refactoring of the GPIO chips,
so that they pass a generic configuration for things like
debouncing and single ended (typically open drain). This change has
also been merged in an immutable branch to the GPIO tree.
- Take hogs with a delayed work, so that we finalize probing a pin
controller before trying to get any hogs.
- For pin controllers putting all group and function definitions into
the device tree, we now have generic code to deal with this and it
is used in two drivers so far.
- Simplifications of the pin request conflict check.
- Make dt_free_map() optional.
Updates to drivers:
- pinctrl-single now use the generic helpers to generate dynamic
group and function tables from the device tree.
- Texas Instruments IOdelay configuration driver add-on to
pinctrl-single.
- i.MX: use radix trees to store groups and functions, use the new
generic group and function helpers to manage them.
- Intel: add support for hardware debouncing and 1K pull-down. New
subdriver for the Gemini Lake SoC.
- Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.
- Aspeed: use syscon cross-dependencies to set up related bits in the
LPC host controller and display controller.
- Aspeed: finalize G4 and G5 support. Fix mux configuration on GPIOs.
Add banks Y, Z, AA, AB and AC.
- AMD: support additional GPIO.
- STM32: set this controller to strict muxing mode. STM32H743 MCU
support.
- Allwinner sunxi: deep simplifications on how to support subvariants
of SoCs without adding to much SoC-specific data for each
subvariant, especially for sun5i variants. New driver for V3s SoCs.
New driver for the H5 SoC. Support A31/A31s variants with the new
variant framework.
- Mvebu: simplifications to use a MMIO and regmap abstraction. New
subdrivers for the 98DX3236, 98DX5241 SoCs.
- Samsung Exynos: delete Exynos4415 support. Add crosstalk to the SoC
driver to access regmaps. Add infrastructure for pin-bank retention
control. Clean out the pin retention control from
arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly in
the Samsung pin control driver(s).
- Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.
- Qualcomm: use raw spinlock variants: this makes the qualcomm driver
realtime-safe"
* tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (111 commits)
pinctrl: samsung: Fix return value check in samsung_pinctrl_get_soc_data()
pinctrl: intel: unlock on error in intel_config_set_pull()
pinctrl: berlin: make bool drivers explicitly non-modular
pinctrl: spear: make bool drivers explicitly non-modular
pinctrl: mvebu: make bool drivers explicitly non-modular
pinctrl: sunxi: make sun5i explicitly non-modular
pinctrl: sunxi: Remove stray printk call in sun5i driver's probe function
pinctrl: samsung: mark PM functions as __maybe_unused
pinctrl: sunxi: Remove redundant A31s pinctrl driver
pinctrl: sunxi: Support A31/A31s with pinctrl variants
pinctrl: Amend bindings for STM32 pinctrl
pinctrl: Add STM32 pinctrl driver DT bindings
pinctrl: stm32: Add STM32H743 MCU support
include: dt-bindings: Add STM32H7 pinctrl DT defines
gpio: aspeed: Remove dependence on GPIOF_* macros
pinctrl: stm32: fix bad location of gpiochip_lock_as_irq
drivers: pinctrl: add driver for Allwinner H5 SoC
pinctrl: intel: Add Intel Gemini Lake pin controller support
pinctrl: intel: Add support for 1k additional pull-down
pinctrl: intel: Add support for hardware debouncer
...
According to VLI64 Intel Atom E3800 Specification Update (#329901)
concurrent read accesses may result in returning 0xffffffff and write
accesses may be dropped silently.
To workaround all accesses must be protected by locks.
Cc: stable@vger.kernel.org
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Debounce value is set globally per community. Otherwise user will easily
get a kernel crash when they start using the feature:
BUG: unable to handle kernel paging request at ffffc900003be000
IP: byt_gpio_dbg_show+0xa9/0x430
Make it clear in byt_gpio_reg().
Note that this fix just prevents kernel to crash, but doesn't make any
difference to the existing logic. It means the last caller will win the
trade and debounce value will be configured accordingly. The actual
logic fix needs to be thought about and it's not as important as crash
fix. That's why the latter goes separately and right now.
Fixes: 658b476c74 ("pinctrl: baytrail: Add debounce configuration")
Cc: Cristina Ciocan <cristina.ciocan@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The commit 04ff5a095d ("pinctrl: baytrail: Rectify debounce support")
almost fixes the logic of debuonce but missed couple of things, i.e.
typo in mask when disabling debounce and lack of enabling it back.
This patch addresses above issues.
Reported-by: Jean Delvare <jdelvare@suse.de>
Fixes: 04ff5a095d ("pinctrl: baytrail: Rectify debounce support")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Apparently each GPIO pad's register are 16 bytes, so multiply the pad_map
by that. The same is done in byt_gpio_reg the only other place where
pad_map is used.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When DIRECT_IRQ_EN is set, the pin is routed directly to the IO-APIC bypassing
the GPIO driver completely. However, the mask register is still used to
determine if the pin is supposed to generate IRQ or not.
So with commit 3ae02c14d9 the IRQ core masks all IRQs (because of
handle_bad_irq()) the pin connected to the touchscreen gets masked as well and
hence no interrupts.
To make this all work as expected we do not add those GPIOs to the IRQ domain
that can actually propagate interrupts.
Fixes: 3ae02c14d9 ("pinctrl: intel: set default handler to be handle_bad_irq()")
Reported-by: Robert R. Howell <rhowell@uwyo.edu>
Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This simplifies error handling and allows us to drop error path handlers
completely.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The commit 658b476c74 ("pinctrl: baytrail: Add debounce configuration")
implements debounce for Baytrail pin control, but seems wasn't tested properly.
The register which keeps debounce value is separated from the configuration
one. Writing wrong values to the latter will guarantee wrong behaviour of the
driver and even might break something physically.
Besides above there is missed case how to disable it, which is actually done
through the bit in configuration register.
Rectify implementation here by using proper register for debounce value.
Fixes: 658b476c74 ("pinctrl: baytrail: Add debounce configuration")
Cc: Cristina Ciocan <cristina.ciocan@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We switch the default handler to be handle_bad_irq() instead of
handle_simple_irq() (which was not correct anyway).
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Initialize the spinlock before using it.
INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.8.0-dwc-bisect #4
Hardware name: Intel Corp. VALLEYVIEW C0 PLATFORM/BYT-T FFD8, BIOS BLAKFF81.X64.0088.R10.1403240443 FFD8_X64_R_2014_13_1_00 03/24/2014
0000000000000000 ffff8800788ff770 ffffffff8133d597 0000000000000000
0000000000000000 ffff8800788ff7e0 ffffffff810cfb9e 0000000000000002
ffff8800788ff7d0 ffffffff8205b600 0000000000000002 ffff8800788ff7f0
Call Trace:
[<ffffffff8133d597>] dump_stack+0x67/0x90
[<ffffffff810cfb9e>] register_lock_class+0x52e/0x540
[<ffffffff810d2081>] __lock_acquire+0x81/0x16b0
[<ffffffff810cede1>] ? save_trace+0x41/0xd0
[<ffffffff810d33b2>] ? __lock_acquire+0x13b2/0x16b0
[<ffffffff810cf05a>] ? __lock_is_held+0x4a/0x70
[<ffffffff810d3b1a>] lock_acquire+0xba/0x220
[<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
[<ffffffff81631567>] _raw_spin_lock_irqsave+0x47/0x60
[<ffffffff8136f1fe>] ? byt_gpio_get_direction+0x3e/0x80
[<ffffffff8136f1fe>] byt_gpio_get_direction+0x3e/0x80
[<ffffffff813740a9>] gpiochip_add_data+0x319/0x7d0
[<ffffffff81631723>] ? _raw_spin_unlock_irqrestore+0x43/0x70
[<ffffffff8136fe3b>] byt_pinctrl_probe+0x2fb/0x620
[<ffffffff8142fb0c>] platform_drv_probe+0x3c/0xa0
...
Based on the diff it looks like the problem was introduced in
commit 71e6ca61e8 ("pinctrl: baytrail: Register pin control handling")
but I wasn't able to verify that empirically as the parent commit
just oopsed when I tried to boot it.
Cc: Cristina Ciocan <cristina.ciocan@intel.com>
Cc: stable@vger.kernel.org
Fixes: 71e6ca61e8 ("pinctrl: baytrail: Register pin control handling")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
New drivers:
- New driver for Oxnas pin control and GPIO. This ARM-based chipset
is used in a few storage (NAS) type devices.
- New driver for the MAX77620/MAX20024 pin controller portions.
- New driver for the Intel Merrifield pin controller.
New subdrivers:
- New subdriver for the Qualcomm MDM9615
- New subdriver for the STM32F746 MCU
- New subdriver for the Broadcom NSP SoC.
Cleanups:
- Demodularization of bool compiled-in drivers.
Apart from this there is just regular incremental improvements to
a lot of drivers, especially Uniphier and PFC.
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Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.8 kernel cycle.
Nothing stands out as especially exiting: new drivers, new subdrivers,
lots of cleanups and incremental features.
Business as usual.
New drivers:
- New driver for Oxnas pin control and GPIO. This ARM-based chipset
is used in a few storage (NAS) type devices.
- New driver for the MAX77620/MAX20024 pin controller portions.
- New driver for the Intel Merrifield pin controller.
New subdrivers:
- New subdriver for the Qualcomm MDM9615
- New subdriver for the STM32F746 MCU
- New subdriver for the Broadcom NSP SoC.
Cleanups:
- Demodularization of bool compiled-in drivers.
Apart from this there is just regular incremental improvements to a
lot of drivers, especially Uniphier and PFC"
* tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
pinctrl: fix pincontrol definition for marvell
pinctrl: xway: fix typo
Revert "pinctrl: amd: make it explicitly non-modular"
pinctrl: iproc: Add NSP and Stingray GPIO support
pinctrl: Update iProc GPIO DT bindings
pinctrl: bcm: add OF dependencies
pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
pinctrl: Add STM32F746 MCU support
pinctrl: intel: Protect set wake flow by spin lock
pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
pinctrl: uniphier: add Ethernet pin-mux settings
sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
pinctrl: ns2: fix return value check in ns2_pinmux_probe()
pinctrl: qcom: update DT bindings with ebi2 groups
pinctrl: qcom: establish proper EBI2 pin groups
pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
includes: dt-bindings: Add STM32F746 pinctrl DT bindings
pinctrl: sunxi: fix nand0 function name for sun8i
pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
...
Fix plt clock 3, 4 and 5 pins, which were not in the proper order.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Kconfig currently controlling compilation of this code is:
config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
...meaning that it currently is not being built as a module by anyone.
Lets remove the modular code that is essentially orphaned, so that
when reading the driver there is no doubt it is builtin-only.
We explicitly disallow a driver unbind, since that doesn't have a
sensible use case anyway, and it allows us to drop the ".remove"
code for non-modular drivers.
Since module_init() was already not in use in this driver, we don't
have any concerns with init ordering changes here.
Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.
We also delete the MODULE_LICENSE tag etc. since all that information
is already contained at the top of the file in the comments.
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
gcc-4.4 and thereabouts has issues with initializers of anonymous
unions, and it generates the following warnings:
drivers/pinctrl/intel/pinctrl-baytrail.c:413: error: unknown field 'simple_funcs' specified in initializer
drivers/pinctrl/intel/pinctrl-baytrail.c:413: warning: missing braces around initializer
drivers/pinctrl/intel/pinctrl-baytrail.c:413: warning: (near initialization for 'byt_score_groups[0].<anonymous>')
drivers/pinctrl/intel/pinctrl-baytrail.c:415: error: unknown field 'simple_funcs' specified in initializer
drivers/pinctrl/intel/pinctrl-baytrail.c:417: error: unknown field 'simple_funcs' specified in initializer
...
Work around this.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
We need to unlock before continuing. Also the continue was accidentally
left out on one error path which would lead to a NULL dereference.
Fixes: 86e3ef812f ('pinctrl: baytrail: Update gpio chip operations')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make debounce setting and getting functionality available when
configurating a certain pin.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch updates device's probing, removal and irq handling in order to
register it as pinctrl device. Pin control data is matched by ACPI UID,
since it is passed along as driver data in acpi_device_id structure.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch updates the irq chip implementation in order
to interact with the pin control chip model: the chip
contains reference to SOC data and pin/group/community
information is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch updates the gpio chip implementation in order
to interact with the pin control model: the chip contains
reference to SOC data and pin/group/community information
is retrieved through the SOC reference.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
- function information (count, name and groups)
- mux setting
- gpio control (enable, disable, set direction)
- pin configuration:
- pull disable
- pull up/down and pull strength
- debounce
- any other option is treated as not supported.
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In order to implement pin control for Baytrail, we need data
structures in which to store and pass along pin, group, function,
community and SOC data information.
Baytrail has 3 GPIO controllers. Add SCORE, NCORE and SUS
controller data:
- pins (for all controllers),
- pad map for pins (for all controllers; we need this since pads
are not ordered),
- groups (for SCORE and SUS controllers),
- functions (for SCORE and SUS controllers),
- communities (for all controllers),
- soc specific data gathering all of the above and the ACPI UID
(for all controllers)
This information is useful for pin control functionality.
NCORE data is lighter than the other two controllers' due to
lack of pin documentation in the public datasheet.
Datasheet:
http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html
Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As we want gpio_chip .get() calls to be able to return negative
error codes and propagate to drivers, we need to go over all
drivers and make sure their return values are clamped to [0,1].
We do this by using the ret = !!(val) design pattern.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The name .dev in a struct is normally reserved for a struct device
that is let us say a superclass to the thing described by the struct.
struct gpio_chip stands out by confusingly using a struct device *dev
to point to the parent device (such as a platform_device) that
represents the hardware. As we want to give gpio_chip:s real devices,
this is not working. We need to rename this member to parent.
This was done by two coccinelle scripts, I guess it is possible to
combine them into one, but I don't know such stuff. They look like
this:
@@
struct gpio_chip *var;
@@
-var->dev
+var->parent
and:
@@
struct gpio_chip var;
@@
-var.dev
+var.parent
and:
@@
struct bgpio_chip *var;
@@
-var->gc.dev
+var->gc.parent
Plus a few instances of bgpio that I couldn't figure out how
to teach Coccinelle to rewrite.
This patch hits all over the place, but I *strongly* prefer this
solution to any piecemal approaches that just exercise patch
mechanics all over the place. It mainly hits drivers/gpio and
drivers/pinctrl which is my own backyard anyway.
Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Alek Du <alek.du@intel.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Jiri Kosina <jkosina@suse.cz>
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When CONFIG_PM is not set we get following compilation warnings:
warning: ‘byt_gpio_runtime_suspend’ defined but not used [-Wunused-function]
warning: ‘byt_gpio_runtime_resume’ defined but not used [-Wunused-function]
Fix this by guarding byt_gpio_runtime_suspend()/byt_gpio_runtime_resume()
with #ifdef CONFIG_PM.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.
Remove the argument.
Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
The Intel Baytrail pinctrl driver implements irqchip callbacks which are
called with desc->lock raw_spinlock held. In mainline this is fine because
spinlock resolves to raw_spinlock. However, running the same code in -rt we
get:
BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
Preemption disabled at:[<ffffffff81092e9f>] cpu_startup_entry+0x17f/0x480
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #13
...
Call Trace:
<IRQ> [<ffffffff816283c6>] dump_stack+0x4a/0x61
[<ffffffff81077e17>] ___might_sleep+0xe7/0x170
[<ffffffff8162d6cf>] rt_spin_lock+0x1f/0x50
[<ffffffff812e3b88>] byt_gpio_clear_triggering+0x38/0x60
[<ffffffff812e3bc1>] byt_irq_mask+0x11/0x20
[<ffffffff810a7013>] handle_level_irq+0x83/0x150
[<ffffffff810a3457>] generic_handle_irq+0x27/0x40
[<ffffffff812e3a5f>] byt_gpio_irq_handler+0x7f/0xc0
[<ffffffff810050aa>] handle_irq+0xaa/0x190
...
This is because in -rt spinlocks are preemptible so taking the driver
private spinlock in irqchip callbacks causes might_sleep() to trigger.
In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.
Also shorten the critical section a bit in few places.
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is a hardware issue in Intel Baytrail where concurrent GPIO register
access might result reads of 0xffffffff and writes might get dropped
completely.
Prevent this from happening by taking the serializing lock in all places
where it is possible that more than one thread might be accessing the
hardware concurrently.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The FSF address is already mentioned in the COPYING file. No need to
duplicate that information to individual files.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use irq_set_handler_locked() as it avoids a redundant lookup of the
irq descriptor.
Search and replacement was done with coccinelle.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
Cc: Julia Lawall <julia.lawall@lip6.fr>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
The BIOS might reconfigure pins as it needs when S3 is entered. This might
cause drivers using the GPIOs to fail because the state was wrong or
interrupts stopped working.
Fix this by saving and restoring enough pin context over system sleep.
Reported-by: Hans Holmberg <hans.holmberg@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Instead of handling everything in the driver's first level interrupt
handler, we can take advantage of already existing flow handlers that are
provided by the IRQ core.
This changes the functionality a bit also. Previously the driver looped
over pending interrupts in a single loop, restarting the loop if some
interrupt changed state. This caused problem with Lenovo Thinkpad 10
digitizer that it was not able to deassert the interrupt before the driver
disabled the interrupt for good (looplimit was exhausted).
Rework the interrupt handling logic a bit so that we provide proper mask,
ack and unmask operations in terms of Baytrail GPIO hardware and loop over
pending interrupts only once. If the interrupt remains asserted the first
level handler will be re-triggered automatically.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If the pin is already configured as GPIO and it has any of the triggering
flags set, we may get spurious interrupts depending on the state of the
pin.
Prevent this by clearing the triggering flags on such pins. However, if the
pin is also configured as "direct IRQ" we leave the flags as is. Otherwise
it will prevent interrupts that are routed directly to IO-APIC.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Zotac ZBOX PI320, a Baytrail based mini-PC, has power button connected to a
GPIO pin and it is exposed to the operating system as Windows 8 button
array. This is implemented in Linux as a driver using gpio_keys.
However, BIOS on this particula machine forgot to mux the pin to be a GPIO
instead of native function, which results following message to be seen on
the console:
byt_gpio INT33FC:02: pin 16 cannot be used as GPIO.
This causes power button to not work as the driver was not able to request
the GPIO it needs.
So instead of completely preventing this we allow turning the pin as GPIO
but issue warning that something might be wrong.
Reported-by: Benjamin Adler <benadler@gmx.net>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Here's the set of driver core patches for 3.19-rc1.
They are dominated by the removal of the .owner field in platform
drivers. They touch a lot of files, but they are "simple" changes, just
removing a line in a structure.
Other than that, a few minor driver core and debugfs changes. There are
some ath9k patches coming in through this tree that have been acked by
the wireless maintainers as they relied on the debugfs changes.
Everything has been in linux-next for a while.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core
Pull driver core update from Greg KH:
"Here's the set of driver core patches for 3.19-rc1.
They are dominated by the removal of the .owner field in platform
drivers. They touch a lot of files, but they are "simple" changes,
just removing a line in a structure.
Other than that, a few minor driver core and debugfs changes. There
are some ath9k patches coming in through this tree that have been
acked by the wireless maintainers as they relied on the debugfs
changes.
Everything has been in linux-next for a while"
* tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits)
Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries"
fs: debugfs: add forward declaration for struct device type
firmware class: Deletion of an unnecessary check before the function call "vunmap"
firmware loader: fix hung task warning dump
devcoredump: provide a one-way disable function
device: Add dev_<level>_once variants
ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries
ath: use seq_file api for ath9k debugfs files
debugfs: add helper function to create device related seq_file
drivers/base: cacheinfo: remove noisy error boot message
Revert "core: platform: add warning if driver has no owner"
drivers: base: support cpu cache information interface to userspace via sysfs
drivers: base: add cpu_device_create to support per-cpu devices
topology: replace custom attribute macros with standard DEVICE_ATTR*
cpumask: factor out show_cpumap into separate helper function
driver core: Fix unbalanced device reference in drivers_probe
driver core: fix race with userland in device_add()
sysfs/kernfs: make read requests on pre-alloc files use the buffer.
sysfs/kernfs: allow attributes to request write buffer be pre-allocated.
fs: sysfs: return EGBIG on write if offset is larger than file size
...
- Force conversion of the ux500 pin control device trees
and parsers to use the generic pin control bindings.
- New driver and device tree bindings for the Qualcomm
PMIC MPP pin controller and GPIO.
- Some ACPI infrastructure for pin controllers.
- New driver for the Intel CherryView/Braswell pin controller,
the first Intel pin controller to fully take advantage of
the pin control subsystem.
- Support the Freescale i.MX VF610 variant.
- Support the sunxi A80 variant.
- Support the Samsung Exynos 4415 and Exynos 7 variants.
- Split out Intel pin controllers to their own subdirectory.
- A large slew of rockchip pin control updates, including
suspend/resume support.
- A large slew of Samsung Exynos pin controller updates.
- Various minor updates and fixes.
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Merge tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij:
"Here is a stash of pin control changes I have collected for the v3.19
series. Mainly new hardware support, with Intels new embedded SoC as
the especially interesting thing standing out, fully using the
subsystem.
- Force conversion of the ux500 pin control device trees and parsers
to use the generic pin control bindings.
- New driver and device tree bindings for the Qualcomm PMIC MPP pin
controller and GPIO.
- Some ACPI infrastructure for pin controllers.
- New driver for the Intel CherryView/Braswell pin controller, the
first Intel pin controller to fully take advantage of the pin
control subsystem.
- Support the Freescale i.MX VF610 variant.
- Support the sunxi A80 variant.
- Support the Samsung Exynos 4415 and Exynos 7 variants.
- Split out Intel pin controllers to their own subdirectory.
- A large slew of rockchip pin control updates, including
suspend/resume support.
- A large slew of Samsung Exynos pin controller updates.
- Various minor updates and fixes"
* tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (49 commits)
pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show
pinctrl: meson: add device tree bindings documentation
gpio: tz1090: Fix error handling of irq_of_parse_and_map
pinctrl: tz1090-pinctrl.txt: Fix typo in binding
pinctrl: pinconf-generic: Declare dt_params/conf_items const
pinctrl: exynos: Add support for Exynos4415
pinctrl: exynos: Add initial driver data for Exynos7
pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
pinctrl: exynos: Consolidate irq domain callbacks
pinctrl: exynos: Generalize the eint16_31 demux code
pinctrl: samsung: Separate per-bank init and runtime data
pinctrl: samsung: Constify samsung_pin_ctrl struct
pinctrl: samsung: Constify samsung_pin_bank_type struct
pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct
pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
pinctrl: Add Intel Cherryview/Braswell pin controller support
gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod()
pinctrl: Fix path error in documentation
pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
pinctrl: rockchip: add suspend/resume functions
...
We are going to have more pinctrl drivers for Intel hardware so separate
all our pin controller drivers to own directory.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Thierry Reding