The SM_SCLK_SM_SCLK is define is cut and pasted twice. I have removed
the second define.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Drive strength for PXA910 is a 2 bit value but because of the mapping in
plat-pxa/mfp.h needs to be shifted up one bit to handle real
location in mfp registers. (MMP2 and PXA910 drive strength start
at bit 11 while PXA168 starts at bit 10).
Values 0, 1, 2, and 3 effectively need to be
0, 2, 4, and 6 to fit into register. 8 does not work.
Signed-off-by: Philip Rakity <prakity@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Dan Carpenter