Old pinctrl drivers will need to disable strict mode for various reasons,
among which:
- Some DT will still have a pinctrl group for each GPIO used, which will
be rejected by pin_request. While we could remove those nodes, we still
have to deal with old DTs.
- Some GPIOs on these boards need to have their pin configuration changed
(for bias or current), and there's no clear migration path
Let's disable the strict mode on those SoCs so that there's no breakage.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
H3 has single PWM channel. The second PWM channel is not supported,
so the pinctrl function should be removed.
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In sun4/5/6/7i, all the pin function related to NAND0 controller is
named "nand0". However, in sun8i, some of the functions are named as
"nand". This patch renamed them to "nand0", for the consistency.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It seems that on H3, just like on A10, when GPIOs are configured as
external interrupt data registers does not contain their value. When
value is read, GPIO function must be temporary switched to input for
reads.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The H3 uses the same pin controller as previous SoC's from Allwinner.
Add support for the pins controlled by the main PIO controller.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime Ripard