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3 Commits

Author SHA1 Message Date
Junzhi Zhao 0d2200794f drm/mediatek: modify the factor to make the pll_rate set in the 1G-2G range 
Currently, the code sets the "pll" to the desired multiple
of the pixel clock manully(4*3m 8*3,etc).  The valid range
of the pll is 1G-2G, however, when the pixel clock is bigger
than 167MHz,  the "pll" will be set to a invalid value( > 2G),
then the "pll" will be 2GHz, thus the pixel clock will be in
correct. Change the factor to make the "pll" be set in the
(1G, 2G) range.

Signed-off-by: Junzhi Zhao <junzhi.zhao@mediatek.com>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
 2016-10-19 09:07:08 +08:00
Philipp Zabel 515ba6a59c drm/mediatek: mtk_dpi: remove invalid error message 
Do not try to dereference dpi if it is NULL.
Since dpi can never be NULL when mtk_dpi_set_display_mode() is called,
remove the message.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
 2016-06-01 16:09:54 +02:00
Jie Qiu 9e629c17aa drm/mediatek: Add DPI sub driver 
Add DPI connector/encoder to support HDMI output via the
attached HDMI bridge.

Signed-off-by: Jie Qiu <jie.qiu@mediatek.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
 2016-05-06 17:47:38 +02:00