Commit Graph

18 Commits

Author SHA1 Message Date
Bill Pemberton 99688ed774 pinctrl: remove use of __devinitdata
CONFIG_HOTPLUG is going away as an option so __devinitdata is no
longer needed.

Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-11-28 11:55:55 -08:00
Bill Pemberton 2a36f08636 pinctrl: remove use of __devexit_p
CONFIG_HOTPLUG is going away as an option so __devexit_p is no longer
needed.

Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-11-28 11:55:55 -08:00
Vipul Kumar Samar 0504271c8d pinctrl: SPEAr1340: Add clcd sleep mode pin configuration
CLCD pads must be configured differently for sleep mode. This patch adds support
for clcd_sleep_pingroup.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05 12:34:32 +01:00
Deepak Sikri 35d1480694 pinctrl: SPEAr1340: Make DDR reset & clock pads as gpio
Some gpio pins are used to control DDR reset and clock enable while the system
is moved into Low power. This patch adds in the corresponding GPIO entries in
the pads_as_gpio_pins to ensure the pads are available as gpio's.

Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05 12:34:26 +01:00
Shiraz Hashim 0e6f1e5c39 pinctrl: SPEAr1310: add register entries for enabling pad direction
Pad direction must also be updated for SPEAr1310, while setting pads values.
This patch adds support for that.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05 12:34:23 +01:00
Vipul Kumar Samar f7c5b3d574 pinctrl: SPEAr1310: Separate out pci pins from pcie_sata pin group
SPEAr1310 has separate PCI and PCIe implementations which are not muxed with
each other. Presently they have been implemented as muxed together with SATA and
are represented wrongly in the software.

In reality only PCIe and SATA implementations are muxed with each other. This
patch separates out pci pins creating a new pingroup and function for pci.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05 12:34:20 +01:00
Vipul Kumar Samar 82a2deb93c pinctrl: SPEAr1310: Fix value of PERIP_CFG reigster and MCIF_SEL_SHIFT
This patch fixes two macros: PERIP_CFG registers offset and MCIF selection
shift.

Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05 12:33:57 +01:00
Shiraz Hashim b06fbfdb06 pinctrl: SPEAr1310: fix clcd high resolution pin group name
All group names in SPEAr pinctrl have "_grp" at the end of their name. Do the
same for clcd_high_res_grp.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05 12:33:46 +01:00
Deepak Sikri b06bf9a905 pinctrl: SPEAr320: Correct pad mux entries for rmii/smii
pin entries of rmii and smii are interchanged by mistake. Fix it.

Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05 12:33:41 +01:00
Shiraz Hashim a778005589 pinctrl: SPEAr3xx: correct register space to configure pwm
To have pwm on pad no. 34 we also need to select between pwm and SD_LED
functions. Add this to pwm pin mux register configuration.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05 12:33:37 +01:00
Viresh Kumar 0b53fa3535 pinctrl: SPEAr: Don't update all non muxreg bits on pinctrl_disable
Not all bits of a register are used for pinctrl in SPEAr. So only update bits
relevant to pinctrl using muxreg->mask.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-11-05 12:33:34 +01:00
Devendra Naga 8003ae335a pinctrl/pinctrl-spear: remove IS_ERR checking of pmx->pctl
pinctrl_register returns a pointer of struct type struct pinctrl_dev,
if successfully registered to pinctrl subsystem, otherwise returns
NULL, and there wont' be any pointers which are not dereferencible.

They are not type of pointer addresses but are kind of error
codes rather actual addresses, but are a kind of return
codes of functions returning integer types.

return -ENODEV if device registration fails.

Signed-off-by: Devendra Naga <devendra.aaru@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-07-03 21:51:08 +02:00
Viresh Kumar 10d8935f46 Viresh has moved
viresh.kumar@st.com email-id doesn't exist anymore as I have left the
company.  Replace ST's id with viresh.linux@gmail.com.

It also updates .mailmap file to fix address for 'git shortlog'

Signed-off-by: Viresh Kumar <viresh.linux@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-06-20 14:39:36 -07:00
Viresh Kumar eb3f995d7e pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-14 17:34:11 +02:00
Viresh Kumar 85ed41a76f pinctrl: Add SPEAr13xx pinctrl drivers
This adds pinctrl driver for SPEAr13xx family. SPEAr13xx family supports two
machines: SPEAr1310 and SPEAr1340.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-14 17:34:07 +02:00
Viresh Kumar d1e77afe9d pinctrl: SPEAr: Create macro for declaring GPIO PINS
Same GPIO pins declarations would be required for other SoCs and that will be a
lot of lines of code. Its better to create common macros for it.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-05-14 17:34:06 +02:00
Viresh Kumar 52130b6033 pinctrl: Add SPEAr3xx pinctrl drivers
This adds pinctrl driver for SPEAr3xx family. SPEAr3xx family supports three
families: SPEAr300, SPEAr310 and SPEAr320.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
2012-04-22 22:49:25 +02:00
Viresh Kumar deda8287e1 pinctrl: Add SPEAr pinctrl drivers
This adds pinctrl driver for SPEAr platform. It also updates MAINTAINERS file
for SPEAr pinctrl drivers.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
2012-04-22 22:49:23 +02:00