This adds support to specify the MAC address by 'mac-address' or
'local-mac-address' properties in the device tree. These are common
properties for the Ethernet controller.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Mike Sinkovsky <msink@permonline.ru>
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
This adds support for W5500 chip.
W5500 has similar register and memory organization with W5100 and W5200.
There are a few important differences listed below but it is still
possible to share common code with W5100 and W5200.
* W5500 register and memory are organized by multiple blocks. Each one
is selected by 16bits offset address and 5bits block select bits.
But the existing register access operations take u16 address. This change
extends the addess by u32 address and put offset address to lower 16bits
and block select bits to upper 16bits.
This change also adds the offset addresses for socket register and TX/RX
memory blocks to the driver private data structure in order to reduce
conditional switches for each chip.
* W5500 has the different register offset for socket interrupt mask
register. Newly added internal functions w5100_enable_intr() and
w5100_disable_intr() take care of the diffrence.
* W5500 has the different register offset for retry time-value register.
But this register is only used to verify that the reset value is correctly
read at initialization. So move the verification to w5100_hw_reset()
which already does different things for different chips.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Mike Sinkovsky <msink@permonline.ru>
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
This adds support for W5200 chip.
W5100 and W5200 have similar memory map although some of their offsets
are different. The register access sequences between them are different
but w5100 driver has abstraction layer for difference bus interface
modes so it is easy to add W5200 support to w5100 and w5100-spi drivers.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Mike Sinkovsky <msink@permonline.ru>
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
SPI transfer routines are callable only from contexts that can sleep.
This adds ability to tell the core driver that the interface mode
cannot access w5100 register on atomic contexts. In this case,
workqueue and threaded irq are required.
This also corrects timeout period waiting for command register to be
automatically cleared because the latency of the register access with
SPI transfer can be interfered by other contexts.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Mike Sinkovsky <msink@permonline.ru>
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
The w5100 driver currently only supports direct and indirect bus
interface mode which use MMIO space for accessing w5100 registers.
In order to support SPI interface mode which is supported by W5100 chip,
this makes the bus interface abstraction layer more generic so that
separated w5100-spi driver can use w5100 driver as core module.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Mike Sinkovsky <msink@permonline.ru>
Cc: David S. Miller <davem@davemloft.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
Akinobu Mita