Commit Graph

7 Commits

Author SHA1 Message Date
Peter De Schrijver a9952a76bc clk: tegra: Fix vic03 mux index
The vic03 mux uses a linear mapping.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2014-02-20 10:45:28 +02:00
Andrew Bresticker 20e7c323ab clk: tegra: fix sdmmc clks on Tegra1x4
The sdmmc clocks on Tegra114 and Tegra124 are 3-bit wide muxes with
6 parents.  Add support for tegra_clk_sdmmc*_8 and switch Tegra114
and Tegra124 to use these clocks instead.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:23 +02:00
Thierry Reding 2edf3e0353 clk: tegra: Correct clock number for UARTE
UARTE has clock number 66. Number 65 is the right one for UARTD.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-02-17 16:14:32 +02:00
Peter De Schrijver 3b34d8214d clk: tegra124: Add new peripheral clocks
Tegra124 introduces a number of new peripheral clocks. This patch adds those
to the common peripheral clock code.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26 18:46:54 +02:00
Peter De Schrijver b29f9e9264 clk: tegra: add TEGRA_PERIPH_NO_GATE
Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26 18:46:53 +02:00
Peter De Schrijver bc44275b8e clk: tegra: add locking to periph clks
Tegra124 has periph clocks which share the hw register. Hence locking is
required.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-26 18:46:52 +02:00
Peter De Schrijver 76ebc134d4 clk: tegra: move periph clocks to common file
Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26 18:46:47 +02:00