Commit Graph

12 Commits

Author SHA1 Message Date
Heiko Stuebner 605df8af33 phy: rockchip-usb: add handler for usb-uart functionality
Most newer Rockchip SoCs provide the possibility to use a usb-phy
as passthrough for the debug uart (uart2), making it possible to
for example get console output without needing to open the device.

This patch adds an early_initcall to enable this functionality
conditionally via the commandline and also disables the corresponding
usb controller in the devicetree.

Currently only data for the rk3288 is provided, but at least the
rk3188 and arm64 rk3368 also provide this functionality and will be
enabled later.

On a spliced usb cable the signals are tx on white wire(D+) and
rx on green wire(D-).

The one caveat is that currently the reconfiguration of the phy
happens as early_initcall, as the code depends on the unflattened
devicetree being available. Everything is fine if only a regular
console is active as the console-replay will happen after the
reconfiguation. But with earlycon active output up to smp-init
currently will get lost.

The phy is an optional property for the connected dwc2 controller,
so we still provide the phy device but fail all phy-ops with -EBUSY
to make sure the dwc2 does not try to transmit anything on the
repurposed phy.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2016-03-01 17:13:50 +05:30
Heiko Stuebner b74fe7c761 phy: rockchip-usb: expose the phy-internal PLLs
The USB phys on Rockchip SoCs contain their own internal PLLs to create
the 480MHz needed. Additionally this PLL output is also fed back into the
core clock-controller as possible source for clocks like the GPU or others.

Until now this was modelled incorrectly with a "virtual" factor clock in
the clock controller. The one big caveat is that if we turn off the usb phy
via the siddq signal, all analog components get turned off, including the
PLLs. It is therefore possible that a source clock gets disabled without
the clock driver ever knowing, possibly making the system hang.

Therefore register the phy-plls as real clocks that the clock driver can
then reference again normally, making the clock hirarchy finally reflect
the actual hardware.

The phy-ops get converted to simply turning that new clock on and off
which in turn controls the siddq signal of the phy.

Through this the driver gains handling for platform-specific data, to
handle the phy->clock name association.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-12-20 15:21:38 +05:30
Heiko Stuebner c2bfc3b888 phy: rockchip-usb: add compatible values for rk3066a and rk3188
We need custom handling for these two socs in the driver shortly,
so add the necessary compatible values to binding and driver.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-12-20 15:21:38 +05:30
Heiko Stuebner 97dd910109 phy: rockchip-usb: move per-phy init into a separate function
This unclutters the loop in probe a lot and makes current (and future)
error handling easier to read.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-12-20 15:21:38 +05:30
Heiko Stuebner 5fdbb97dec phy: rockchip-usb: introduce a common data-struct for the device
This introduces a common struct that holds data belonging to
the umbrella device that contains all the phys and that we
want to use later.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-12-20 15:21:38 +05:30
Heiko Stuebner 75d390fecf phy: rockchip-usb: fix clock get-put mismatch
Currently the phy driver only gets the optional clock reference but
never puts it again, neither during error handling nor on remove.
Fix that by moving the clk_put to a devm-action that gets called at
the right time when all other devm actions are done.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-12-20 15:21:38 +05:30
Julia Lawall f6f31af81c phy: rockchip-usb: add missing of_node_put
for_each_available_child_of_node performs an of_node_get on each iteration,
so a return from the middle of the loop requires an of_node_put.

A simplified version of the semantic patch that finds this problem is as
follows (http://coccinelle.lip6.fr):

// <smpl>
@@
expression root,e;
local idexpression child;
@@

 for_each_available_child_of_node(root, child) {
   ... when != of_node_put(child)
       when != e = child
(
   return child;
|
*  return ...;
)
   ...
 }
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-12-03 12:28:23 +05:30
huang lin 08db7e5cbf phy: rockchip-usb: power down phy when rockchip phy probe
rockchip phy are enable when soc reset, to save power consumption,
we disable it when probe, and enable each phy when it use

Signed-off-by: huang lin <hl@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-09-25 17:01:14 +05:30
Axel Lin 4a9e5ca1a5 phy: Constify struct phy_ops variables
The phy_ops variables are never modified after initialized in these
drivers, so make them const.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-08-03 18:35:09 +05:30
Krzysztof Kozlowski 219bf1599e phy: Drop owner assignment from platform_driver
platform_driver does not need to set an owner because
platform_driver_register() will set it.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-07-25 15:45:48 +05:30
Axel Lin 6b08e36ba3 phy: rockchip-usb: Fixup rockchip_usb_phy_power_on failure path
If rockchip_usb_phy_power() fails, we need to call clk_disable_unprepare()
before return. This is to ensure we have balanced clk_enable/disable calls.
Also remove unneeded ret checking in rockchip_usb_phy_power_off.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-03-12 11:01:17 +05:30
Yunzhi Li 64d11406de phy: add a driver for the Rockchip SoC internal USB2.0 PHY
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.

Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-01-30 16:06:47 +05:30