Commit Graph

58 Commits

Author SHA1 Message Date
Emilio López 89a9456d6e clk: sunxi: add __iomem markings to MMIO pointers
This commit adds __iomem thoughout the sunxi clock driver, in places
where it was ommited. This cleans most of the sparse warnings we
are getting here.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-28 15:39:05 -07:00
Chen-Yu Tsai 515c1a4bdc clk: sunxi: Add A23 clocks support
The clock control unit on the A23 is similar to the one found on the A31.

The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
on the A31, but some outputs are missing.

The main CPU PLL (PLL1) however is like that on older Allwinner SoCs,
such as the A10 or A20, but the N factor starts from 1 instead of 0.

This patch adds support for PLL1 and all the basic clock muxes and gates.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:05:17 +02:00
Chen-Yu Tsai ea5671bffb clk: sunxi: Add support for table-based divider clocks
A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.

This patch adds support for optional divider tables,
so the clock framework will know about the odd values.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:05:13 +02:00
Chen-Yu Tsai 70eab199fa clk: sunxi: move "ahb_sdram" to protected clock list
With sunxi_gates clocks registered with clkdev, we can use the
protected clocks list to enable the "ahb_sdram" clock, instead
of looking for it and adding CLK_IGNORE_UNUSED inline in the
clock setup code.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:05:09 +02:00
Chen-Yu Tsai d14e47056c clk: sunxi: register clock gates with clkdev
The new important clock protect code requires the clocks be
registered with clkdev. This was missing for sunxi_gates
type clocks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:04:55 +02:00
Maxime Ripard efb3184c08 clk: sun6i: Protect SDRAM gating bit
Prevent the SDRAM controller from being gated by force-enabling it in the
machine code.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 10:25:02 +02:00
Maxime Ripard 2df73f40dc clk: sun6i: Protect CPU clock
Right now, AHB is an indirect child clock of the CPU clock. If that
happens to change, since the CPU clock has no other consumers declared
in Linux, it would be shut down, which is not really a good idea.

Prevent this by forcing it enabled.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 10:25:01 +02:00
Maxime Ripard 134a6690a3 clk: sunxi: Rework clock protection code
Since we start to have a lot of clocks to protect, some of them in a
few SoCs only, it becomes difficult to handle the clock protection
without having to add per machine exceptions.

Add per-SoC data to tell which clock to leave enabled.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 10:25:01 +02:00
Maxime Ripard 59cb10e32a clk: sunxi: Move the GMAC clock to a file of its own
Since we have a folder of our own, we can actually make use of it by
splitting the huge clock file into several sub drivers.

The gmac clock is pretty easy to deal with, since it's pretty much
isolated and doesn't have any dependency on the other clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:44 +02:00
Maxime Ripard ff01df28e5 clk: sunxi: Move the 24M oscillator to a file of its own
Since we have a folder of our own, we can actually make use of it by
splitting the huge clock file into several sub drivers.

The main oscillator is pretty easy to deal with, since it's pretty much
isolated.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:44 +02:00
Maxime Ripard 2c6fba1038 clk: sunxi: Remove calls to clk_put
Callers of clk_put must disable the clock first. This also means that
as long as the clock is enabled the driver should hold a reference to
that clock. Hence, the call to clk_put here are bogus and should be
removed.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:44 +02:00
Maxime Ripard e0e7943c55 clk: sunxi: Implement A31 USB clock
The A31 USB clock slightly differ from its older counterparts, mostly
because it has a different gate for each PHY, while the older one had
a single gate for all the phy.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:43 +02:00
Linus Torvalds 1a5700bc2d The clock framework changes for 3.16 are pretty typical: mostly clock
driver additions and fixes. There are additions to the clock core code
 for some of the basic types (e.g. the common divider type has some fixes
 and featured added to it).
 
 One minor annoyance is a last-minute dependency that wasn't handled
 quite right. ba0fae3 in this pull request depends on
 include/dt-bindings/clock/berlin2.h, which is already in your tree via
 the arm-soc pull request. Building for the berlin platform will break
 when the clk tree is built on it's own, but merged into your master
 branch everything should be fine.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJTkhd7AAoJEDqPOy9afJhJ/kAQAKJt4slFYNW5t69HBmqlfkxR
 1Y61KqTaZiJ2XNqudNUDd6GkD5CW0pqD194dOXOLQMSGIZ3i+mHJ91ddV4x7J8xe
 +eAvaHqDc4XJyJouzOOxx2LhnThRUkpyXLzbXTITIoy4nK6K+ANg6hPjfBwTDs3m
 7dDu+WDYAN4EMjMffpPD26axl778H5FXzqJaKx+RmMDw6f3y6g+8hKCvSicetpAa
 AnTLhx8q4kbEmOZHOEny28KliOpDAMPd/nNcnjqpfKBSoq0J6aYGM0t5bUH+clY9
 nzjgMfE+pRm8N+oyssNCqT99ebeIxSF6Ps/EVZRJCETUi3s0n1/Y4dK3uPNOyo+G
 BSv0wfQ5M1IebmnIIlQuJ+zNvtKFkoLoi1Q/fsOr51HVfddwrEbd972+zYdjSeVe
 RXRb3HAStfQEjp0874VD9wr6u0tHskUrQGzHSSs8PNsfCv/URwJUPuS7XnePPXAZ
 KdtJST/b+WiY96pPJDLc44trRko1opxgncYqsusnWtwsUzK5aKnAbbYSiTIZhxJU
 44p7/xOokeTcgDuluEk8mR+PEX5EhGokYXOVXfSCMJOXehpHnpMHtzCieTcmJ9Ir
 NaOATHjSXwHI7jiv/W+EZQnZCnoHnST+GT4FtmjYkD3lzMpK9d/E9mxjKs8hUNgO
 xH71k4uL7WljxsVWp/16
 =2AAL
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux into next

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.16 are pretty typical: mostly clock
  driver additions and fixes.  There are additions to the clock core
  code for some of the basic types (e.g. the common divider type has
  some fixes and featured added to it).

  One minor annoyance is a last-minute dependency that wasn't handled
  quite right.  Commit ba0fae3b06 ("clk: berlin: add core clock driver
  for BG2/BG2CD") in this pull request depends on
  include/dt-bindings/clock/berlin2.h, which is already in your tree via
  the arm-soc pull request.  Building for the berlin platform will break
  when the clk tree is built on it's own, but merged into your master
  branch everything should be fine"

* tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits)
  mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
  clk: export __clk_round_rate for providers
  clk: versatile: free icst on error return
  clk: qcom: Return error pointers for unimplemented clocks
  clk: qcom: Support msm8974pro global clock control hardware
  clk: qcom: Properly support display clocks on msm8974
  clk: qcom: Support display RCG clocks
  clk: qcom: Return highest rate when round_rate() exceeds plan
  clk: qcom: Fix mmcc-8974's PLL configurations
  clk: qcom: Fix clk_rcg2_is_enabled() check
  clk: berlin: add core clock driver for BG2Q
  clk: berlin: add core clock driver for BG2/BG2CD
  clk: berlin: add driver for BG2x complex divider cells
  clk: berlin: add driver for BG2x simple PLLs
  clk: berlin: add driver for BG2x audio/video PLL
  clk: st: Terminate of match table
  clk/exynos4: Fix compilation warning
  ARM: shmobile: r8a7779: Add clock index macros for DT sources
  clk: divider: Fix overflow in clk_divider_bestdiv
  clk: u300: Terminate of match table
  ...
2014-06-07 20:27:30 -07:00
Rob Herring 83221923fc clk: sunxi: fix function type for CLK_OF_DECLARE
Adding function type checking to CLK_OF_DECLARE found a type mismatch with
sunxi_init_clocks. The function takes a single struct device_node
parameter.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-20 14:25:22 -05:00
Rob Herring cb7d5f425f clk: sunxi: avoid double DT matching
Use for_each_matching_node_and_match instead of for_each_matching_node plus
of_match_node to avoid searching the DT twice for each node.

The sunxi DT scanning code should really be re-worked rather than have
its own private matching infrastructure. It is working around needing a
function pointer and a data pointer for each compatible match.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: "Emilio López" <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-20 14:25:22 -05:00
Hans de Goede a97181adf1 clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clk
__clk_get_hw is supposed to be used by clk providers, not clk consumers.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-14 16:58:21 -07:00
Emilio López 95713978b0 clk: sunxi: Implement MMC phase control
HdG: add header exporting clk_sunxi_mmc_phase_control

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-05 15:55:57 -07:00
Emilio López 9ce71ca10f clk: sunxi: fix thinko in comment
This should read MOD0 and not MMC; MMC is just one example of a MOD0
clock.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19 12:35:07 -07:00
Emilio López 2226013972 clk: sunxi: fix some calculations
Some divisor calculations were misrounded, causing higher than requested
rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one
homebrew instance of it as well with the right macro.

Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19 12:34:56 -07:00
Emilio López 5a8ddf2682 clk: sunxi: fix A20 PLL4 calculation
Allwinner actually reworked the PLL4 on A20; now it's compatible with
the sun4i PLL5/6 design previous to any divisions, as well as to the new
PLL8 in sun7i.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19 12:34:39 -07:00
Maxime Ripard fd1b22f6fb clk: sunxi: Add new clock compatibles
The Allwinner A10 compatibles were following a slightly different compatible
patterns than the rest of the SoCs for historical reasons. Add compatibles
matching the other pattern to the clock driver for consistency, and keep the
older one for backward compatibility.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-18 10:34:28 -03:00
Chen-Yu Tsai e4c6d6c11b clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-18 10:34:28 -03:00
Maxime Ripard 92ef67c53a clk: sunxi: Add support for PLL6 on the A31
The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-18 09:45:13 -03:00
Roman Byshko 5abdbf2f49 clk: sunxi: Add USB clock register defintions
Add register definitions for the usb-clk register found on sun4i, sun5i and
sun7i SoCs.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-18 09:35:20 -03:00
Hans de Goede cfb0086dca clk: sunxi: Add support for USB clock-register reset bits
The usb-clk register is special in that it not only contains clk gate bits,
but also has a few reset bits. This commit adds support for this by allowing
gates type sunxi clks to also register a reset controller.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-18 09:29:10 -03:00
Chen-Yu Tsai 97e36b3ce3 clk: sunxi: get divs parent clock name from parent factor clock
Divs clocks consist of a parent factor clock with multiple outputs,
and seperate clocks for each output. Get the name of the parent
clock from the parent factor clock, instead of the DT node name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-03 00:24:33 -03:00
Chen-Yu Tsai 667f542db5 clk: sunxi: add names for pll5, pll6 parent clocks to factors_data
Some factor clocks, such as the parent clock of pll5 and pll6, have
multiple output names. Add the corresponding names to factors_data
tied to compatible string.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-03 00:24:32 -03:00
Chen-Yu Tsai f64111ebaf clk: sunxi: add clock-output-names dt property support
sunxi clock drivers use dt node name as clock name, but clock
nodes should be named clk@X, so the names would be the same.
Let the drivers read clock names from dt clock-output-names
property.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-02-03 00:24:32 -03:00
Emilio López d1933689aa clk: sunxi: fix overflow when setting up divided factors
Currently, we are allocating space for two pointers, when we actually
may need to store three of them (two divisors plus the original clock).
Fix this, and change sizeof(type) to sizeof(*var) to keep checkpatch.pl
happy.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-01-27 12:28:23 -08:00
Chen-Yu Tsai 6f86341726 clk: sunxi: Allwinner A20 output clock support
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
2013-12-28 17:14:21 -03:00
Emilio López 76192dc887 clk: sunxi: support better factor DT nodes
The DT nodes should look like

    abc_clk: clk@deadbeef {
        ...
        clock-output-names = "abc";
    }

But our old DT nodes look like

    abc: abc@deadbeef {
        ...
    }

So, let's support both formats, until we can transition everything
to the new, correct one.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28 17:08:25 -03:00
Emilio López 7551769a22 clk: sunxi: mod0 support
This commit implements support for the "module 0" type of clocks, as
used by MMC, IR, NAND, SATA and other components.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28 17:08:22 -03:00
Emilio López d584c1331d clk: sunxi: add PLL5 and PLL6 support
This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28 17:08:17 -03:00
Emilio López 5f4e0be3a7 clk: sunxi: make factors_clk_setup return the clock it registers
We will be needing this to register a factor clock as parent with leaf
divisors on a single call.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28 17:08:14 -03:00
Emilio López d838ff33ec clk: sunxi: add gating support to PLL1
This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28 17:08:06 -03:00
Emilio López edaf3fb580 clk: sunxi: clean the magic number of mux parents
This was pointed out during the review of the factor patches. Let's
indicate what does that magic 5 mean.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28 17:08:00 -03:00
Emilio López 40a5dcba4e clk: sunxi: register factors clocks behind composite
This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-12-28 17:07:42 -03:00
Mike Turquette 1d9438f7b5 Allwinner sunXi SoCs clock changes
Those are mostly random fixes, except for one patch to the composite
 clock that adds support for automatic reparenting.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABAgAGBQJSf2QbAAoJEBx+YmzsjxAg1FMP/0iMDhjaqpeKfoZdfS+eYOPZ
 tE3AJq3JiCIeWWojYvHKCc+4JhYb5w0rW95Z6XOtV0zRLMhyj97bObSRGXv+uL0K
 1xyGtGDCqfIP3TIPlMt6sKzBZi6DVHyjkyVjQ1BvGFHKYgsnbMaOgODzANMUf4kE
 L/Z7JQGpFKNJgcJq6H8RuCT6FQYpD+2nLNbqFTcM52XFB39I1ztLiKXDB9wju738
 +M+oiXGYrg9iorzK3t26VfgqyYDDkJe7fn+66SPhTGhiWLpOpas/8hNyU8+wUs7h
 q1ACiAfOW2VFrQMbAbH6Az7wydXPZ7ruYxvcO7Ihbua60w382czOpeZOABoQ+ikg
 Ogby1mRU0cydAYne0/B/Ege+e60PivZQQ+1/6F8vIGZ1e8s+9DJZETNQV14wQ7gx
 3uB9AsmdDCfW7ky5kIXk9WbdCYrmcagtbpkbCnf701O8bayJHiLCw96DIwz3/EMm
 p682Su4L1/w06uUjdRJgjkhZqYgCQgD7ZKfXUEw8QIrTSTh9qQyXmWY0lpgW3c72
 WCLGp9TGeonuH4LxUAllFHNNQpsaZzeYSoz4q5+qkuqo3p12S7vzAQU4T/7LKL6y
 BMfVYPYB5HZof0vG/Cyngvjq9pq7dq+4eFwcwOJ4F6/UsNdBtmUcTEMbBnjfre4E
 V0U5CWDWhGI1s3n9Ibx3
 =sWyX
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-next-sunxi-rebase

Allwinner sunXi SoCs clock changes

Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.

Conflicts:
	drivers/clk/sunxi/clk-sunxi.c
2013-12-01 12:42:45 -08:00
Victor N. Ramos Mello e71c69fc33 drivers: clk: sunxi: Fix memory leakage in clk-sunxi.c
Fix a possible memory leak in sun4i_osc_clk_setup().
Moved clock-frequency check to save superfluous allocation.

Signed-off-by: Victor N. Ramos Mello <victornrm@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-11-10 11:40:51 +01:00
Emilio López 8e6a4c40bb clk: sunxi: protect core clocks from accidental shutdown
Some important clocks may get disabled as a side effect of another clock
being disabled, because they have no consumers. This patch implements a
mechanism so those clocks can be claimed by the driver and therefore
remain enabled at all times.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2013-11-10 11:39:55 +01:00
Sebastian Hesselbarth be0804513a clk: sunxi: declare OF clock provider
Common clock framework allows to register clock providers to get called
on of_clk_init() by using CLK_OF_DECLARE. This converts sunxi clock
providers to make use of it and get rid of the mach specific clk init
call. As sunxi has a bunch of independent clk provider nodes, we hook
current clock init to board compatible to make it called once.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
2013-09-29 21:07:16 +02:00
Sachin Kamat 52be7cc862 clk: sunxi: Fix incorrect placement of __initconst
__initconst should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: refreshed patch based on sunxi changes]
2013-08-27 18:35:43 -07:00
Maxime Ripard 1fb2e4aab8 clk: sunxi: Add Allwinner A20 gates
The Allwinner A20 is almost identical to the earlier A10 SoC from
Allwinner on many aspects, including the clocks tree. However, since the
A20 has some additionnal IPs compared to the A10, the clock tree isn't
exactly the same, especially when it comes to the gated clocks
available. We thus need to register different clock gates for the A20.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Emilio López <emilio@elopez.com.ar>
2013-08-26 10:58:21 +02:00
Maxime Ripard 6a721db180 clk: sunxi: Add A31 clocks support
The A31 has a mostly different clock set compared to the other older
SoCs currently supported in the Allwinner clock driver.

Add support for the basic useful clocks. The other ones will come in
eventually.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Emilio López <emilio@elopez.com.ar>
2013-08-26 10:58:11 +02:00
Maxime Ripard 70855bb5c6 clk: sunxi: Allow to specify the divider width from the dividers data
The divider width used to be hardcoded. Some A31 dividers are no longer
with the hardcoded width, so we need to make it specific to each divider
and set it in the dividers data.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Emilio López <emilio@elopez.com.ar>
2013-08-26 10:48:45 +02:00
Maxime Ripard 81ba6c5e7b clk: sunxi: Rename the structure to prepare the addition of sun6i
Rename all the generic-named structure to sun4i to avoid confusion when
we will introduce the sun6i (A31) clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Emilio López <emilio@elopez.com.ar>
2013-08-26 10:48:44 +02:00
Emilio López 431807f0bf clk: sunxi: fix initialization of basic clocks
With the recent move towards CLK_OF_DECLARE(...), the driver stopped
initializing osc32k, which is compatible "fixed-clock". This is because
we never called of_clk_init(NULL). Fix this by moving the only other
simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL)
to initialize both of them.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
2013-08-26 10:48:39 +02:00
Maxime Ripard 2371dd88b8 clk: sunxi: Add A10s gates
The Allwinner A10s has a slightly different gates set than the A10 and
A13, so add these gates to the clk driver.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Emilio López <emilio@elopez.com.ar>
2013-08-26 10:46:32 +02:00
James Hogan 819c1de344 clk: add CLK_SET_RATE_NO_REPARENT flag
Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes
being reparented during clk_set_rate.

To avoid breaking existing platforms, all callers of clk_register_mux()
are adjusted to pass the new flag. Platform maintainers are encouraged
to remove the flag if they wish to allow mux reparenting on set_rate.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Cc: Chao Xie <xiechao.mail@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrew Chew <achew@nvidia.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: spear-devel@list.st.com
Cc: linux-tegra@vger.kernel.org
Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Stephen Warren <swarren@nvidia.com> [tegra]
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi]
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-19 12:27:17 -07:00
Axel Lin ee85e9bd25 clk: sunxi: Fix checking return value of clk_register_[composite|factors]
clk_register_composite() and clk_register_factors() return ERR_PTR on error.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:27 -07:00