The clock controller also includes some reset lines. This patch
implements a reset controller to assert and de-assert these resets.
The reset controller itself is registered early (through
CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot
process (to start the secondary CPU cores).
According to the public S805 datasheet there are two more reset bits
in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by
this patch (as these seem to be unused in Amlogic's vendor Linux kernel
sources and their u-boot tree):
- bit 15: GEN_DIV_SOFT_RESET
- bit 14: SOFT_RESET
All information was taken from the public S805 Datasheet and Amlogic's
vendor GPL kernel sources. This patch is based on an earlier version
submitted by Carlo Caione.
Suggested-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Add the clkids for the clocks feeding the input0 of the mmc controllers
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Expose all clocks which maybe used as DT bindings
Only clock ids internal the controller remain un-exposed
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Expose all clocks which maybe used as DT bindings
Only clock ids internal the controller remain un-exposed (none on this
particular controller at the moment)
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
gxbb clock driver gracefully handles case where the clkid is defined but
the clock hw pointer is not provided, as long as it is not at the end of
the hw_onecell_data array.
This patch ensure that the last entries are defined as well to handle
this particular case.
Fixes: a70c6e06ed ("clk: meson: gxbb: protect against holes in the onecell_data array")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
meson8b clock driver gracefully handles case where the clkid is defined
but the clock hw pointer is not provided, as long as it is not at the end
of the hw_onecell_data array.
This patch ensure that the last entries are defined as well to handle
this particular case.
Fixes: e92f7cca44 ("clk: meson8b: clean up fixed rate clocks")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
can be adjusted by changing the frequency of the PLL_CPUX clock.
Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
clock can be adjusted when adjusting the CPUX clock.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Fixes: 0577e4853b ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should prevent any system hangs
resulting from cpufreq changes to the clk.
Reported-by: Ondrej Jirman <megous@megous.com>
Fixes: 0577e4853b ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
This SoC is too old. It is difficult to maintain any longer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently a bug in the sci_clk_get implementation causes it to always
return a clock belonging to the last device in the static list of clock
data. This is due to a bug in the init code that causes the array
used by sci_clk_get to only be populated with the clocks for the last
device, as each device overwrites the entire array with its own clocks.
Fix this by calculating the actual number of clocks for the SoC, and
allocating the whole array in one go. Also, we don't need the handle
to the init data array anymore after doing this, instead we can
just compare the dev_id / clk_id against the registered clocks and
use binary search for speed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Dave Gerlach <d-gerlach@ti.com>
Fixes: b745c0794e ("clk: keystone: Add sci-clk driver support")
Cc: Nishanth Menon <nm@ti.com>
Tested-by: Franklin Cooper <fcooper@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
One critical clock fix for sun5i (A10s/A13/R8) which enables propogation
of clock rate changes from the "cpu" clock to it's parent PLL clock.
This fixes cpufreq related crashes that have been observed on KernelCI
with the C.H.I.P. and multi_v7_defconfig.
-----BEGIN PGP SIGNATURE-----
iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAlmBWB8OHHdlbnNAY3Np
ZS5vcmcACgkQOJpUIZwPJDBGvRAAkwO1p1Aw62i5QmrGox3iyWabH/Rbon0M+tLQ
jP+kVukWrLR8REclkpwXqSK07Blg5m3o1MVMJXBKKOD6NAKCPOJoN75K/aX44fzZ
msrTuuzGkixovkG7p8ln253v/TOoBMwwK+QDtTOk7zBNEZuRKevKAUOglQTJYTmy
um7cVsisv5Yr89vtG767o0UyP82TUbnga6yLYY+72PbEKP1MnJtR0gzQp6Y9zxmW
Oyt7MaHH7km6SDGrQUWgQ8SvZ36s3uLxPfrtPx0zbTE1sM31sgdHf4kZmciP7Yap
eiLoHxV+twVxrgYh/Fl7BxOMfSqdIpZrzL3z2N3Hc53oARjOSl9c3N12UVzC0D0K
lRldFpmW26U21xMp22033j6uW9daU2PmyybNyJu892DRfY8RcX2N7otwIgAtxEtY
SKvVaG/uin2WVXs5FsxbpBUOm5xEJ04547TXuEegGjKyEv8+d1lCO6yU8i6xdUE0
qBzNm5rNuuSTD5zKu41YpEWhMWxEFEJE+Cx/tsCOhaySDuKKOrV7Bbd15ec3PjRD
llv2TvJNiBAkm4pakOsLZcDKk6RWqBEoN+6GXuC/66Dm+k+rR0nsRthDk418pDF2
T8YgG1p5wETdh/DfnUnwg63xN/dVs4On8IJkGunznTTGMxHiYduQsmqAxkgaRq6h
k4insAE=
=uoCy
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull one Allwinner clock fix from Chen-Yu Tsai:
One critical clock fix for sun5i (A10s/A13/R8) which enables propagation
of clock rate changes from the "cpu" clock to it's parent PLL clock.
This fixes cpufreq related crashes that have been observed on KernelCI
with the C.H.I.P. and multi_v7_defconfig.
* tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider
Fixes: 007e6e5c5f ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be
set before returning. Because of that, unstable clock may be used.
Add a wait for lock in the helper function.
Fixes: 89a3dfb787 ("clk: sunxi-ng: Add fractional lib")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ccu_frac_helper_read_rate() prints some info which is not really
helpful except during debugging.
Replace printk() with pr_debug().
Fixes: 89a3dfb787 ("clk: sunxi-ng: Add fractional lib")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Driver for multiplier clock is missing a call to
ccu_frac_helper_enable() when fractional mode is selected.
Add a call to ccu_frac_helper_enable().
Fixes: d77e8135b3 ("clk: sunxi-ng: multiplier: Add fractional support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
N-M factor clock driver is missing a call to ccu_frac_helper_enable()
when fractional mode is used. Additionally, most SoCs require that M
factor must be set to 0 when fractional mode is used.
Without this patch, clock keeps the old value and clk_set_rate() returns
without error.
Fixes: 6174a1e24b ("clk: sunxi-ng: Add N-M-factor clock support")
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This patch fixes values of the EPLL K coefficient and changes
the EPLL output frequency values to match exactly what is
possible to achieve with given M, P, S, K coefficients.
This allows to avoid rounding errors and unexpected frequency
being set with clk_set_rate(), due to recalc_rate returning
different values than the PLL rate specified in the
exynos5420_epll_24mhz_tbl table. E.g. this prevents a case
where two consecutive clk_set_rate() calls with same argument
result in different PLL output frequency.
The PLL output frequencies have been calculated with formula:
f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16
where fxtal = 24000000.
Fixes: 9842452acd ("clk: samsung: exynos542x: Add EPLL rate table")
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Remove trailing extra underscore in definition of _CCU_SUN8I_R_H
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The current CPU clock is missing the option to change the rate of its
parents, leading to improper rates calculated by cpufreq, and eventually
crashes.
Cc: <stable@vger.kernel.org>
Fixes: 5e73761786 ("clk: sunxi-ng: Add sun5i CCU driver")
Reported-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: "Emilio López" <emilio@elopez.com.ar>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Register each PLL and its division clocks to clock
lookup table to facilitate the clock look up for
clock consumer.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Clock on ls1088a chip takes primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP modules.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Do the checks for accessing the SD divider table only when the rate gets
updated, namely on init and set_rate. In all other cases, reuse the last
value. This simplifies code, runtime load, and error reporting.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
'rate' is not used, so we can use 'parent_rate' directly.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Read the enable register to determine if the clock is already in use by
the firmware. In this case avoid gating the clock.
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Darren Hart (VMware) <dvhart@infradead.org>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Fixes: 282a4e4ce5 ("platform/x86: Enable Atom PMC platform clocks")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Drop static on a local variable, when the variable is initialized before
any possible use. Thus, the static has no benefit.
The semantic patch that fixes this problem is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@bad exists@
position p;
identifier x;
type T;
@@
static T x@p;
...
x = <+...x...+>
@@
identifier x;
expression e;
type T;
position p != bad.p;
@@
-static
T x@p;
... when != x
when strict
?x = e;
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Remove unnecessary static on local variable _base_ in both functions
moxart_of_pll_clk_init() and moxart_of_apb_clk_init(). Such variables
are initialized before being used, on every execution path throughout
the mentioned functions. The statics have no benefit and, removing
them reduce the code size.
This issue was detected using Coccinelle and the following semantic patch:
@bad exists@
position p;
identifier x;
type T;
@@
static T x@p;
...
x = <+...x...+>
@@
identifier x;
expression e;
type T;
position p != bad.p;
@@
-static
T x@p;
... when != x
when strict
?x = e;
In the following log you can see the difference in the code size. Also,
notice that the bss segment is reduced down to zero. This log is the
output of the size command, before and after the code change:
before:
text data bss dec hex filename
1724 384 128 2236 8bc drivers/clk/clk-moxart.o
after:
text data bss dec hex filename
1697 240 0 1937 791 drivers/clk/clk-moxart.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
As there is no way to actually query the hardware for the current clock
rate, now racalc_rate() just returns the last rate that was previously
set. But if the rate was not set yet, we return the bogus rate of 1000Hz.
The branch clocks have the same rate as their parent, so in this case we
just need to remove recalc_rate ops and then the core framework will handle
this automagically. The round_rate() is unused, so remove it as well.
Reported-by: Archit Taneja <architt@codeaurora.org>
Fixes: 00f64b5887 ("clk: qcom: Add support for SMD-RPM Clocks")
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Fixed the signedness bug returning '(-22)' on the return type as u8 with
removing the sanity checker in clk_cpumux_get_parent() since
clk_cpumux_set_parent() always ensures validity in clk_cpumux_get_parent()
got called.
Fixes: 1e17de9049 ("clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
commit e2860e1f62 ("serial: 8250_of: Add reset support")
introduced reset support for the 8250_of driver.
However it unconditionally uses the assert/deassert pair to
deassert reset on the device at probe and assert it at
remove. This does not work with systems that have a
self-deasserting reset controller, such as Gemini, that
recently added a reset controller.
As a result, the console will not probe on the Gemini with
this message:
Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
of_serial: probe of 42000000.serial failed with error -524
This (-ENOTSUPP) is the error code returned by the
deassert() operation on self-deasserting reset controllers.
To work around this, implement dummy .assert() and
.deassert() operations in the Gemini combined clock and
reset controller. This fixes the issue on this system.
Cc: Joel Stanley <joel@jms.id.au>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-serial@vger.kernel.org
Fixes: e2860e1f62 ("serial: 8250_of: Add reset support")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Update IDT VersaClock 5 driver to support 5P49V5925. This chip has only
external clock input, four fractional dividers (FODs) and five clock
outputs (four universal clock outputs and one reference clock output at
OUT0_SELB_I2C).
Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901.
This chip has two clock inputs (external XTAL or external CLKIN), four
fractional dividers (FODs) and five clock outputs (four universal clock
outputs and one reference clock output at OUT0_SELB_I2C).
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
on Salvator-XS with the display LVDS output.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The VersaClock 6 has an input frequency doubler between the input
clock mux and the predivider. Add new capability flag and support
for this frequency doubler block into the driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
on Salvator-XS with the display LVDS output.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Split the VC5 clock input mux and the predivider to more accurately
model the hardware and fix the previously incorrect assumption that
both the OUT_SEL_I2CB and the PLL are fed from the predivider.
It is in fact the clock input mux output which is directly feeding
the clock into the OUT_SEL_I2CB output, while the clock input mux
output first passes through the predivider before it is fed into
the PLL.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
on Salvator-XS with the display LVDS output.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The output buffer input mux can be configured in either of three
states -- disabled, input from FOD, input from previous output.
Once the .prepare() callback of the output buffer is called, the
output buffer input mux must be set to either input from FOD or
input from previous output, it cannot be set to Disabled anymore
or the output won't work.
Default to the input from FOD if the output buffer input mux was
Disabled and the .prepare() was called on it.
Note that we do not set the output buffer input mux back to Disabled
in the .unprepare() callback as there is no obvious benefit of doing
so. We disable the entire output buffer in the .unprepare() callback
already.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The output buffer input mux can be configured in either of three
states -- disabled, input from FOD, input from previous output.
If the output buffer input mux is set to disabled, the code in
vc5_clk_out_get_parent() would consider this an invalid setting
and warn about it, which is not necessarily the case.
In case the output buffer input mux is disabled, default to input
from FOD to have some parent and don't print the warning.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
In case the initial values of the FOD registers are not configured in
the OTP or by the bootloader, it is possible that the FOD registers
will contain zeroes. The code in vc5_fod_recalc_rate() immediately
feeds the FOD divider value obtained from the FOD registers into the
div64_u64() and if the FOD divider value is zero, triggers division
by zero exception.
Check if the FOD divider value is zero and return the frequency of
the FOD output as 0 Hz if it is so. This prevents the division by
zero exception.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
AXS10X boards manages it's clocks using various PLLs. These PLL has same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.
We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.
As of today we add support for PLLs that generate clock for the
following devices:
* ARC core on AXC CPU tiles.
* ARC PGU on ARC SDP Mainboard.
and more to come later.
By this patch we add support for two plls (arc core pll and pgu pll),
so we had to use two different init types: CLK_OF_DECLARE for arc core pll and
regular probing for pgu pll.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
[sboyd@codeaurora.org: Silence dubious !x & y sparse warning,
make of_axs10x_pll_clk_setup() unregister clk on failure]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Enable compile-testing of the remaining clock drivers and subdrivers,
now dummies are available for of_clk_get_from_provider(),
of_device_compatible_match(), and rcar_rst_read_mode_pins(), and the
CPG/MSSR driver core has been converted from of_match_node() to
of_device_get_match_data().
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add the missing documentation for the fields in struct div6_clock
related to parent selection for DIV6 clocks with selectable parents, as
found in R/SH-Mobile SoCs.
Fixes: c6d67fb037 ("clk: shmobile: div6: support selectable-input clocks")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Pull MIPS updates from Ralf Baechle:
"Boston platform support:
- Document DT bindings
- Add CLK driver for board clocks
CM:
- Avoid per-core locking with CM3 & higher
- WARN on attempt to lock invalid VP, not BUG
CPS:
- Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6
- Prevent multi-core with dcache aliasing
- Handle cores not powering down more gracefully
- Handle spurious VP starts more gracefully
DSP:
- Add lwx & lhx missaligned access support
eBPF:
- Add MIPS support along with many supporting change to add the
required infrastructure
Generic arch code:
- Misc sysmips MIPS_ATOMIC_SET fixes
- Drop duplicate HAVE_SYSCALL_TRACEPOINTS
- Negate error syscall return in trace
- Correct forced syscall errors
- Traced negative syscalls should return -ENOSYS
- Allow samples/bpf/tracex5 to access syscall arguments for sane
traces
- Cleanup from old Kconfig options in defconfigs
- Fix PREF instruction usage by memcpy for MIPS R6
- Fix various special cases in the FPU eulation
- Fix some special cases in MIPS16e2 support
- Fix MIPS I ISA /proc/cpuinfo reporting
- Sort MIPS Kconfig alphabetically
- Fix minimum alignment requirement of IRQ stack as required by
ABI / GCC
- Fix special cases in the module loader
- Perform post-DMA cache flushes on systems with MAARs
- Probe the I6500 CPU
- Cleanup cmpxchg and add support for 1 and 2 byte operations
- Use queued read/write locks (qrwlock)
- Use queued spinlocks (qspinlock)
- Add CPU shared FTLB feature detection
- Handle tlbex-tlbp race condition
- Allow storing pgd in C0_CONTEXT for MIPSr6
- Use current_cpu_type() in m4kc_tlbp_war()
- Support Boston in the generic kernel
Generic platform:
- yamon-dt: Pull YAMON DT shim code out of SEAD-3 board
- yamon-dt: Support > 256MB of RAM
- yamon-dt: Use serial* rather than uart* aliases
- Abstract FDT fixup application
- Set RTC_ALWAYS_BCD to 0
- Add a MAINTAINERS entry
core kernel:
- qspinlock.c: include linux/prefetch.h
Loongson 3:
- Add support
Perf:
- Add I6500 support
SEAD-3:
- Remove GIC timer from DT
- Set interrupt-parent per-device, not at root node
- Fix GIC interrupt specifiers
SMP:
- Skip IPI setup if we only have a single CPU
VDSO:
- Make comment match reality
- Improvements to time code in VDSO"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits)
locking/qspinlock: Include linux/prefetch.h
MIPS: Fix MIPS I ISA /proc/cpuinfo reporting
MIPS: Fix minimum alignment requirement of IRQ stack
MIPS: generic: Support MIPS Boston development boards
MIPS: DTS: img: Don't attempt to build-in all .dtb files
clk: boston: Add a driver for MIPS Boston board clocks
dt-bindings: Document img,boston-clock binding
MIPS: Traced negative syscalls should return -ENOSYS
MIPS: Correct forced syscall errors
MIPS: Negate error syscall return in trace
MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select
MIPS16e2: Provide feature overrides for non-MIPS16 systems
MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo
MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions
MIPS: MIPS16e2: Identify ASE presence
MIPS: VDSO: Fix a mismatch between comment and preprocessor constant
MIPS: VDSO: Add implementation of gettimeofday() fallback
MIPS: VDSO: Add implementation of clock_gettime() fallback
MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse()
MIPS: Use current_cpu_type() in m4kc_tlbp_war()
...
Add a driver for the clocks provided by the MIPS Boston board from
Imagination Technologies. 2 clocks are provided - the system clock & the
CPU clock - and each is a simple fixed rate clock whose frequency can be
determined by reading a register provided by the board.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16483/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The probe does a shift and mask of val without having read it from the hardware.
Fixes: 846423f967 ("clk: Add Gemini SoC clock controller")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Current implementation of scpi_clk_add just print a warning when clock
fails to register but then keep going as if nothing happened. The
provider is then registered with bogus data.
This may latter lead to an Oops in __clk_create_clk when
hlist_add_head(&clk->clks_node, &hw->core->clks) is called.
This patch fixes the issue and errors if a clock fails to register.
Fixes: cd52c2a4b5 ("clk: add support for clocks provided by SCP(System Control Processor)")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
On sama5d2, VDD core maybe be cut while in suspend. This means registers
will be lost. Ensure they are saved and restored properly.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
CONFIG_COMPILE_TEST allows building a configuration without
TI_SCI_PROTOCOL, which then fails to link:
drivers/clk/keystone/sci-clk.o: In function `ti_sci_clk_probe':
sci-clk.c:(.text.ti_sci_clk_probe+0x4c): undefined reference to `devm_ti_sci_get_handle'
This makes it a hard dependency. Right now, that means we can't
actually compile-test the driver unless ARCH_KEYSTONE is set as
well, but we can fix that by allowing TI_MESSAGE_MANAGER to
be selected for COMPILE_TEST as well.
Fixes: b745c0794e ("clk: keystone: Add sci-clk driver support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Similarly to commit f1e9203e23 ("clk: samsung: Fix Exynos 5420 pinctrl
setup and clock disable failure due to domain being gated") for
Exynos5420, the Exynos4412 also requires that EPLL is not disabled.
Otherwise any access to MAUDIO block will silently halt.
This was not visible before because EPLL on Exynos4 could not be
disabled before commit 6edfa11cb3 ("clk: samsung:
Add enable/disable operation for PLL36XX clocks"). After this commit,
on Odroid U3 board one can see silent hang, usually with last (but
unrelated) messages:
[ 2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[ 2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci
[ 2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653)
Mark Exynos4 variant as also needed EPLL to be enabled all the time.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This allows the NAND driver to get the clock rate via clk_get_rate().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock
controller that derive all clocks from a single crystal, using some
documented and some undocumented PLLs, half dividers, counters and
gates. This is a best attempt to construct a clock driver for the
clocks so at least we can gate off unused hardware and driver the
PCI bus clock.
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[sboyd@codeaurora.org: Fix devm_ioremap_resource() return value
checking]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Now that this function is called from driver probe routines, it
needs to drop the __init marking because it isn't just called
from init code.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Cc: Anup Patel <anup.patel@broadcom.com>
Cc: Ray Jui <ray.jui@broadcom.com>
Cc: Scott Branden <scott.branden@broadcom.com>
Fixes: 654cdd3229 ("clk: bcm: Add clocks for Stingray SOC")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds support for Stingray clocks in iproc
ccf. The Stingray SOC has various plls based on iproc
pll architecture.
Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
up cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds CPU multiplexer clocks which are essential for Mediatek
cpufreq driver. It would use the CPU clock multiplexer to switch to the
intermediate clock source temporarily and then wait for the primary clock
changing getting stable.
Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
If CONFIG_OF=n:
drivers/clk/renesas/renesas-cpg-mssr.c: In function ‘cpg_mssr_probe’:
drivers/clk/renesas/renesas-cpg-mssr.c:702: warning: dereferencing ‘void *’ pointer
drivers/clk/renesas/renesas-cpg-mssr.c:702: error: request for member ‘data’ in something not a structure or union
To fix this, use the of_device_get_match_data() helper, for which a
dummy version is provided if CONFIG_OF=n.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Export I2S mux clocks, so that device tree can refer to them for setting
a better parent clock for I2S work clock.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
and NAND_CLK_ROOT. However, the gate has been in the chain of the
latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
only, e.g. as required by APBH-Bridge-DMA.
Add new clocks which represent the clock after the gate, and use a
shared clock gate to correctly model the hardware.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Set PPLL2 to 2880M. With this patch, we saw better compatibility
on various 1080p HDMI monitors.
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Zheng Shaobo <zhengshaobo1@huawei.com>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
[sboyd@codeaurora.org: Add UL to long number to silence C90
warning]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Parent name of clk_mux_sysbus is not correct. This patch fixes it.
Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
MCLK for internal audio codec is expected to be at 9.6MHz by default.
This patch adds support to 9.6MHz to make the default case possible.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds support for the global clock controller found on
the ipq8074 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Mark an array of strings static const and remove the dereference
of a function pointer when assigning to the platform driver probe
struct member.
drivers/clk/mvebu/cp110-system-controller.c:89:12:
warning: symbol 'gate_base_names' was not declared. Should it be static?
drivers/clk/mvebu/cp110-system-controller.c:447:18:
error: cannot dereference this type
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull improved Marvel Armada 7K/8K cp110 clk support from Gregory CLEMENT:
We got more information about the clock controllers and the clock tree
of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The
clk driver is modified accordingly from this new information.
* 'clk-cp110' of git://git.infradead.org/linux-mvebu:
clk: mvebu: cp110: add sdio clock to cp-110 system controller
clk: mvebu: cp110: introduce a new binding
clk: mvebu: cp110: do not depend anymore of the *-clock-output-names
clk: mvebu: cp110: make failure labels more meaningful
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are
offset by 1 additional bit.
Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and
Stratix10 platforms.
Fixes: 5611a5ba8e ("clk: socfpga: update clk.h so for Arria10 platform to use")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The timer will register into system at very early phase at kernel boot;
if timer needs to use clock, the clock should be get ready in function
of_clk_init() so later the timer driver probe can retrieve clock
successfully. This is finished in below flow on arm64:
start_kernel()
`-> time_init()
`-> of_clk_init(NULL) => register timer's clock
`-> clocksource_probe() => register timer
On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered
as platform driver rather than CLK_OF_DECLARE_DRIVER method. As result,
sp804 timer probe returns failure due if cannot bind clock properly.
To fix the failure, this patch is to split crgctrl clocks into two
subsets. One part is for fixed_rate_clks which includes pre-defined
fixed rate clocks, and "osc32k" clock is in this category; So we change
their registration to CLK_OF_DECLARE_DRIVER method, as result the clocks
can be registered ahead with function of_clk_init() and timer driver can
bind timer clock successfully; the rest of the crgctrl clocks are still
registered by the probe of the platform driver.
This patch also adds checking for all crgctrl clocks registration and
print out log if any clock has failure.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit updates the CP110 system controller driver to add the
definition for a missing clock.
The SDIO clock is dedicated driving the SDHCI interface and its frequency
is 400MHz (2/5 of PLL source clock).
The SDIO interface should be bound to this clock and not the core clock
as in the older code.
Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
the HW really supports up to 400 Mhz.
This patch also fixes the NAND clock relationship documentation.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
[gregory.clement@free-electrons.com:
- use sdio instead of emmc to name the clock]
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The initial intent when the binding of the cp110 system controller was to
have one flat node. The idea being that what is currently a clock-only
driver in drivers would become a MFD driver, exposing the clock, GPIO and
pinctrl functionality. However, after taking a step back, this would lead
to a messy binding. Indeed, a single node would be a GPIO controller,
clock controller, pinmux controller, and more.
This patch adopts a more classical solution of a top-level syscon node
with sub-nodes for the individual devices. The main benefit will be to
have each functional block associated to its own sub-node where we can
put its own properties.
The introduction of the Armada 7K/8K is still in the early stage so the
plan is to remove the old binding. However, we don't want to break the
device tree compatibility for the few devices already in the field. For
this we still keep the support of the legacy compatible string with a big
warning in the kernel about updating the device tree.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Using the *-clock-output-names property was a convenient way to have a
unique name for each clock even when there are multiple cp110 blocks
as we can find on Armada 8K.
However it has some drawbacks: the main one being a stronger link than
necessary between the driver and the device tree. For example the clock
name can't be changed, removed or moved. It is still the early stage of
introduction of the Armada 7K/8K and the hardware is still not totally
documented, especially for the clock part. By removing the use of
*-clock-output-names it will be easier to add new clocks without breaking
the compatibility.
The name of each clock is now created by using its physical address as a
prefix (as it was done for the platform device names). Thanks to this we
have an automatic way to compute a unique name.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* Add new compatible to the meson8 clock controller for meson8b
* Add missing parents to gxbb clk81
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJZRDQVAAoJEAFRo5MEFpTRaVgQAKqGVc39PNOGuzx8P2pj4H0B
lhedpQu7XHTGc7/2/b8ezMwzgnlHnFsAJOnzpLj4FbUNbNSlJmJFaBfybbV1cgd+
MF1cN9D5ssqI5zjkXeIhhZO6ogoe3AUlhjqKJMQfK2jlbQdF9Y9GrCIFFdzj/xC8
pwI4UxRg1g0SGfsF76IaGWeBsduYr9kzZJ3Xr1zUIi32bn/peTaHL+Ye/tv8ssir
NPnIXDte8XV+gmlOk0Ir1ELqIt501UfbljKmknU4FtVmOH9B/xkuxxOZU0w0Ia1o
6uoXKDMVENQO+LFWifdexIKh5MV7fXC1wynYoiqTd0BiOA2vKryTo4lcqPblWA5T
V95wIqwjsk6+XHl5uEFT7HPm2V5QEmBKzeDA4ng6hlGB7GYxZFhpzZQK4lnNrML0
pB+crpY9/5lAdQlpC/XMkOHORhJ0862ktT45TplToprowWadnmLZBbHB7QcNe+iH
z8v26eoh800YTN5KMfiSjPXNRW6GPS8YKJmT/9vx35+ysKFMD2fW2FmM7DL5LN+M
Bv+fgbJSJ4slniqMzFCEVWfcMESGltAYKM8G2YpPUF1uf99SnRweFwf7tshPSvJ4
bhvnqUdKsWxMgag3aL2D5eKq+yCRlk6/3zobq5qlCAomr9XDMm97C4CGmFUn40iV
xiIzVBXoiydjJyaBLSzX
=0BO9
-----END PGP SIGNATURE-----
Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into clk-next
Pull Amlogic clk driver updates from Jerome Brunet:
* Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH)
* Add new compatible to the meson8 clock controller for meson8b
* Add missing parents to gxbb clk81
* tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson:
clk: meson: gxbb: add all clk81 parents
clk: meson: meson8b: add compatibles for Meson8 and Meson8m2
clk: meson8b: export the ethernet gate clock
clk: meson8b: export the USB clocks
clk: meson8b: export the gate clock for the HW random number generator
clk: meson8b: export the SDIO clock
clk: meson8b: export the SAR ADC clocks
Some new clock units are supported, for the display clocks unsed in the
newer SoCs, and the A83T PRCM.
There is also a bunch of minor fixes for clocks that are not used by
anyone, and reworks needed by drivers that will land in 4.13.
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJZQY1YAAoJEBx+YmzsjxAgaqkQAIzXNo0oo/M+WWl2BiDBywQT
saAaquvpFBagelEYA7tN7hkVmbUdemZoYGSjK/FmOxWKDDGYuUphZboBiQ+UGdqf
5EMS0V+OLjA0EVviBIMm9g1hotPx/RJOyVHW1Whi4HwRwCRHbK7t2wZgZi1Df1+p
OPSeW+oPPEOOf8V4wI89sh2FXvqF/xY/dRUZKWA/GJNOia7tk3rxCTTA6TMl8W0M
hBQFMKqzIfruUMIgpKx305Rc5wpZbFz7Vc/XlZCwnmtr3UTHqaQp953LLm5VHUS5
EfbEibYRcy9ZBFLjciIJofyfO9V7mMrpkEqACG/C64gu4qbxi110mH6grUjGQtxC
CWStTtwVCHIl16dZe0e0WsxR/ZpXH/Q9DlHmshCGlQxz2d6YKqpimo5ZygIrw6uD
/TiFvqfoWowwGdI7ghA7FrRHHPW8HCiL7oEft+K06G4kgEo4YN74xI+xcyuAYDph
z/GLXgJVVOE34iFsd2rndYm857OsaEmyL1XG7NBbnW/g6U4OnhI3aC7JrrEqXdKu
iFMp80kWymoCujyWnabB7dKQbtuFxiqrCZ6OkqP+VE83Ux5JWQagumunhgr1OTUB
VJL4PVgaP5lCV74PtUmj/H1HaaQwWxr20xaHI2yOOmCxF7jlWbISjuQI1zb3lyKu
v9qczQNze3OiLPY14RpW
=41iN
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock patches from Maxime Ripard:
Some new clock units are supported, for the display clocks unsed in the
newer SoCs, and the A83T PRCM.
There is also a bunch of minor fixes for clocks that are not used by
anyone, and reworks needed by drivers that will land in 4.13.
* tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits)
clk: sunxi-ng: Move all clock types to a library
clk: sunxi-ng: a83t: Add support for A83T's PRCM
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM
clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t
clk: sunxi-ng: a83t: Fix audio PLL divider offset
clk: sunxi-ng: a83t: Fix PLL lock status register offset
clk: sunxi-ng: Add driver for A83T CCU
clk: sunxi-ng: Support multiple variable pre-dividers
dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU
clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()
clk: sunxi-ng: sun5i: Export video PLLs
clk: sunxi-ng: mux: Re-adjust parent rate
clk: sunxi-ng: mux: Change pre-divider application function prototype
clk: sunxi-ng: mux: split out the pre-divider computation code
clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
clk: sunxi-ng: div: Switch to divider_round_rate
clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
clk: divider: Make divider_round_rate take the parent clock
clk: sunxi-ng: explicitly include linux/spinlock.h
clk: sunxi-ng: add support for DE2 CCU
...
Remove the FIXME on clk81 mux and add all the documented parents
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Add data for omap4 clkctrl clocks, and register it within the clkctrl
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Previously, hwmod core has been used for controlling the hwmod level
clocks directly. This has certain drawbacks, like being unable to share
the clocks for multiple users, missing usecounting and generally being
totally incompatible with the common clock framework.
This patch adds support for clkctrl clocks for addressing the above
issues. These support the modulemode handling, which will replace the
direct hwmod clkctrl linkage. Any optional clocks are also supported,
gate, mux and divider.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Some fixes that fix some bindings that went in 4.12, fix a few reset and
clock offsets and a build error fix
-----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJZQYutAAoJEBx+YmzsjxAglWMQALkuMBskgMNE78L9M3kgNoOs
e44VWQLI0K0fOHyrnG1Y8wGy8pzTFXVhk13M8eJM9ELeVwN2hnwplcwooxt/I/Og
9B95qjDFSD4yTsE0SdcyT2KB6NXX6qrh/Wv5Q4ixi1vr09DGZ52jdbug+h0fLZxM
e1akTgv6oIQRdr1S4WykxnDDhNvooNV9Qgn4zKObwP2euTuRlllhPt+dj8rvgJzh
z23m6b296MbYh0hb2t0uqocQwkyOVHa9rtdCTVJFPaOeb+kjxl5NuFZzG/hrBRUm
+LbXwy0acst5SAdDDPGEYTnxyREB+vVYKF22i2+jSf3vTxRWZrZQkPlSs+0LtMLZ
LtLPUIdwFWdps/kY1IFjt0UeBw6mnv3LCv1dSciazRZDKexvzrWaNEZ942oS0Iqw
N7tltUEf4UJFZsgCY+yY+C4WL0QXsWtmVKFJDYtr2/yhgC1SpDNZP20DomwVMZ6G
i7SP+5uyCf7TNRXvckTfz3q0747f1V0yD9a0vR/cR5+TCmKChLIUava95/07qvy8
+AbSz9g2n7sKZTn+z3UUDuln9XTXGcy29SXigSXneeiFV1tjHUssZueLPvb/4EA9
LlNMr2JWG7Ois6H655512K6fvMUlqNvWpbdfnB45raPLU7AGa1xc95QXo7fMcfo/
6wxUN+7nhPDO8AXZmc7w
=G33o
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Allwinner clock fixes for 4.12
Some fixes that fix some bindings that went in 4.12, fix a few reset and
clock offsets and a build error fix
* tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM
clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM
dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks
clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM
clk: sunxi-ng: v3s: Fix usb otg device reset bit
clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
- conversion to the clk_hw API
- definitions and fixes of exynos5420 SoC audio subsystem
related clocks
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJZOpzhAAoJEE1bIKeAnHqLPFsP/jh9z5A1eq+rlB3ivWW8OByi
4iANs6Gd9Tnw7MNF46XV6qPHmj+9cEe1ntT/6lVs9Hlz67HwEnWuMc8dgtU6YU7d
A7Vzx+fMpE/UwFISLhqMjn5Djh13KP4wuPYiHaJKS+00JNEfT/IsvL6kZPS5I2bZ
teoeWzD1vOnn8QXxSnJeCCkmS91zVq5Sxyrge9Lui0gLMN+5wVxY1VTiw7erL9hi
jDL6qSRvcJfG1lruGD9No5MkI0kBXiVgqMHi1b2mTYnUS2NUQeAhCfGsvkO71ZU7
YjDSAOHYTccIdWHs6X4aIvzeVLjuHMVsnnXErDjI388POOQ3BCQ0JE2FDkp68UrM
DNGQFaKE528mxOL819aH71JQ5qj1kB9Upq7NUSC6roPbahiPv1tdx9dzX2vgGslM
pW+lXR6ysnsEYsE8HsCsOti4jpVSG6iWYyffI6GMGHVqRiDUY9d6cxHgj/Qx3YFR
9a7QmehnmSSzJK9sC1acD6e/U1YhcZYKMmb4ygtjFP/w2N2pwNXTgEw74UmXS/Mg
/ydVbcwJh6spaN85wXKer5lrZNio+gHDj4B+Vwnfo8yB2GW2akHYGW5cNkGeGac6
7ysI0wp7l9AuofzmovtiPw0pvz0p41rJO2LvIOvvsGeo6i5OOZBke7aAxe7lfg8G
hoXF2gS+r0wg/C3ljj4z
=2bgV
-----END PGP SIGNATURE-----
Merge tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next
Pull samsung clk driver updates from Sylwester Nawrocki
- conversion to the clk_hw API
- definitions and fixes of exynos5420 SoC audio subsystem
related clocks
* tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: exynos542x: Add EPLL rate table
clk: samsung: Add missing exynos5420 audio related clocks
clk: samsung: Add enable/disable operation for PLL36XX clocks
clk: samsung: s5pv210-audss: Convert to the new clk_hw API
clk: samsung: exynos-clkout: Convert to the new clk_hw API
clk: samsung: exynos-audss: Convert to the new clk_hw API
clk: samsung: Convert common drivers to the new clk_hw API
clk: samsung: Add local variable to match its purpose
clk: samsung: Remove dead code
table and the usual bunch of some new clock-ids and some clocks marked as
critical.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlk5xMgQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgQhdCACyqXbTUEGQDaqKa40f0IPOQCPZ31XYuz8t
3kQRV08ZkBQlI0tAKgxS4+tTERtpWBA3PjIlnZQ/VRogQsiJpWj6//98Z8jJ9oEx
2lsKTw3XAb/BVsvW4Awi7VbStt5LNxRxwuIU4uXgHaapTi7wQrqAlam+2iXNOW7h
05/piVKlKOyS52009UeiO3bzFojiTlElC1JQPqnVA65KxqhYvb/9rt3hn8Y8ZqF1
KuLibE/AC5eDX7XaCFe+a7dbJpA6b+ciHg24jk+BMuksy53yYbngLbDwlOs7YFjo
PjFgbdsJw25uE2i0ZwtarAOJoLOtBJiSNib6FJCmC6yHLy5Sc8l/
=kKnC
-----END PGP SIGNATURE-----
Merge tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk
table and the usual bunch of some new clock-ids and some clocks marked as
critical.
* tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: mark some special clk as critical on rk3368
clk: rockchip: mark noc and some special clk as critical on rk3288
clk: rockchip: mark noc and some special clk as critical on rk3228
clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036
clk: rockchip: add clock controller for rk3128
dt-bindings: add bindings for rk3128 clock controller
clk: rockchip: export more rk3228 clocks ids
clk: rockchip: add ids for rk3399 testclks used for camera handling
clk: rockchip: add dt-binding header for rk3128
clk: rockchip: fix up the RK3228 clk cpu setting table
clk: rockchip: add clock-ids for more rk3228 clocks
clk: rockchip: add ids for camera on rk3399
In K2G, the clock handling is done through firmware executing on a
separate core. Linux kernel needs to communicate to the firmware
through TI system control interface to access any power management
related resources, including clocks.
The keystone sci-clk driver does this, by communicating to the
firmware through the TI SCI driver. The driver adds support for
registering clocks through DT, and basic required clock operations
like prepare/get_rate, etc.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Make ti_sci_init_clocks() static]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The clock controller on Meson8, Meson8b and Meson8m2 is very similar
based on the code from the Amlogic GPL kernel sources. Add separate
compatibles for each SoC to make sure that we can easily implement
all the small differences for each SoC later on.
In general the Meson8 and Meson8m2 seem to be almost identical as they
even share the same mach-meson8 directory in Amlogic's GPL kernel
sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar,
because they are all using the same PLL values, 90% of the clock gates
are the same (the actual diffstat of the mach-meson8/clock.c and
mach-meson8b/clock.c files is around 30 to 40 lines, when excluding
all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3,
CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead
of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or
on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL
kernel sources)
None of these gates is added for now, since it's unclear whether these
definitions are actually correct (the VCLK2_ENCT gate for example is
defined, but only used in some commented block).
The main difference between all three SoCs seem to be the video (VPU)
clocks. Apart from different supported clock rates (according to vpu.c
in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the
most notable difference is that Meson8m2 has a GP_PLL clock and a mux
(probably the same as on the Meson GX SoCs) to support glitch-free
(clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b
clock driver yet though.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Export the ethernet gate clock to the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Export the USB related clocks (for the USB controller and the USB2 PHYs)
so they can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This exports the clock so it can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Export the SDIO clock so it can be used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Export the clocks for the SAR ADC so they can be used in the
dt-bindings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
A specific clock rate table is added for EPLL so it is possible
to set frequency of the EPLL output clock as multiple of various
audio sampling rates.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds missing definitions of mux clocks required for using
EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
The existing enable/disable ops for PLL35XX are made more generic
and used also for PLL36XX. This fixes issues in the kernel with
PLL36XX PLLs when the PLL has not been already enabled by bootloader.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Clock providers should use the new struct clk_hw based API, so convert
Samsung S5PV210 Audio Subsystem clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Clock providers should use the new struct clk_hw based API, so convert
Exynos CLKOUT clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Clock providers should use the new struct clk_hw based API, so convert
Exynos Audio Subsystem clock provider to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Clock providers should use the new struct clk_hw based API, so convert
Samsung clock providers and their helper functions to the new approach.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Add new variable to avoid using clk pointer for different purposes across
the exynos_register_cpu_clock() function. This will help in future rewrite
for the new clk_hw API.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
samsung_clk_register_pll2550x() function is not used anymore,
so remove its declaration.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
We've run into kconfig missing dependency errors in the sunxi-ng
code a couple times now. Each time the fix is to find the missing
select statement and add it to the Kconfig entry for a particular
SoC driver. Given that all this code is builtin (non-modular) we
don't need to do this complicated dependency tracking in Kconfig.
Instead we can move all the "library"ish code to be compiled as
lib-y instead of obj-y, let the linker throw away unused code in
the resulting vmlinux, and drop all the Kconfig stuff we use to
track clock types.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[Maxime: added lib.a to obj-y, added the comment]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A83T's PRCM has the same set of clocks and resets as the A64.
However, a few dividers are different. And due to the lack of a low
speed 32.768 kHz oscillator, a few of the clock parents are different.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
We get a link error when CCU_MULT is not set with the
newly added driver:
drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.1+0x4): undefined reference to `ccu_mult_ops'
drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.3+0x4): undefined reference to `ccu_mult_ops'
Fixes: 46b492116666 ("clk: sunxi-ng: Add driver for A83T CCU")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The divider of the audio PLL has an offset of 1.
Fix this in the driver.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The offset for the PLL lock status register was incorrectly set to
0x208, which actually points to an unused register. The correct
register offset is 0x20c.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A83T clock control unit is a hybrid of some new style clock designs
from the A80, and old style layout from the other Allwinner SoCs.
Like the A80, the SoC does not have a low speed 32.768 kHz oscillator.
Unlike the A80, there is no clock input either. The only low speed clock
available is the internal oscillator which runs at around 16 MHz,
divided by 512, yielding a low speed clock around 31.250 kHz.
Also, the MMC2 module clock supports switching to a "new timing" mode.
This mode divides the clock output by half, and disables the CCU based
clock delays. The MMC controller must be configure to the same mode,
and then use its internal clock delays.
This driver does not support runtime switching of the timing modes.
Instead, the new timing mode is enforced at probe time. Consumers can
check which mode is active by trying to get the current phase delay
of the MMC2 phase clocks, which will return -ENOTSUPP if the new
timing mode is active.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.
As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
PTR_ERR should access the value just tested by IS_ERR, otherwise
the wrong error code will be returned.
Fixes: b0d9a4bd52bd ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The video PLLs are used directly by the HDMI controller. Export them so
that we can use them in our DT node.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Currently, the parent rate given back to the clock framework in our
request is the original parent rate we calculated before trying to round
the rate of our clock.
This works fine unless our clock also changes its parent rate, in which
case we will simply ignore that change and still use the previous parent
rate.
Create a new function to re-adjust the parent rate to take the pre-dividers
into account, and give that back to the clock framework.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The current function name is a bit confusing, and doesn't really allow to
create an explicit function to reverse the operation.
We also for now change the parent rate through a pointer, while we don't
return anything.
In order to be less confusing, and easier to use for downstream users,
change the function name to something hopefully clearer, and return the
adjusted rate instead of changing the pointer.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The pre-divider retrieval code was merged into the function to apply the
current pre-divider onto the parent clock rate so that we can use that
adjusted value to do our factors computation.
However, since we'll need to do the reverse operation, we need to split out
that code into a function that will be shared.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The current code only rely on the parent to change its rate in the case
where CLK_SET_RATE_PARENT is set.
However, some clock rates might be obtained only through a modification of
the parent and the clock divider. Just rely on the round rate of the clocks
to give us the best computation that might be achieved for a given rate.
round_rate functions now need to honor CLK_SET_RATE_PARENT, but either the
functions already do that if they modify the parent, or don't modify the
praents at all.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
divider_round_rate_parent already evaluates changing the parent rate if
CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's
just use it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The clocks might need to modify their parent clocks. In order to make that
possible, give them access to the parent clock being evaluated, and to a
pointer to the parent rate so that they can modify it if needed.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
So far, divider_round_rate only considers the parent clock returned by
clk_hw_get_parent.
This works fine on clocks that have a single parents, this doesn't work on
muxes, since we will only consider the first parent, while other parents
may totally be able to provide a better combination.
Clocks in that case cannot use divider_round_rate, so would have to come up
with a very similar logic to work around it. Instead of having to do
something like this, and duplicate that logic everywhere, create a
divider_round_rate parent to allow caller to give an additional parameter
for the parent clock to consider.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
ccu_reset.h and ccu_reset.c use spinlock_t and associated functions but
rely on implict inclusion of linux/spinlock.h which means that changes
in other headers could break the build. Thus, add an explicit include.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.
Add a sunxi-ng style driver for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Commit ad14972422 ("clk: imx7d: Fix the powerdown bit location
of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case.
Fix it accordingly to avoid a kernel hang.
Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The old RealView clock implementation is not used anymore
(nothing in the kernel calls realview_clk_init()) as we have
moved all clocks over to device tree. Delete it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Fractional clock dividers generate accurate average frequencies but
with jitter, particularly when the integer divisor is small.
Introduce a new metric of clock accuracy to penalise clocks with a good
average but worse jitter compared to clocks with an average which is no
better but with lower jitter. The metric is the ideal rate minus the
worse deviation from that ideal using the nearest integer divisors.
Use this metric for parent selection for clocks requiring low jitter
(currently just PCM).
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Restrict clock sources for the PCM peripheral to the oscillator and
PLLD_PER because other source may have varying rates or be switched off.
Prevent other sources from being selected by replacing their names in
the list of potential parents with dummy entries (entry index is
significant).
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
If a clock has the prediv flag set, both the integer and fractional
parts must be scaled when calculating the resulting frequency.
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This patch introduces the managed version of clk_bulk_get.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Anson Huang <anson.huang@nxp.com>
Cc: Robin Gong <yibin.gong@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: Octavian Purdila <octavian.purdila@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
These helper function allows drivers to get several clk consumers in
one operation. If any of the clk cannot be acquired then any clks
that were got will be put before returning to the caller.
This can relieve the driver owners' life who needs to handle many clocks,
as well as each clock error reporting.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Anson Huang <anson.huang@nxp.com>
Cc: Robin Gong <yibin.gong@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: Octavian Purdila <octavian.purdila@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
These can be marked as const * const.
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Expose more i2s and spdif output clocks
* Expose EE uart and SPICC gate clocks
* Remove cpu_clk from to gxbb
* Mark clk81 as critical on gxbb
* Add CEC EE clocks
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJZMYA7AAoJEAFRo5MEFpTROkYQAIil0GjmG8azaiGXFWZ3LMf1
NupLsoH6Xd3nBnUmFR0DIHcH8ZadK5Io0+hWSVG0xopJzQS7+HWr/CfgQzdSiAa1
VDRSBZcoEmTBgiMkXfzN56HgUW1fz/bkQ2vZavQFsRJznkH2/kR09uL+/4BAY41k
v4uYZwXLbEFfYEytFrHzppV43W2CnaMN1EH7GpKUvP3VldxpCt0yYAQZFS7k2wyJ
If44bKN7sGma8g4IxrcrJ3AnpvE+OyLQAYgMyC1jm5WdRyEfWjqMNj54YL4cyIpl
x6v+38oB5y39g7/k+YCvCugoY25DnVcdzCdtkAY8rWfoStOl9R67CVKshEIfG9WN
WfRFLGBoC5RINvMEffjWSGPaGms1Cuk0UNWBOFNGzjwbc6Gw3OYZ4oXq4oSz8vby
/GZcogEocizX343id/vX/6WZWz2Pp2hPzFi3OrqIB0xb2jrTFxZ2zqYOeEp/ChCx
5HHVOwfrkKTEw6vvGre7VcIBipZ/MYoTWVUO86cVOpj+QuK2wigsTjTQWU0dVh2w
JOOGfk+3nrLoKzPpRLHdicc3FYv038RJcV35UqPOVmOhUh7+lGkRBTgEZunLXJI4
6qLmT49OFgSqLtx4u2R92xIdZYRGq5ysmIutUkmw69quWcfytsj9rZALp+2TWf8i
02pZYwcKJbrwHwK+Eqkk
=8rsv
-----END PGP SIGNATURE-----
Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into clk-next
Pull Amlogic clock driver updates from Jerome Brunet:
* Expose more i2s and spdif output clocks
* Expose EE uart and SPICC gate clocks
* Remove cpu_clk from to gxbb
* Mark clk81 as critical on gxbb
* Add CEC EE clocks
* tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson:
clk: meson-gxbb: Add EE 32K Clock for CEC
clk: gxbb: remove CLK_IGNORE_UNUSED from clk81
clk: meson: meson8b: mark clk81 as critical
clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver
clk: meson-gxbb: un-export the CPU clock
clk: meson-gxbb: expose UART clocks
clk: meson-gxbb: expose SPICC gate
clk: meson-gxbb: expose spdif master clock
clk: meson-gxbb: expose i2s master clock
clk: meson-gxbb: expose spdif clock gates
Undo preparation of a clock source, if palmas_clks_init_configure is not
successful.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.
The ddrphy/ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,
The pmu_hclk_otg0 is Chip design defect, must be always on,
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them.
But this clks need enable,so make it as ignore_unused for now.
The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,
The pmu_hclk_otg0 is Chip design defect, must be always on,
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them.
But this clks need enable,so make it as critical.
The ddrupctl/ddrmon/ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,
The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.
All these non-noc/non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch
and bus IDLE(or pd on/off).
The software is not very good to solve this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
No driver to handle this clk yet, but chip design requiress for this clock
supplying the ddr controller to be always on.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the clock tree definition for the new rk3128 SoC.
And it also applies to the RK3126 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/
VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
clk_testout1 and clk_testout2 are used for camera handling, so add their ids.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
- Add more module clocks for R-Car H3 ES2.0 and M3-W,
- Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support
for module resets, which are not supported by the existing driver,
- Rework Kconfig and Makefile logic,
- Small fixes and cleanups.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZLAkIAAoJEEgEtLw/Ve77w5oP/0YMQEoE3+pntUYIMEr0Op4k
xdMgLWkEJ+sK2/hoKp7bMY4KSA7XZ3F6dRyn4oI0HCSvHgs79xv6BnxzYk9RzKmy
3ywwP5C9icqH6chQvIGQrXntAhijeJH5nsc3b/dIeRusC0g24sR1teUmknrN++VJ
P+3zMD8IKLTrhOJwqgNUpXa1WEqEQylb6dBjnzPiHT3PYUznB32BuylwZYhYbrhG
RMD1HOD9+WnpBZOVYn3ju5fSxxcUxJwj/pBplok6rKgFU50kJIaINCRRJHeUwmrS
BM/ufmf0o10bKFkvTUX6gqA/kNeOHTjwkq/OIrfVQLL7j3lKLTlXEVf10bUKnuk6
WhcfhAtEg9vGX7upusndkEaNaFn3j3MpvC8HhCJuKAujg8U3j1U4Ly/j8rgnKt1C
D0tPLCXloQlzzRvTOWX0hUyjO2xeKX3nv/e9i7GXoX11K3VoiLGtiWq6sqHnw+Us
T4TzRG0wMYhhfwCl4PkzHerpWvBFSpG0fv2yynY+sMSGd28P7kyrr3Jh0TfxYccM
3wgprqXxm+msnWFLkqf80U7lw6WgRdKuYb/Na5pUCEYuFNJTJssTj+Z2XVeOHPjT
EZa6WshVnvf06hEa5qLWM+jmlhcj1u4rWeA0aVvJ83IzP/s0ftLjdyIl96B2a8ll
G6Owe6OVfk/5MRvsxRzW
=29vW
-----END PGP SIGNATURE-----
Merge tag 'clk-renesas-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
clk: renesas: Updates for v4.13
- Add more module clocks for R-Car H3 ES2.0 and M3-W,
- Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support
for module resets, which are not supported by the existing driver,
- Rework Kconfig and Makefile logic,
- Small fixes and cleanups.
In preparation to the addition of a new clock, rename the goto labels
used to handle the failure cases using a name related to the failure
cause. This will allow to insert additional failing cases without
renaming all the labels.
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
When failing to set a clock the printout emitted is incorrect.
"u32 rate" is formatted as %d and should be %u whereas "unsigned long
clk_set_rate()" is formatted as %ld and should be %lu as per
Documentation/printk-formats.txt.
Fixes: 2885c3b2a3 ("clk: Show correct information when fail to set clock rate")
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The frequencies above the maximum value of signed integer(i.e. 2^31 -1)
will overflow with the current code.
This patch fixes the return type of __scpi_dvfs_round_rate from 'int'
to 'unsigned long'.
Fixes: cd52c2a4b5 ("clk: add support for clocks provided by SCP(System Control Processor)")
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
clk_generated_startup is called after clk_hw_register. So the first call to
get_parent will not have the correct value (i.e. 0) and because this is
cached, it may never be updated.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Fixes: df70aeef60 ("clk: at91: add generated clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
According to the MX7D Reference Manual the powerdown bit of
CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The Linksys WRT3200ACM CPU is clocked at 1866MHz. Add 1866MHz to the
list of supported CPU frequencies. Also update multiplier and divisor
for the l2clk and ddrclk.
Noticed by the following warning:
[ 0.000000] Selected CPU frequency (16) unsupported
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Martin Blumenstingl