Commit Graph

13 Commits

Author SHA1 Message Date
Joseph Lo a44a019d45 ARM: dts: tegra: add the PM configurations of PMC
Adding the PM configuration of PMC when the platform support suspend
function.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04 17:17:43 -06:00
Joseph Lo 7a2617a64d ARM: tegra: add non-removable and keep-power-in-suspend property for MMC
This patch adds "non-removable" property of MMC host where the eMMC device
is for Tegra platform.

And the "keep-power-in-suspend" property was used for the SDIO device that
need this to go into suspend mode (e.g. BRCM43xx series).

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04 17:17:43 -06:00
Stephen Warren f9cd2b3bf4 ARM: tegra: add clocks property to sound nodes
Audio-related clocks need to be represented in the device tree. Update
bindings to describe which clocks are needed, and DT files to include
those clocks.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04 17:17:42 -06:00
Joseph Lo 7021d12205 ARM: tegra: add clock source of PMC to device trees
Adding the bindings of the clock source of PMC in DT.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-03 14:29:56 -06:00
Joseph Lo 908ab93688 ARM: dts: tegra: fix the activate polarity of cd-gpio in mmc host
The GPIO pin of SD slot card detection should active low.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-11 14:25:10 -06:00
Olof Johansson 5b22c33e8e ARM: tegra: device tree updates
Numerous updates to the various Tegra device trees are made:
 
 * Addition of NVIDIA Beaver (Tegra30) and Toradex Colibri T20 and Iris
   carrier boards.
 * Enablement of the HDMI connector on most boards.
 * Enablement of the keyboard controller on a few boards.
 * Addition of the AC'97 controller to Tegra20.
 * Addition of a GPIO poweroff node for TrimSlice.
 * Changes to support the new "high speed UART" (DMA-capable) driver for
   Tegra serial ports, and enablement for Cardhu's UART C.
 * A few cleanups, such as compatible flag fixes, node renames, node
   ordering fixes, commonizing properties into SoC .dtsi files, etc..
 
 This pull request is based on (most of) the previous pull request with
 tag tegra-for-3.9-soc-t114.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJRCY++AAoJEMzrak5tbycx6BMQALRuxbStMPDVBmOp65kF8B/s
 u8wynnbL1qs6dJ81LW9IcVCEqzsR/7tfda9h4p+SPnihF4OxLMYyG95qzK0rR+ZR
 pA+yIhRQjEq4q4+TgvHNblpSGN1wguLVC/FmN7kpJlSI6IMQsK3iQmPEsUE4gSfK
 aaCwWaFuUUed7B6gpzJY6pX5C7H4EkwJZxOGBmr/houuoaEKz0vjGY8KaSwBd9RZ
 oACibtHbhvkkYY6LCkBHSWNHAcwpMZRw+b0SDQ5ephShPK4gMGC44lwTz4RFJawS
 pgZVYOUpb5OFivZFPKqXglCNe3PMwNgb9ntFm7UU//99ibQiGGB49oIkDL2HJx1g
 KKeyEOZLN+h0CbgxDu5p2ItCcID1Z5CzD/ryqE7ofFx1iQrUc7b0RsIlM9chUjei
 xumU5rQJRxwNIvyvYu+zvuV3J7luSe9W+2teXkvKccAwmr1YIbwQeFPGYgkchFOz
 efKhESGVaoUMKdVyg09nPkDRpM/NwHkxcPCga7ypOJl9oKU3B6t5mmMxI9+sUxet
 iYL50iDBoulHtBDlCFjYfjnq1Go9sCE+fXxGaWJ5Yec3qsB9zhHDE72hZ3NF1tWj
 3YWq5dhyAYz90N6RUhXBHfWvZ4a188Z3tPAUt3C/TUQ9dttzZqkRsCnu7A5nAKyN
 f9Ul9sK48KSub5+Zb7+7
 =UMMs
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt

From Stephen Warren:
ARM: tegra: device tree updates

Numerous updates to the various Tegra device trees are made:

* Addition of NVIDIA Beaver (Tegra30) and Toradex Colibri T20 and Iris
  carrier boards.
* Enablement of the HDMI connector on most boards.
* Enablement of the keyboard controller on a few boards.
* Addition of the AC'97 controller to Tegra20.
* Addition of a GPIO poweroff node for TrimSlice.
* Changes to support the new "high speed UART" (DMA-capable) driver for
  Tegra serial ports, and enablement for Cardhu's UART C.
* A few cleanups, such as compatible flag fixes, node renames, node
  ordering fixes, commonizing properties into SoC .dtsi files, etc..

This pull request is based on (most of) the previous pull request with
tag tegra-for-3.9-soc-t114.

* tag 'tegra-for-3.9-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (22 commits)
  ARM: dt: tegra30: Rename "smmu" to "iommu"
  ARM: dt: tegra20: Rename "gart" to "iommu"
  ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
  ARM: tegra: Add Toradex Iris carrier board DT with T20 512MB COM
  ARM: tegra: Add Colibri T20 512MB COM device tree
  ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
  ARM: tegra: harmony: enable keyboard in DT
  ARM: tegra: whistler: enable keyboard in DT
  ARM: tegra: cardhu: register UARTC
  ARM: tegra: seaboard: enable keyboard in DT
  ARM: tegra: add DT entry for KBC controller
  ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT
  ASoC: tegra: add ac97 host controller to device tree
  ARM: DT: tegra: Add Tegra30 Beaver board support
  ARM: DT: tegra: Add board level compatible properties
  ARM: tegra: paz00: enable HDMI port
  ARM: tegra: ventana: enable HDMI port
  ARM: tegra: seaboard: enable HDMI port
  ARM: tegra: trimslice: add gpio-poweroff node to DT
  ARM: DT: tegra: Unify the description of Tegra20 boards
  ...
2013-02-05 13:19:11 -08:00
Venu Byravarasu 40e8b3a690 ARM: tegra: Add reset GPIO information to PHY DT node
As reset GPIO information is PHY specific detail, adding
it to PHY DT node.

Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28 11:41:45 -07:00
Lucas Stach ab343e91aa ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28 11:24:09 -07:00
Stephen Warren 11a3c868f9 ARM: tegra: paz00: enable HDMI port
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28 11:24:07 -07:00
Prashant Gaikwad d409b3af89 ARM: tegra: paz00: add clock information to DT
Add clock i2c clock information to device node.

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28 11:19:33 -07:00
Stephen Warren b9c665d75b ARM: tegra: update *.dts for regulator-compatible deprecation
Commit 13511de "regulator: deprecate regulator-compatible DT property"
now allows for simpler content within the regulators node within a PMIC.
Modify all the Tegra device tree files to take advantage of this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
2012-11-05 11:36:04 -07:00
Stephen Warren 217b8f0f35 ARM: dt: tegra: paz00: add regulators
The Toshiba AC100/PAZ00 uses a TPS6586x regulator. Instantiate this.

Three data sources were used for the data encoded here:
* The HW defaults, as extracted from real HW.
* The schematic, which specifies a voltage for each rail in the signal
  names.
* The AC100 kernel used by the Ubuntu port:

  repo git://gitorious.org/~marvin24/ac100/marvin24s-kernel.git
  branch chromeos-ac100-3.0
  file arch/arm/mach-tegra/board-paz00-power.c

  For many rails, the constraints in that tree specified differing min
  and max voltages. In all cases, the min value was ignored, since
  there's no need currently to vary any of the voltages at run-time.
  DVFS might change this in the future.

In most cases these sources all matched. Differences are:

sm0: HW defaults and schematic match at 1.2v. marvin24's kernel had a max
of 1.3v, but this higher voltage was only applied to HW by DVFS code,
which isn't currently supported in mainline.

sm1: HW defaults and schematic match at 1.0v. marvin24's kernel had a max
of 1.125v, but this higher voltage was only applied to HW by DVFS code,
which isn't currently supported in mainline.

ldo3: The HW default is on. marvin24's kernel didn't specify always-on,
but since the board wasn't marked as having fully constrained regulators,
the rail was not turned off, so the difference had no effect. The rail
is needed for USB.

ldo6: The HW default is 2.85v. The schematics indicate 2.85v. However,
since this regulator is used for the same purpose as on other boards that
require 1.8v, this is set to 1.8v. Note that this regulator feeds the CRT
VDAC on Tegra, and so in practice is unlikely to be used, even though it
is actaully hooked up in HW.

Portions based on work by Laxman Dewangan <ldewangan@nvidia.com>

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Marc Dietrich <marvin24@gmx.de> # v2
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
2012-09-06 11:48:39 -06:00
Stephen Warren 702b0e4f2f ARM: dt: tegra: rename board files to match SoC
Most ARM ${board}.dts files are already named ${soc}-${board}.dts. This
change modifies the Tegra board files to be named the same way for
consistency.

Once a related change is made in U-Boot, this will cause both U-Boot and
the kernel to use the same names for the .dts files and SoC identifiers,
thus allowing U-Boot's recently added "soc" and "board" environment
variables to be used to construct the name of Tegra .dtb files, and hence
allow board-generic U-Boot bootcmd scripts to be written.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-20 12:30:10 -06:00