Commit Graph

15 Commits

Author SHA1 Message Date
Jernej Skrabec 2d2b61c13a
clk: sunxi-ng: Add check for minimal rate to NM PLLs
Some NM PLLs doesn't work well when their output clock rate is set below
certain rate.

Add support for that constrain.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-02 08:42:14 +01:00
Chen-Yu Tsai 7d333ef1cc clk: sunxi-ng: Support fixed post-dividers on NM style clocks
On the A83T, the audio PLL should have its div1 set to 0, or /1, and
div2 set to 1, or /2. This setting is the default, and is required
to match the sigma-delta modulation parameters from the BSP kernel.

To do this, we first add fixed post-divider to the NM style clocks,
which is the type of clock the audio PLL clock is modeled into.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-12-08 10:08:07 +01:00
Chen-Yu Tsai 392ba5fafc clk: sunxi-ng: nm: Add support for sigma-delta modulation
Some of the N-M-style clocks, namely the PLLs, support sigma-delta
modulation to do fractional-N frequency synthesis. This is used in
the audio PLL to generate the exact frequency the audio blocks need.
These frequencies can not be generated with integer N-M factors.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-13 09:27:13 +02:00
Chen-Yu Tsai 4cdbc40d64 clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock
The round_rate callback for N-M-factor style clocks does not check if
the requested clock rate is supported by the fractional clock mode.
While this doesn't affect usage in practice, since the clock rates
are also supported through N-M factors, it does not match the set_rate
code.

Add a check to the round_rate callback so it matches the set_rate
callback.

Fixes: 6174a1e24b ("clk: sunxi-ng: Add N-M-factor clock support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-10-13 09:27:00 +02:00
Jernej Škrabec 1d42460a49 clk: sunxi-ng: Wait for lock when using fractional mode
Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be
set before returning. Because of that, unstable clock may be used.

Add a wait for lock in the helper function.

Fixes: 89a3dfb787 ("clk: sunxi-ng: Add fractional lib")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-01 10:18:23 +08:00
Jernej Škrabec b64dfec010 clk: sunxi-ng: Fix fractional mode for N-M clocks
N-M factor clock driver is missing a call to ccu_frac_helper_enable()
when fractional mode is used. Additionally, most SoCs require that M
factor must be set to 0 when fractional mode is used.

Without this patch, clock keeps the old value and clk_set_rate() returns
without error.

Fixes: 6174a1e24b ("clk: sunxi-ng: Add N-M-factor clock support")
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-08-01 10:18:21 +08:00
Chen-Yu Tsai 95ad8ed9c8 clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch
In commit 2beaa601c8 ("clk: sunxi-ng: Implement minimum for
multipliers"), the multiplier minimums in the set_rate callback
for NM and NKMP style clocks were not updated.

This patch fixes them to match their round_rate callbacks.

Fixes: 2beaa601c8 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-13 14:09:28 +02:00
Chen-Yu Tsai 4162c5ce52 clk: sunxi-ng: use 1 as fallback for minimum multiplier
A zero multiplier does not make sense for clocks.

Use 1 as the minimum when a multiplier minimum isn't specified.

Fixes: 2beaa601c8 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-13 14:09:25 +02:00
Maxime Ripard 0c3c8e1358 clk: sunxi-ng: Implement multiplier maximum
Some multipliers have a maximum rate that is lower than what the register
width allows to. Add a field in the multiplier structure to allow CCU
driver to set that maximum.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-23 11:45:01 +01:00
Maxime Ripard e66f81bbd7 clk: sunxi-ng: Implement factors offsets
The factors we've seen so far all had an offset of one. However, on the
earlier Allwinner SoCs, some factors could have no offset at all, meaning
that the value computed to reach the rate we want to use was the one we had
to program in the registers.

Implement an additional field for the factors that can have such an offset
(linears, not based on a power of two) to specify that offset.

This offset is not linked to the extremums that can be specified in those
structures too. The minimum and maximum are representing the range of
values we can use to try to compute the best rate. The offset comes later
on when we want to set the best value in the registers.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-23 11:44:27 +01:00
Maxime Ripard 2beaa601c8 clk: sunxi-ng: Implement minimum for multipliers
Allow the CCU drivers to specify a multiplier for their clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-10-25 12:40:25 +02:00
Maxime Ripard 6e0d50daa9 clk: sunxi-ng: Add minimums for all the relevant structures and clocks
Modify the current clocks we have to be able to specify the minimum for
each clocks we support, just like we support the max.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-10-25 12:40:23 +02:00
Maxime Ripard ee28648cb2 clk: sunxi-ng: Remove the use of rational computations
While the rational library works great, it doesn't really allow us to add
more constraints, like the minimum.

Remove that in order to be able to deal with the constraints we'll need.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-10-25 12:39:25 +02:00
Maxime Ripard 87ba9e5962 clk: sunxi-ng: div: Allow to set a maximum
Some dividers might have a maximum value that is lower than the width of
the register.

Add a field to _ccu_div to handle those case properly. If the field is set
to 0, the code will assume that the maximum value is the maximum one that
can be used with the field register width.

Otherwise, we'll use whatever value has been set.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-09-10 11:41:18 +02:00
Maxime Ripard 6174a1e24b clk: sunxi-ng: Add N-M-factor clock support
Introduce support for clocks that multiply and divide using linear factors.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-11-maxime.ripard@free-electrons.com
2016-07-08 18:05:00 -07:00