Commit Graph

8 Commits

Author SHA1 Message Date
Jeeja KP 399b210bef ASoC: Intel: Skylake: Add helper routine to handle Algo parameter
Some DSP modules has user configurable parameters, which are
required by some modules at module initialization.

To configure the module algorithm parameter during initialization
we add helpers here

Signed-off-by: Divya Prakash <divya1.prakash@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-01 22:17:00 +00:00
Hardik T Shah 65aecfa884 ASoC: Intel: Skylake: Add support for module GUIDs
The DSP FW specifies loadable modules using GUIDs so add support to
specify the GUIDs from topology

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Omair M Abdullah <omair.m.abdullah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-16 10:08:09 +00:00
Hardik T Shah 04afbbbb1c ASoC: Intel: Skylake: Update the topology interface structure
This patch updates the topology interface structure alignment and
also updates the Sample interleaving defines

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Omair M Abdullah <omair.m.abdullah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-16 10:08:09 +00:00
Hardik T Shah 4cd9899f0d ASoC: Intel: Skylake: Add multiple pin formats
The module pin formats are considered homogeneous, but some
modules can have different pcm formats on different pins, like
reference signal for a module.

This patch add support for configuration of each pin of module
and allows us to specify if pins and homogeneous or heterogeneous

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Omair M Abdullah <omair.m.abdullah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-16 10:08:09 +00:00
Jeeja KP 6abca1d71b ASoC: Intel: Skylake: Add support to topology for module static pin
Some module pin connection are static and defined by the topology.
This patch adds support for static pin definitions in topology widget
private data

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-24 01:31:34 +09:00
Jeeja KP bfa764accd ASoC: Intel: Skylake: Fix to set Non gateway copier cfg
If copier instance is connected to a DMA gateway then driver
needs to configure the gateway configuration otherwise set
it to invalid.
This patch sets the non gateway copier node value to invalid.

Signed-off-by: Dharageswari.R <dharageswari.r@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-24 01:31:34 +09:00
Vinod Koul 3af36706ff ASoC: Intel: Skylake: Add topology core init and handlers
The SKL driver does not code DSP topology in driver. It uses the
newly added ASoC topology core to parse the topology information
(controls, widgets and map) from topology binary.
Each topology element passed private data which contains
information that driver used to identify the module instance
within firmware and send IPCs for that module to DSP firmware
along with parameters.
This patch adds init routine to invoke topology load and callback
for topology creation.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-07 16:04:14 +01:00
Jeeja KP 23db472bba ASoC: Intel: Skylake: Add helpers for DSP module configuration
This adds helper functions to calculate parameters required for base module
format and copier module. A generic module is modelled by base module.
Copier module is responsible for getting/sending data to FE (host DMAs) and
BE (link HDA DMA, SSP, PDM)
This also ads module pin management helpers which help in finding pins to
use or freeing them up

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-07 14:26:02 +01:00