3 Commits

Author	SHA1	Message	Date
Victor Kamensky	edfaf05c2f	ARM: OMAP2+: raw read and write endian fix ... All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>	2014-05-08 07:09:53 -07:00
Sanjeev Premi	4f288f081b	ARM: OMAP2+: AM43x: SRAM base and size ... This definition corresponds to the L3_OCMC0, as in case of AM33XX. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> [tony@atomide.com: updated to remove default y] Signed-off-by: Tony Lindgren <tony@atomide.com>	2013-06-12 08:07:23 -07:00
Tony Lindgren	bb77209432	ARM: OMAP: Move omap2+ specific parts of sram.c to mach-omap2 ... Let's make the omap2+ specific parts private to mach-omap2. This leaves just a minimal shared code into plat-omap like it should be. Signed-off-by: Tony Lindgren <tony@atomide.com>	2012-10-31 10:14:14 -07:00