The exynos5800 is very similar to exynos5420. We can re-use
the existing MCPM support for exynos5800 for secondary boot
-up and switching.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This makes it possible to enable the Exynos platform as part of a
multiplatform kernel.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Instead of repeating the Kconfig entries for every SoC,
move them under ARCH_EXYNOS3, 4 and 5 and move the entries
common to 3, 4 and 5 under ARCH_EXYNOS.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch fix the offset of CPU boot address and don't
need to send smc call of SMC_CMD_CPU1BOOT command for
secondary CPU boot because Exynos3250 removes WFE in
secure mode.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch add Exynos3250's SoC ID. Exynos 3250 is SoC that
is based on the 32-bit RISC processor for Smartphone.
Exynos3250 uses Cortex-A7 dual cores and has a target speed
of 1.0GHz.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos5800 is an octa core SoC which is based on the 5420
platform. This patch adds the basic support for it in the
mach-exynos.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch add basic arch side support for exynos5260 SoC.
Note that this is required to enable build for clock driver.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch add pmusysreg node for Exynos3250 to access PMU
(Power Management Unit) register in a centralized way using
syscon driver.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The vbus-supply property is wrongly updated in the
usbdrd node instead of the usbdrd_phy node. This patch
fixes the same.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The vbus-supply property is wrongly updated in the
usbdrd node instead of the usbdrd_phy node. This patch
fixes the same.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds new exynos3250.dtsi to support Exynos3250 SoC
based on Cortex-A7 dual core and includes following dt nodes:
- GIC interrupt controller
- Pinctrl to control GPIOs
- Clock controller
- CPU information (Cortex-A7 dual core)
- UART to support serial port
- MCT (Multi Core Timer)
- ADC (Analog Digital Converter)
- I2C/SPI bus
- Power domain
- PMU (Performance Monitoring Unit)
- MSHC (Mobile Storage Host Controller)
- PWM (Pluse Width Modulation)
- AMBA bus
- sysram node for SYSRAM memory mapping
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Hyunhee Kim <hyunhee.kim@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: devicetree@vger.kernel.org
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add required fixed-regulator for VBUS supply for USB 3.0
controller phy.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable display controller with timing information for 1080p
panel in Exynos5800 peach-pi board.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Adds support for google peach-pi board having the
Exynos5800 SoC.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Most of the nodes of exynos5420 remains same for exynos5800.
So the exynos5420.dtsi is included in exynos5800 and the changed
node properties will be overriden.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The patch adds the dts file for xyref5260 board which
is based on exynos5260 SoC.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Made it as per DT node naming convention <name@reg_addr>.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Key code macros improve readability on exnos4210-origen,
exynos4412-origen and exynos5250-arndale boards.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
[kgene.kim@samsung.com: squashed similar two patches]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enabled RTC and WDT nodes on exynos4210-origen and
exynos4412-origen boards.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
[kgene.kim@samsung.com: squashed similar two patches]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Call pcie_bus_configure_settings() on ARM, like for other platforms.
pcie_bus_configure_settings() makes sure the MPS across the bus is uniform
and provides the ability to tune the MRSS and MPS to higher performance
values. This is particularly important for embedded where there is no
firmware to program these PCIe settings for the OS.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
This corrects a bug that will be introduced in v3.15.
The bug causes audio playback to fail on the Armadillo800 EVA board.
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Merge tag 'renesas-fixes-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/fixes-non-critical
Merge "Renesas ARM Based SoC Fixes for v3.16" from Simon Horman:
This corrects a bug that will be introduced in v3.15.
The bug causes audio playback to fail on the Armadillo800 EVA board.
* tag 'renesas-fixes-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: armadillo800eva: fixup HDMI sound flags setting
Signed-off-by: Olof Johansson <olof@lixom.net>
Pull ARM fixes from Russell King:
"The usual random collection of relatively small ARM fixes"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 8063/1: bL_switcher: fix individual online status reporting of removed CPUs
ARM: 8064/1: fix v7-M signal return
ARM: 8057/1: amba: Add Qualcomm vendor ID.
ARM: 8052/1: unwind: Fix handling of "Pop r4-r[4+nnn],r14" opcode
ARM: 8051/1: put_user: fix possible data corruption in put_user
ARM: 8048/1: fix v7-M setup stack location
When configure kprobe events of ftrace with "stacktrace" option enabled
in arm, there is no stacktrace was recorded after the kprobe event was
triggered. The root cause is no save_stack_trace_regs() function implemented.
Implement the save_stack_trace_regs() function in arm, then ftrace will
call this architecture-related function to record the stacktrace into
ring buffer.
After this fix, stacktrace can be recorded, for example:
# mount -t debugfs nodev /sys/kernel/debug
# echo "p:netrx net_rx_action" >> /sys/kernel/debug/tracing/kprobe_events
# echo 1 > /sys/kernel/debug/tracing/events/kprobes/netrx/enable
# echo 1 > /sys/kernel/debug/tracing/options/stacktrace
# echo 1 > /sys/kernel/debug/tracing/tracing_on
# ping 127.0.0.1 -c 1
# echo 0 > /sys/kernel/debug/tracing/tracing_on
# cat /sys/kernel/debug/tracing/trace
# tracer: nop
#
# entries-in-buffer/entries-written: 12/12 #P:1
#
# _-----=> irqs-off
# / _----=> need-resched
# | / _---=> hardirq/softirq
# || / _--=> preempt-depth
# ||| / delay
# TASK-PID CPU# |||| TIMESTAMP FUNCTION
# | | | |||| | |
<------ missing some entries ---------------->
ping-1200 [000] dNs1 667.603250: netrx: (net_rx_action+0x0/0x1f8)
ping-1200 [000] dNs1 667.604738: <stack trace>
=> net_rx_action
=> do_softirq
=> local_bh_enable
=> ip_finish_output
=> ip_output
=> ip_local_out
=> ip_send_skb
=> ip_push_pending_frames
=> raw_sendmsg
=> inet_sendmsg
=> sock_sendmsg
=> SyS_sendto
=> ret_fast_syscall
Signed-off-by: Lin Yongting <linyongting@gmail.com>
Acked-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Support for ARM710 CPUs was removed in v3.5. Now remove the last code
depending on its Kconfig macro.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We will reach fixup handler when one thread(say cpu0) caused an undefined exception, while another thread(say cpu1) is unmmaping the page.
Fixup handler returns to the next userspace instruction which has caused the undef execption, rather than going to the same instruction.
ARM ARM says that after undefined exception, the PC will be pointing
to the next instruction. ie +4 offset in case of ARM and +2 in case of Thumb
And there is no correction offset passed to vector_stub in case of
undef exception.
File: arch/arm/kernel/entry-armv.S +1085
vector_stub und, UND_MODE
During an undefined exception, in normal scenario(ie when ldrt
instruction does not cause an abort) after resorting the context in
VFP hardware, the PC is modified as show below before jumping to
ret_from_exception which is in r9.
File: arch/arm/vfp/vfphw.S +169
@ The context stored in the VFP hardware is up to date with this thread
vfp_hw_state_valid:
tst r1, #FPEXC_EX
bne process_exception @ might as well handle the pending
@ exception before retrying branch
@ out before setting an FPEXC that
@ stops us reading stuff
VFPFMXR FPEXC, r1 @ Restore FPEXC last
sub r2, r2, #4 @ Retry current instruction - if Thumb
str r2, [sp, #S_PC] @ mode it's two 16-bit instructions,
@ else it's one 32-bit instruction, so
@ always subtract 4 from the following
@ instruction address.
But if ldrt results in an abort, we reach the fixup handler and return
to ret_from_execption without correcting the pc.
This patch modifes the fixup handler to re-execute the same instruction which caused undefined execption.
Signed-off-by: Vinayak Menon <vinayakm.list@gmail.com>
Signed-off-by: Arun KS <getarunks@gmail.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
asm-generic offers an atomic-add based rwsem implementation, which
can avoid the need for heavier, spinlock-based synchronisation on the
fast path.
This patch makes use of the optimised implementation for ARM CPUs.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
As we have now removed all instances of the L2C-310 having its cache
size "modified" via platform/SoC code, discourage new cases showing
up by printing a warning.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We no longer need or require the .set_debug method; we handle everything
it used to do via the .write_sec method instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
L2X0_AUX_CTRL_MASK is not useful for PL310s. It would be better if
people thought about their value for this rather than cargo-cult
programming.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
It is beneficial to have the L2 cache up and running earlier in the
system boot. Not only will this allow for simpler code when we come to
enable some features, but it also means that we get a more accurate
bogomips value for the udelay() loop. Calibrating the loop with the
L2 cache off, and then running with the L2 cache on is not the best
idea.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ux500 can't change the auxiliary control register, so there's no point
passing values to try and modify it to the l2x0 init functions.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ux500 can't write to any of the secure registers on the L2C controllers,
so provide a dummy handler which ignores all writes.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. We can remove the .init_machine as it becomes
the same as the generic version.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. This also allows us to eliminate the
.init_machine function as this becomes the same as the generic version.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add better commentry about the L2 cache requirements on these platforms.
Unfortunately, the auxiliary control register is not pre-set to indicate
the correct cache parameters, so we have to manually program these.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. Along with this change, we can delete l2x0.c
from prima2.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add support for L2 cache controller (PL310) on AM437x SoC.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Get rid of init call to initialize L2 cache. Instead use the init_early
machine hook. This helps in using the initialization routine across
SoCs without the need of ugly cpu_is_*() checks.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
L2 cache initialization for OMAP4 redundantly sets the cache policy to
Round-Robin. This is not needed since thats the PL310 default anyway.
Removing this reduces the number of platform specific aux control
settings.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Avoid reading directly from the L2 registers in platform code. The L2
code will have already saved the register values itself into the
l2x0_saved_regs structure, so platform code should just move these
values to where they're required.
This is safe because the L2x0 will have been initialised by an early
initcall, whereas the OMAP4 PM code is initialised late.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since we now always enable NS access to the unlock registers, this can
be removed from OMAP4. Remove the NS access bit for the interrupt
registers from OMAP4 as well - nothing in the kernel accesses that yet,
and we can add it in core code when we have the need.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that OMAP2 uses the write_sec method, we don't need to enable the L2
cache in OMAP2 specific code; this can be done via the normal mechanisms
in the L2C code. Remove the OMAP2 specific code.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With the write_sec method, we no longer need to override the default
L2C disable method, and we no longer need the L2C set_debug method.
Both of these can be handled via the write_sec method.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. This also allows us to eliminate the
.init_machine function as it is identical to the generic version.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. Since the .init_irq method only calls
irqchip_init(), we can remove that too as the generic code will take
care of that.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that we handle this in core code, we don't need platforms enabling
the low power modes directly.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that highbank uses the write_sec method, we don't need to enable
the L2 cache in SoC specific code; this can be done via the normal
mechanisms in the L2C code.
Checking with Rob Herring:
> > Can we kill the "highbank_smc1(0x102, 0x1);" here? That means
> > l2x0_of_init() will see the L2 cache disabled, and will try to enable
> > it via the write_sec hook, so it should do the right thing.
>
> Yes, that should work. You should be able to just call l2x0_of_init
> unconditionally. The condition was really to just avoid the smc on
> Midway which does get handled on h/w, but not if running virtualized.
So also drop the DT check too. I'm leaving the config check in place
so that if L2 is disabled, the write_sec hook can be optimised away.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With the write_sec method, we no longer need to override the default L2C
disable method. This can be handled via the write_sec method instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
exynos was unconditionally calling the L2 cache initialisation from an
early_initcall. This breaks multiplatform kernels. Thankfully,
converting to generic l2c initialisation fixes this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP. Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code. Remove them so we can find out which really need
this.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. We can remove the explicit machine init too
as this becomes identical to the generic version.
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. We can remove the explicit machine init too
as this becomes identical to the generic version.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Provide a common assembly implementation for PL310 resume code. Certain
platforms need to re-initialise the L2C cache early as it may preserve
data across a S2RAM cycle, and therefore must be enabled along with the
L1 cache and MMU.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add a hook into the core ARM code to perform L2 cache initialisation
in a platform independent manner. Platforms still get to indicate
their auxiliary control register values and mask, but the
initialisation call will now be made from generic code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since we always write to these during the cache initialisation, it is
a good idea to always have the non-secure access bit set. Set it in
core code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly. Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted. Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.
Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the L2 cache register saving to a more sensible location - after
the cache has been enabled, and fixups have been run. We move the
saving of the auxiliary control register into the ->save function as
well which makes everything operate in a sane and maintainable way.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess. Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices. Provide full auxiliary control register definitions.
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than having SoCs work around L2C erratum themselves, move them
into core code. This erratum affects the double linefill feature which
needs to be disabled for r3p0 to r3p1-50rel0.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort. Platforms normally have to call
firmware to work around this. Provide a hook for them to intercept
any L2C secure register write.
l2c_write_sec() avoids writes to secure registers which are already set
to the appropriate value, thus avoiding the overhead of needlessly
calling into the secure monitor.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the L2C-310 errata configuration options to arch/arm/mm/Kconfig
along side the option which enables support for this device.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the way size calculation data (base of way size) out of the
switch statement into the provided initialisation data.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than assuming these are always 8-way, it can be decoded from the
auxillary register in the same manner as L2C-210.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than decoding this from the ID register, store it in the
l2c_init_data structure. This simplifies things some more, and
allows us to better provide further details as to how we're
driving the cache. We print the cache ID value anyway should we
need to precisely identify the cache hardware.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
non-OF initialisation has never been used with any cache controller
which isn't an ARM cache controller, so we can safely get rid of the
old (and buggy) l2x0_*-based operations structure.
This is also the last reference to:
- l2x0_clean_line()
- l2x0_inv_line()
- l2x0_flush_line()
- l2x0_flush_all()
- l2x0_clean_all()
- l2x0_inv_all()
- l2x0_inv_range()
- l2x0_clean_range()
- l2x0_flush_range()
- l2x0_enable()
- l2x0_resume()
so kill those functions too.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later. These
require no errata workarounds, and so we can directly call the l2c210
functions from their methods.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The L2C-220 is different from the L2C-210 and L2C-310 in that every
operation is a background operation: this means we have to use
spinlocks to protect all operations, and we have to wait for every
operation to complete.
Should a second operation be attempted while a previous operation
is in progress, the response will be an imprecise abort.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Where no errata affect the L2C-310 handlers, they are functionally
equivalent to L2C-210. Re-use the L2C-210 handlers for the L2C-310
part.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Implement L2C-310 erratum 588369 by overriding the invalidate range
and flush range methods in the outer_cache operations structure.
This allows us to sensibly contain the erratum code in one place
without affecting other locations/implemetations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Implement L2C-310 erratum 727915 by overriding the flush_all method
in the outer_cache operations structure. This allows us to sensibly
contain the erratum code in one place without affecting other
locations or implementations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add L2C-210 specific cache operation handlers. These are tailored to
the requirements of the L2C-210 cache controller, which doesn't
require any workarounds. We avoid using the way operations during
normal operation, which means we can avoid locking: the only time
we use the way operations are during initialisation, and when
disabling the cache.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the pl310_set_debug() into the l2c-310 code area, and don't hide
it with ifdefs. Rename it to l2c310_set_debug().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The l2x0 unlocking code is only called from l2x0_enable() now, so move
the logic entirely into that function and simplify it.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rename the pl310 save/resume functions to have a l2c310 prefix - this
is it's official name. Use a local cached copy of the l2x0_base
virtual address, and also realise that many of the resume function
tails are the same as the enable functions, so make a call to the
enable function instead of duplicating that code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add the save/resume code hooks to the non-OF implementations as well.
There's no reason for the non-OF implementations to be any different
from the OF implementations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than putting quirk handling in __l2c_init(), move it out to a
separate function which individual implementations can specify. This
helps to localise the quirks to those implementations which require
them.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than having this hacked into the OF initialiation function, we
can handle this via the enable function instead. While here, clean
up that code and comments a little.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Avoid unnecessary writes to the auxiliary control register if the
register already contains the required value. This allows us to
avoid invoking the platforms secure monitor code unnecessarily.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We should write the auxillary control register before unlocking: the
write may be necessary to enable non-secure access to the lock
registers.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Providing an enable method gives L2 cache controllers a chance to do
special handling at enable time. This allows us to remove a hack in
l2x0_unlock() for Marvell Aurora L2 caches.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Back in the mists of time, someone decided that it would be a good idea
to group like functions together - so all the save functions in one
place, all the resume functions in another, all the OF parsing functions
some place else.
This makes it difficult to get an overview on what a particular
implementation is doing - grouping an implementations specific functions
together makes more sense, because you can see what it's doing without
the clutter of other implementations.
Organise it according to implementation.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There's no reason this functionality should be specific to DT, so move
it into the common initialisation function.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Pass the iomem address into this function so we don't have to keep
accessing it from a global.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than having a boolean and other tricks to disable some bits of
l2x0_init(), split this function into two parts: a common part shared
between OF and non-OF, and the non-OF part.
The common part can take a block of function pointers, and the cache
ID (to cope with Aurora's DT specified ID.) Eliminate the redundant
setting of l2x0_base in the OF case, moving it to the non-OF init
function.
This allows us to localise the OF-specific initialisation handling
from the non-OF handling.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The revision namespace is specific to the L2 cache part, so don't name
these with generic identifiers, use a part specific identifier.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
cache_wait_way() is actually used to wait for a particular mask to
report clear; it's not really got much to do with cache ways at all.
Indeed, it gets used to wait for the C bit to clear on older caches.
Rename this with a more generic function name which better reflects
its purpose: l2c_wait_mask().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Provide a generic helper function for way based operations. These are
always background operations, and thus have to be waited for before a
new operation is commenced. This helper extracts that requirement from
several locations in the code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Split the cache unlock code out of l2x0_unlock(). We want to be able
to re-use this functionality later.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Provide a generic function which always calls the set_debug method.
This will be used later in the series as some work-arounds require
that the debug register be written.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rename a few things to help distinguish their function(s):
l2x0_of_data -> l2c_init_data
setup -> of_parse
add of_ prefix to OF specific data
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove NULL initialisers, make these all __initconst structures, and
order their members in the same order as the structure declaration.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Update sunxi_defconfig and multi_v7 with all the latest Allwinner
additions.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
v3.16 that's dts fixes for clocks and enabling few features
that were still being discussed earlier:
- A bunch of omap clock related dts fixes queued by Tero Kristo.
- Enable parallel nand on am437x that was not merged earlier as
I requested more information about the muxing for it. And
we need to also enable ecc hardware support for am43xx.
- Enable the modem support for n900 that was dropped earlier
because we had to fix the related hwmod entry first with patch
ARM: OMAP2+: Fix ssi hwmod entry to allow idling.
- And finally, add the omap2 clock dts files. These will allow
us to enable the dt clocks and drop the legacy clocks for omap2
with a follow-up patch once the related clock driver binding
changes are merged.
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Merge tag 'omap-for-v3.16/dt-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Merge "omap dt fixes and and clocks for v3.16 merge window" from Tony Lindgren:
Most likely the last pull request from me for omap changes for
v3.16 that's dts fixes for clocks and enabling few features
that were still being discussed earlier:
- A bunch of omap clock related dts fixes queued by Tero Kristo.
- Enable parallel nand on am437x that was not merged earlier as
I requested more information about the muxing for it. And
we need to also enable ecc hardware support for am43xx.
- Enable the modem support for n900 that was dropped earlier
because we had to fix the related hwmod entry first with patch
ARM: OMAP2+: Fix ssi hwmod entry to allow idling.
- And finally, add the omap2 clock dts files. These will allow
us to enable the dt clocks and drop the legacy clocks for omap2
with a follow-up patch once the related clock driver binding
changes are merged.
* tag 'omap-for-v3.16/dt-part3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: omap2 clock data
ARM: dts: am437x-gp-evm: add support for parallel NAND flash
ARM: OMAP2+: gpmc: enable BCH_HW ecc-scheme for AM43xx platforms
ARM: dts: omap3 a83x: fix duplicate usb pin config
ARM: dts: omap3: set mcbsp2 status
ARM: dts: omap3-n900: Add modem support
ARM: dts: omap3-n900: Add SSI support
ARM: OMAP2+: Fix ssi hwmod entry to allow idling
ARM: dts: AM4372: clk: efuse based crystal frequency detect
ARM: dts: am43xx-clocks.dtsi: add ti, set-rate-parent to display clock path
ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clk
ARM: dts: omap4: add twd clock to DT
ARM: dts: omap54xx-clocks: Correct abe_iclk clock node
ARM: dts: omap54xx-clocks: remove the autoidle properties for clock nodes
ARM: dts: am43x-clock: add tbclk data for ehrpwm
ARM: dts: am33xx-clock: Fix ehrpwm tbclk data
ARM: dts: set 'ti,set-rate-parent' for dpll4_m5 path
ARM: dts: use ti,fixed-factor-clock for dpll4_m5x2_mul_ck
ARM: dts: am43xx-clocks: use ti, fixed-factor-clock for dpll_per_clkdcoldo
Signed-off-by: Olof Johansson <olof@lixom.net>
When targetting ARCH_MULTIPLATFORM, we may include support for SoCs with
PCI-capable devices (e.g. mach-virt with virtio-pci).
This patch allows PCI support to be selected for these SoCs by selecting
CONFIG_MIGHT_HAVE_PCI when CONFIG_ARCH_MULTIPLATFORM=y and removes the
individual selections from multi-platform enabled SoCs.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
- From Daniel Lezcano:
This patchset relies on the cpm_pm notifier to initiate the
powerdown sequence operations from pm.c instead cpuidle.c.
Thus the cpuidle driver is no longer dependent from arch
specific code as everything is called from the pm.c file.
Note, this is based on tags/exnos-mcpm and tags/samsung-clk
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Merge tag 'exynos-cpuidle' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
Merge "Samsung exynos-cpuidle updates for v3.16" from Kukjin Kim:
- From Daniel Lezcano:
This patchset relies on the cpm_pm notifier to initiate the
powerdown sequence operations from pm.c instead cpuidle.c.
Thus the cpuidle driver is no longer dependent from arch
specific code as everything is called from the pm.c file.
* tag 'exynos-cpuidle' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (94 commits)
ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos
ARM: EXYNOS: Move the driver to drivers/cpuidle directory
ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c
ARM: EXYNOS: Pass the AFTR callback to the platform_data
ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c
ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier
ARM: EXYNOS: Move the AFTR state function into pm.c
ARM: EXYNOS: Encapsulate the AFTR code into a function
ARM: EXYNOS: Disable cpuidle for exynos5440
ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle
ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle
ARM: EXYNOS: Remove ifdef for scu_enable in pm
ARM: EXYNOS: Move scu_enable in the cpu_pm notifier
ARM: EXYNOS: Use the cpu_pm notifier for pm
ARM: EXYNOS: Fix S5P_WAKEUP_STAT call for cpuidle
ARM: EXYNOS: Move some code inside the idle_finisher for cpuidle
ARM: EXYNOS: Encapsulate register access inside a function for pm
ARM: EXYNOS: Change function name prefix for cpuidle
ARM: EXYNOS: Use cpuidle_register
ARM: EXYNOS: Prevent forward declaration for cpuidle
...
Signed-off-by: Olof Johansson <olof@lixom.net>
In this time, it is having dependency with arch/arm/ for 3.16,
I pulled them into samsung tree from Tomasz under agreement from Mike.
- Pull for_3.16/exynos5260 from Tomasz Figa:
"This pull request contains patches preparing Samsung Common Clock Framework
helpers to support Exynos5260 by adding support for multiple clock providers
and then adding clock driver for Exynos5260."
- Pull for_3.16/clk_fixes_non_critical from Tomasz Figa:
"This pull requests contains a number of non-critical fixes for Samsung clock
framework and drivers, including:
1) a series of fixes for Exynos5420 to correct clock definitions and make the
driver closer to the documentation,
2) several missing clocks and clock IDs added to Exynos4, Exynos5250 and
Exynos5420 drivers,
3) fix for incorrect initialization of clock table with NULL,
4) compiler warning fix."
- Pull for_3.16/clk_cleanup from Tomasz Figa:
"This pull requests contains minor clean-up related to Samsung clock
support, including:
1) move Kconfig entries of Samsung clock drivers to drivers/clk,
2) compile drivers/clk/samsung conditionally when COMMON_CLK_SAMSUNG is
selected,
3) remove obsolete Kconfig lines after moving s3c24xx to CCF."
- Pull for_3.16/exynos3250 from Tomasz Figa:
"This small pull request contains a patch adding clock driver for Exynos3250,
which depends on previous pull requests in this series."
- add dt bindings for exynos3250 clock
- add exynos5800 specific clocks in current exynos5420 clock
Note that this branch is based on s3c24xx ccf branch
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Merge tag 'samsung-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Samsung clock updates for 3.16" from Kukjin Kim:
In this time, it is having dependency with arch/arm/ for 3.16,
I pulled them into samsung tree from Tomasz under agreement from Mike.
- Pull for_3.16/exynos5260 from Tomasz Figa:
"This pull request contains patches preparing Samsung Common Clock Framework
helpers to support Exynos5260 by adding support for multiple clock providers
and then adding clock driver for Exynos5260."
- Pull for_3.16/clk_fixes_non_critical from Tomasz Figa:
"This pull requests contains a number of non-critical fixes for Samsung clock
framework and drivers, including:
1) a series of fixes for Exynos5420 to correct clock definitions and make the
driver closer to the documentation,
2) several missing clocks and clock IDs added to Exynos4, Exynos5250 and
Exynos5420 drivers,
3) fix for incorrect initialization of clock table with NULL,
4) compiler warning fix."
- Pull for_3.16/clk_cleanup from Tomasz Figa:
"This pull requests contains minor clean-up related to Samsung clock
support, including:
1) move Kconfig entries of Samsung clock drivers to drivers/clk,
2) compile drivers/clk/samsung conditionally when COMMON_CLK_SAMSUNG is
selected,
3) remove obsolete Kconfig lines after moving s3c24xx to CCF."
- Pull for_3.16/exynos3250 from Tomasz Figa:
"This small pull request contains a patch adding clock driver for Exynos3250,
which depends on previous pull requests in this series."
- add dt bindings for exynos3250 clock
- add exynos5800 specific clocks in current exynos5420 clock
Note that this branch is based on s3c24xx ccf branch
* tag 'samsung-clk' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (59 commits)
clk: exynos5420: Add 5800 specific clocks
dt-bindings: add documentation for Exynos3250 clock controller
ARM: S3C24XX: fix merge conflict
clk: samsung: exynos3250: Add clocks using common clock framework
drivers: clk: use COMMON_CLK_SAMSUNG for Samsung clock support
ARM: S3C24XX: move S3C24XX clock Kconfig options to Samsung clock Kconfig file
ARM: select COMMON_CLK_SAMSUNG for ARCH_EXYNOS and ARCH_S3C64XX
clk: samsung: add new Kconfig for Samsung common clock option
ARM: S3C24XX: Remove omitted Kconfig selects and conditionals
clk: samsung: exynos5420: add more registers to restore list
clk: samsung: exynos5420: add misc clocks
clk: samsung: exynos5420: update clocks for MAU Block
clk: samsung: exynos5420: fix register offset for sclk_bpll
clk: samsung: exynos5420: correct sysmmu-mfc parent clocks
clk: samsung: exynos5420: update clocks for FSYS and FSYS2 blocks
clk: samsung: exynos5420: update clocks for WCORE block
clk: samsung: exynos5420: update clocks for PERIS and GEN blocks
clk: samsung: exynos5420: update clocks for PERIC block
clk: samsung: exynos5420: update clocks for DISP1 block
clk: samsung: exynos5420: update clocks for G2D and G3D blocks
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- adding MCPM backend support for SMP secondary boot and core switching
on Samsung's Exynos5420.
Tested on exynos5420-smdk5420 and exynos5420 based chromebook (peach-pit)
using the "/dev/b.L_switcher" user interface. Secondary core boot-up has
also been tested on both the boards.
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Merge tag 'exynos-mcpm' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Merge "Exynos MCPM support for v3.16" from Kukjin Kim:
- adding MCPM backend support for SMP secondary boot and core switching
on Samsung's Exynos5420.
Tested on exynos5420-smdk5420 and exynos5420 based chromebook (peach-pit)
using the "/dev/b.L_switcher" user interface. Secondary core boot-up has
also been tested on both the boards.
* tag 'exynos-mcpm' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Add MCPM call-back functions
ARM: dts: add CCI node for exynos5420
ARM: EXYNOS: Add generic cluster power control functions
ARM: EXYNOS: use generic exynos cpu power control functions
ARM: EXYNOS: Add generic cpu power control functions for exynos SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
- exynos4
: add hsotg device, exynos_usbphy nodes
: add PMU syscon and audio subsystem nodes
: replace number by macro in clock binding
- exynos4210-universal_c210
: add external sd card node and multimedia nodes
: enable USB functionality
- exynos4412-trats2
: enable usb nodes and usb gagdet functionality
: add cm36651 light/proximity sensor node
: fixed gpio key node
- exynos5250 and exynos5420
: add pmu syscon handle and sysreg system controller nodes
: add support for usb2phy
: replace number by macro in clock binding
: add USB 2.0 support on exynos5420
- exynos5420-peach-pit
: move dp hpd gpio pin to pinctrl_0
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Merge tag 'samsung-dt-2' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
Merge "Samsung 2nd DT updates for v3.16" from Kukjin Kim:
exynos4
- add hsotg device, exynos_usbphy nodes
- add PMU syscon and audio subsystem nodes
- replace number by macro in clock binding
exynos4210-universal_c210
- add external sd card node and multimedia nodes
- enable USB functionality
exynos4412-trats2
- enable usb nodes and usb gagdet functionality
- add cm36651 light/proximity sensor node
- fixed gpio key node
exynos5250 and exynos5420
- add pmu syscon handle and sysreg system controller nodes
- add support for usb2phy
- replace number by macro in clock binding
- add USB 2.0 support on exynos5420
exynos5420-peach-pit
- move dp hpd gpio pin to pinctrl_0
* tag 'samsung-dt-2' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (21 commits)
ARM: dts: enable usb nodes for exynos4412-trats2
ARM: dts: add hsotg device node for exynos4
ARM: dts: add exynos_usbphy node for exynos4
ARM: dts: add PMU syscon node for exynos4
ARM: dts: add pmu syscon handle to exynos5420 hdmi
ARM: dts: add pmu syscon handle to exynos5250 hdmi
ARM: dts: replace number by macro in clock binding for exynos5420
ARM: dts: replace number by macro in clock binding for exynos5250
ARM: dts: replace number by macro in clock binding for exynos4
ARM: dts: add external sd card node for exynos4210-universal_c210
ARM: dts: add multimedia nodes for exynos4210-universal_c210
ARM: dts: enable USB functionality for exynos4210-universal_c210
ARM: dts: Enable USB gadget functionality for exynos4210-trats
ARM: dts: Add audio subsystem nodes to exynos4.dtsi
ARM: dts: fixed gpio key node for exynos4412-trats2
ARM: dts: add cm36651 light/proximity sensor node for exynos4412-trats2
ARM: dts: Add USB 2.0 support on exynos5420
ARM: dts: Add usb2phy support on exynos5420
ARM: dts: Add usb2phy to exynos5250
ARM: dts: Add sysreg sytem controller node to exynos5250 and exynos5420
...
- use a common macro v7_exit_coherency_flush macro instead of local function
- cleanup mach-exynos/Makefile and remove inclusion plat/cpu.h in mach-exynos
- migrate exynos macros from plat-samsung to mach-exynos
- cleanup s3c24xx debug macro/earlyprintk to remove arch dependency
- fixed compilation error for cpufreq due to moving header in this branch
: use of_machine_is_compatible() instead of soc_is_exynos...()
Note that based on tags/samsung-clk and tags/samsung-fixes.
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Merge tag 'samsung-cleanup' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
Merge "Samsung cleanup for v3.16" from Kukjin Kim:
- use a common macro v7_exit_coherency_flush macro instead of local function
- cleanup mach-exynos/Makefile and remove inclusion plat/cpu.h in mach-exynos
- migrate exynos macros from plat-samsung to mach-exynos
- cleanup s3c24xx debug macro/earlyprintk to remove arch dependency
- fixed compilation error for cpufreq due to moving header in this branch
: use of_machine_is_compatible() instead of soc_is_exynos...()
Note that based on tags/samsung-clk and tags/samsung-fixes.
* tag 'samsung-cleanup' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
cpufreq: exynos: Fix the compile error
ARM: S3C24XX: move debug-macro.S into the common space
ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
ARM: S3C24XX: trim down debug uart handling
ARM: compressed/head.S: remove s3c24xx special case
ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
ARM: EXYNOS: Remove exynos_subsys registration
ARM: EXYNOS: Remove duplicate lines in Makefile
ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
ARM: dts: Remove g2d_pd node for exynos5420
ARM: dts: Remove mau_pd node for exynos5420
ARM: exynos_defconfig: enable HS-I2C to fix for mmc partition mount
ARM: dts: disable MDMA1 node for exynos5420
ARM: EXYNOS: fix the secondary CPU boot of exynos4212
Signed-off-by: Olof Johansson <olof@lixom.net>
Add device-tree file for APQ8084-MTP board, which belongs
to the Snapdragon 805 family.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add support for the Qualcomm Snapdragon 805 APQ8084 SoC. It is
used on APQ8084-MTP and other boards.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add information about the APQ8084 debug UART physical and virtual
addresses in the DEBUG_QCOM_UARTDM Kconfig help section.
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8660-surf.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Add GSBI node and configuration of GSBI controller
Signed-off-by: Kumar Gala <galak@codeaurora.org>
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
* Add GSBI node and configuration of GSBI controller
Signed-off-by: Kumar Gala <galak@codeaurora.org>
This has been unused since omap4 board files went away.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
This adds support for the tsc2005 touchscreen
to the Nokia N900 DTS file.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Put architecture-specific assembly code where it belongs,
allowing for support of additional architectures such as arm64 in
the future.
Signed-off-by: Christopher Covington <cov@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
On sam9x5, dedicated CTS (and RTS) pins are unusable together with the
LCDC, the EMAC, or the MMC because they share the same line.
Moreover, the USART controller doesn't handle DTR/DSR/DCD/RI signals,
so we have to control them via GPIO.
This patch permits to use GPIOs to control the CTS/RTS/DTR/DSR/DCD/RI
signals.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This is needed for gpiod_get_direction().
Otherwise, it returns -EINVAL.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-apq8074-dragonboard.dts)
* Move spi pinctrl into board file
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
* Move timer node out of SoC container
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Now that CONFIG_USB_DEBUG is gone, remove it from a number of defconfig
files that were enabling it.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The content of /sys/devices/system/cpu/cpu*/online is still 1 for those
CPUs that the switcher has removed even though the global state in
/sys/devices/system/cpu/online is updated correctly.
It turns out that commit 0902a9044f ("Driver core: Use generic
offline/online for CPU offline/online") has changed the way those files
retrieve their content by relying on on the generic attribute handling
code. The switcher, by calling cpu_down() directly, bypasses this
handling and the attribute value doesn't get updated.
Fix this by calling device_offline()/device_online() instead.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Abhilash Kesavan