Add device tree node for usbmisc which controls the non-core USB
registers. This is required to use the property to disable the over-
current detection.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This adds USB PHY and USB controller nodes. Vybrid SoCs have two
independent USB cores which each supports DR (dual role). However,
real OTG is not supported since the OTG ID pin is not available.
The PHYs are located within the anadig register range, hence we need
to change the length of the anadig registers.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add FlexCAN node for the two FlexCAN IP instances in Vybrid.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Pull timer core updates from Thomas Gleixner:
"This time you get nothing really exciting:
- A huge update to the sh* clocksource drivers
- Support for two more ARM SoCs
- Removal of the deprecated setup_sched_clock() API
- The usual pile of fixlets all over the place"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
clocksource: Add Freescale FlexTimer Module (FTM) timer support
ARM: dts: vf610: Add Freescale FlexTimer Module timer node.
clocksource: ftm: Add FlexTimer Module (FTM) Timer devicetree Documentation
clocksource: sh_tmu: Remove unnecessary OOM messages
clocksource: sh_mtu2: Remove unnecessary OOM messages
clocksource: sh_cmt: Remove unnecessary OOM messages
clocksource: em_sti: Remove unnecessary OOM messages
clocksource: dw_apb_timer_of: Do not trace read_sched_clock
clocksource: Fix clocksource_mmio_readX_down
clocksource: Fix type confusion for clocksource_mmio_readX_Y
clocksource: sh_tmu: Fix channel IRQ retrieval in legacy case
clocksource: qcom: Implement read_current_timer for udelay
ntp: Make is_error_status() use its argument
ntp: Convert simple_strtol to kstrtol
timer_stats/doc: Fix /proc/timer_stats documentation
sched_clock: Remove deprecated setup_sched_clock() API
ARM: sun6i: a31: Add support for the High Speed Timers
clocksource: sun5i: Add support for reset controller
clocksource: efm32: use $vendor,$device scheme for compatible string
KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform
...
This adds devicetree node for VF610, and there are 8 channels
supported.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The kernel was not able to boot from SD card because sdhc support
was not present into the dts.
A new entry for sdhc1 was added for vf610-twr board based on the
compatible entry present on imx53.
After applying these changes, the kernel is able to boot successfully
from SD card.
Signed-off-by: Cosmin Stoica <cosminstefan.stoica@freescale.com>
Signed-off-by: Chircu Bogdan <Bogdan.Chircu@freescale.com>
Signed-off-by: Eddy Petrisor <eddy.petrisor@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Per bindings of fixed-clock, #clock-cells is a required property. Let's
add it for those fixed rate clocks.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This is likely a copy-and-paste error from the
ARM GIC documentation, that has already been fixed.
address-cells should have been set to 0, as with the size
cells. As having those properties set to 0 is the
same thing as not specifying them, drop them completely.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Add i2c dts node properties for eDMA support, them depend on the eDMA driver.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
vf610 has two ADC controllers, and vf610-twr board ADC0_SE5 pin connect
to sliding rheostat for ADC test, other ADC pins connect to connectors for
future use.
Add support for ADC0_SE5.
CC: Jonathan Cameron <jic23@kernel.org>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: Peter Meerwald <pmeerw@pmeerw.net>
CC: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch uses the IRQ_TYPE_LEVEL_HIGH/IRQ_TYPE_NONE to replace
the hardcode.
[shawn.guo: While at it, we also fix the typo in uart0 interrupts
property, where the 0x00 should 0x04. Hense, it should also be
IRQ_TYPE_LEVEL_HIGH just like other UART instances.]
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts. However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected. This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board. It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.
The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral. Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Fugang Duan <B38611@freescale.com>
The fec/enet driver calculates MDC rate with the formula below.
ref_freq / ((MII_SPEED + 1) x 2)
The ref_freq here is the fec internal module clock, which is missing
from clk-vf610 clock driver right now. And clk-vf610 driver mistakenly
supplies RMII clock (50 MHz) as the source to fec. This results in the
situation that fec driver gets ref_freq as 50 MHz, while physically it
runs at 66 MHz (fec module clock physically sources from ipg which runs
at 66 MHz). That's why software expects MDC runs at 2.5 MHz, while the
measurement tells it runs at 3.3 MHz. And this causes the PHY KSZ8041
keeps swithing between Full and Half mode as below.
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
libphy: 400d0000.etherne:00 - Link is Up - 100/Full
libphy: 400d0000.etherne:00 - Link is Up - 100/Half
Add the missing module clock for ENET0 and ENET1, and correct the clock
supplying in device tree to fix above issue.
Thanks to Alison Wang <b18965@freescale.com> for debugging the issue.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The gpio-ranges properties in vf610.dtsi were written according to an
older version of the GPIO bindings. Unfortunately, these were changed
incompatibly in commit 86853c8 "gpio: add gpio offset in gpio range
cells property". This patch adds the missing required extra cell in each
gpio-ranges property.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Stefan Agner