Some PLL clocks are N (multiplier) type clocks, or can be simplified
as such. An example of the former is the DDR1 PLL clock on the A33.
An example of the latter is the CPU PLL clock on the A80, in which
the P divider is only used for low frequencies that are of little
use. Both clocks support PLL lock detection.
The mult clock macro implies support for this, but that is not true.
The field is simply discarded. This patch adds proper support for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Some multipliers have a maximum rate that is lower than what the register
width allows to. Add a field in the multiplier structure to allow CCU
driver to set that maximum.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The factors we've seen so far all had an offset of one. However, on the
earlier Allwinner SoCs, some factors could have no offset at all, meaning
that the value computed to reach the rate we want to use was the one we had
to program in the registers.
Implement an additional field for the factors that can have such an offset
(linears, not based on a power of two) to specify that offset.
This offset is not linked to the extremums that can be specified in those
structures too. The minimum and maximum are representing the range of
values we can use to try to compute the best rate. The offset comes later
on when we want to set the best value in the registers.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Some clocks on the earlier SoCs such as the video PLLs are multipliers with
fractional settings.
Support those cases.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Allow the CCU drivers to specify a multiplier for their clocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Rename the structures meant to be embedded in other structures to make it
consistent with the mux structure name
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Add support for the class with a single factor, N, being a multiplier.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Start our new clock infrastructure by adding the registration code, common
structure and common code.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com
Chen-Yu Tsai