On arm32, the machine model specified in the device tree is printed
during boot-up, courtesy of of_flat_dt_match_machine().
On arm64, of_flat_dt_match_machine() is not called, and the machine
model information is not available from the kernel log.
Print the machine model to make it easier to derive the machine model
from an arbitrary kernel boot log.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* pci/resource-mmap:
ia64: Use generic pci_mmap_resource_range()
ia64: Remove redundant checks for WC in pci_mmap_page_range()
ia64: Remove redundant valid_mmap_phys_addr_range() from pci_mmap_page_range()
PCI: Add I/O BAR support to generic pci_mmap_resource_range()
x86/PCI: Use generic pci_mmap_resource_range()
unicore32/PCI: Use generic pci_mmap_resource_range()
sh/PCI: Use generic pci_mmap_resource_range()
parisc: Use generic pci_mmap_resource_range()
mn10300/PCI: Use generic pci_mmap_resource_range()
MIPS: PCI: Use generic pci_mmap_resource_range()
cris/PCI: Use generic pci_mmap_resource_range()
ARM/PCI: Use generic pci_mmap_resource_range()
PCI: Add pci_mmap_resource_range() and use it for ARM64
PCI: Add BAR index argument to pci_mmap_page_range()
PCI: Use BAR index in sysfs attr->private instead of resource pointer
PCI: Add arch_can_pci_mmap_io() on architectures which can mmap() I/O space
PCI: Move multiple declarations of pci_mmap_page_range() to <linux/pci.h>
PCI: Add arch_can_pci_mmap_wc() macro
xtensa/PCI: Do not mmap PCI BARs to userspace as write-through
PCI: Only allow WC mmap on prefetchable resources
PCI: Fix another sanity check bug in /proc/pci mmap
PCI: Fix pci_mmap_fits() for HAVE_PCI_RESOURCE_TO_USER platforms
Add missing L2 cache events: read/write accesses and misses, as well as
the DTLB refills.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The sunxi clk driver causes a link error when the reset controller
subsystem is disabled:
drivers/clk/built-in.o: In function `sun4i_ve_clk_setup':
:(.init.text+0xd040): undefined reference to `reset_controller_register'
drivers/clk/built-in.o: In function `sun4i_a10_display_init':
:(.init.text+0xe5e0): undefined reference to `reset_controller_register'
drivers/clk/built-in.o: In function `sunxi_usb_clk_setup':
:(.init.text+0x10074): undefined reference to `reset_controller_register'
We already force it to be enabled on arm32 and some other arm64 platforms,
but not on arm64/sunxi. This adds the respective Kconfig statements to
also select it here.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum.
According to regular hierarchy of sprd dts, whale2.dtsi contains SoC
peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff
and sp9860g dts is for the board level.
Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com>
Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY+jQpAAoJEME3ZuaGi4PXmkAP/i9Sbf+bYZqa32Zv8zh0hu8r
KQ6iJ7N7fANYqBe+/H7gBXvjLq5VWsPMMkJSDBOVHWXH76iQAji7w+ORc75VlWXw
gpx+rLQMflMAFk7yq7Ern+V7Nj+ZmEZSUK455//M2cBPBsrpSt9qtKVZd/IxzcbP
zexpcwYilTv890sXtJfOVZgHzBTQ996XbD0VrI2HAH1XFiGgEFEyViSgPpikS/gZ
MyQjSRi0t+ETp45oNIQuMcNgBrR1naDm+VVOhiQXNW3cXrDkQ0ENMrEGtpbaOC/X
ngfNJk8f3wrGg+kS2H2v1/PeUYiWXNBTCFR/CNoBcDyvLHXEjPtI7LO/pAKKgfBQ
H1Bqxquk+QvgtGJEoshuVOWJixjZ3WEAUZ3kNgYHp2YHf/+mvff6STgxb2RePj74
ZSZInREUST/mc8M3DzjCVGnMUPIpbvOQnWPLkdAmtWXxm4lyIblXV9YPJUjRsaTQ
xpKhnpIpEG1N4mfb/VNGKm8kEs5MWV6j6ajejScTCnqgD+CGzTy9cVZKOMRd4MEz
+1L+BOcR9lvnTey0WghVPrpl3CZAskVpI5gq2o7jrg2GsfTifZ4BxxQKktZXjcrM
n6x9Hlr4yBT0zLzT36yfM5+jyzUuSv3EQHcgolcBdlSJX6isQwQJAZhXO9B824tA
ckVPhI4X43BGscjszMTs
=NymV
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Pull "Fix DTC warnings in Exynos ARMv7 Device Tree sources." from Krzysztof Kozłowski:
* tag 'samsung-dt-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Use - instead of @ for DT OPP entries
- Fix DTC warnings in Exynos ARM64 Device Tree sources.
- Add panel node to TM2E board.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY/kHtAAoJEME3ZuaGi4PXXQsP/2dMb6o0Vh9sVkOxluVMnpol
1gW0c6DAbrPq6AikGzWJ4A9btqIhtHcSJiqQKOTdz0NJzWGvwBMBYZc5YwJuD+iw
cgStgPzHS1gd8n6kCGDvIUzjMUvWkhHkd8XoJuRn7jPQgmM8maPBy9GarkYtdy4B
Kvu4T9SIic/zY1lGJTow841vlgqVW/pYE4r0kWIutThr+O60wfu8G5eklc3XUwpb
StNm17G/JDxfKbYHXTQTFYM/A7Jf/p60zLXH+DkzyQf+Z7ROoFM1jKmKiefYaw+s
Mr5UKshRe1ovdlTln0/JB6Gt7UYPO9OLmuwKqxH+ywGOTSzCWqYjOFmMhfg5T82q
E+xdJ9mGX5JwSaFg/BCeYL4DxBOfisTY8CBKbkT0RCRs74EMK8XGc5bNhxqZUrVn
gpDfmj4w8rPRzb80ZqIla3tl+9rTHlcVo1ah9keOBiuagjrk2fdFUkZET993m558
K66u1AdQ9WaaLsOQDQVF/4hBiSg+eakS5mGhrE6ryaAAm0SiHUq+yxFsU+ufXBV1
t53TNo4CqQAQlyoeJ1vsCuIGVwHREXNnj4h1zc2Vb/o6NHQ4T2KG2mE9W9vNx0of
gingYJzJdacRwbpM6MmXNwSh4A2OkDPBEkRb78LgPzb69aF1HhoOjn6poLCUfpJh
jx/inKl91/sGdXB+h9b3
=JgAW
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.12-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Pull "Second update of Samsung DeviceTree ARM64 for v4.12" from Krzysztof Kozłowski:
- Fix DTC warnings in Exynos ARM64 Device Tree sources.
- Add panel node to TM2E board.
* tag 'samsung-dt64-4.12-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Use - instead of @ for DT OPP entries
arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
1. Couple of fixes to remove device tree warnings introduced with
recently added checks in DTC
2. Add information about L1 and L2 caches to Juno device trees as
CCSIDR-based cacheinfo probing is now removed
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABCAAGBQJY95CUAAoJEABBurwxfuKYiREP/1SKsiZsRsaX9EfnIT+5GtLO
8K0UT4lDZz/co6OHPODWFhwiFAeuLALQ5WCX1qTippF/HrPs5xNFK7x1Qxku46Hj
dEr++8S4QHBg0CevxBK5RvmiAc3V+xzCt98b5sVWuvXYRUR3rLQMeT1bm23ms76D
96oFFMuJ0JzsVsYypiLw1GVwoH+rLVfyuevnknNqnIhJ+FPuGgREh16+FqzCL6RT
KrpJiRcA2ZAlge7krQxvP2zRv3Q3hkSu5O2ORFbNFc7EybszZUaIolBQ6+KJW9Ol
NPVu6plUibmJeki4GY7iyyx0MTyK0Dg1WbDHj8Ag7Z3up2OVdcFWz4/lpvNtQIq5
/4BFK7XJyrk7SJphWI4UePjCK+6oU/WA6AeB5ZI1X8BLHgbK7I1YYYWN/qL94MEZ
0pyVfOuBsF5yodyoXbt47MSa1UbvaRPEFbzvyywXPR97MZza+JHlmw4Kgg+paB9k
n93X7Kd693bRBQwaqjeLuXCyYK/6jZWzJAJx/uN7i+pL6NceR0w/9VMYU9G9WXj2
qrLsCqx6AAjqYQho2iVcfBAIVjwP50GKb+/0pcb3i8Lo/gtNX+lSXqWgA3lKRPCH
x43PerYGh49STAfMk4VR+WC95bpiohk6JUpk3kJ2WLy9v86EJ9usnX1wflL1wW5f
V/KNxYcnjuOZLRXiFt4u
=5Rho
-----END PGP SIGNATURE-----
Merge tag 'juno-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64
Pull "ARMv8 Juno DT fixes for v4.12" from Sudeep Holla:
1. Couple of fixes to remove device tree warnings introduced with
recently added checks in DTC
2. Add information about L1 and L2 caches to Juno device trees as
CCSIDR-based cacheinfo probing is now removed
* tag 'juno-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: add information about L1 and L2 caches
arm64: dts: juno: fix few unit address format warnings
arm64: dts: juno: fix PCI bus dtc warnings
Changes include:
- Using the common sysreg definitions between KVM and arm64
- Improved hyp-stub implementation with support for kexec and kdump on the 32-bit side
- Proper PMU exception handling
- Performance improvements of our GIC handling
- Support for irqchip in userspace with in-kernel arch-timers and PMU support
- A fix for a race condition in our PSCI code
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJY/IasAAoJEEtpOizt6ddyd7gH/2N3BIMxi/Uqigx0e0byA43s
f+8gNq8A71VBTERGW2l9QP1/AZAXpQYNWdWmN2jn+91x2yoVL7AT00gEsliSLEZv
tqZaTGFXKi1vNihYrxEWm1mfVNzhRrnbW6vjLrO4J5Advq7T3OWhNuVt2BLTxz3Y
h0iqOWNVrUD9h3QSBFH8tz7yXhguDTSppAcXbE0tACdRu4vN50wqEWokHJG5TsMG
Tl3KYWrcc3YCKlAJGuJi7t5rMrXk+g1q6HnxlIN6OSk0POC2Vmw9/Gigtltj1Qwh
ZEAwsnka/U8ak8WaWeZa3EsGTSFSoAk/+pKv2FB8mFN+uOmWDqVlEiol4dW49AY=
=mEOk
-----END PGP SIGNATURE-----
Merge tag 'kvm-arm-for-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
KVM/ARM Changes for v4.12.
Changes include:
- Using the common sysreg definitions between KVM and arm64
- Improved hyp-stub implementation with support for kexec and kdump on the 32-bit side
- Proper PMU exception handling
- Performance improvements of our GIC handling
- Support for irqchip in userspace with in-kernel arch-timers and PMU support
- A fix for a race condition in our PSCI code
Conflicts:
Documentation/virtual/kvm/api.txt
include/uapi/linux/kvm.h
kvm_make_all_requests() provides a synchronization that waits until all
kicked VCPUs have acknowledged the kick. This is important for
KVM_REQ_MMU_RELOAD as it prevents freeing while lockless paging is
underway.
This patch adds the synchronization property into all requests that are
currently being used with kvm_make_all_requests() in order to preserve
the current behavior and only introduce a new framework. Removing it
from requests where it is not necessary is left for future patches.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Some operations must ensure that the guest is not running with stale
data, but if the guest is halted, then the update can wait until another
event happens. kvm_make_all_requests() currently doesn't wake up, so we
can mark all requests used with it.
First 8 bits were arbitrarily reserved for request numbers.
Most uses of requests have the request type as a constant, so a compiler
will optimize the '&'.
An alternative would be to have an inline function that would return
whether the request needs a wake-up or not, but I like this one better
even though it might produce worse assembly.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The arm64 module PLT code allocates all PLT entries in a single core
section, since the overhead of having a separate init PLT section is
not justified by the small number of PLT entries usually required for
init code.
However, the core and init module regions are allocated independently,
and there is a corner case where the core region may be allocated from
the VMALLOC region if the dedicated module region is exhausted, but the
init region, being much smaller, can still be allocated from the module
region. This leads to relocation failures if the distance between those
regions exceeds 128 MB. (In fact, this corner case is highly unlikely to
occur on arm64, but the issue has been observed on ARM, whose module
region is much smaller).
So split the core and init PLT regions, and name the latter ".init.plt"
so it gets allocated along with (and sufficiently close to) the .init
sections that it serves. Also, given that init PLT entries may need to
be emitted for branches that target the core module, modify the logic
that disregards defined symbols to only disregard symbols that are
defined in the same section as the relocated branch instruction.
Since there may now be two PLT entries associated with each entry in
the symbol table, we can no longer hijack the symbol::st_size fields
to record the addresses of PLT entries as we emit them for zero-addend
relocations. So instead, perform an explicit comparison to check for
duplicate entries.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Commit f1b36dcb5c ("arm64: pmuv3: handle !PMUv3 when probing") is
a little too restrictive, and prevents the use of of backwards
compatible PMUv3 extenstions, which have a PMUver value other than 1.
For instance, ARMv8.1 PMU extensions (as implemented by ThunderX2) are
reported with PMUver value 4.
Per the usual ID register principles, at least 0x1-0x7 imply a
PMUv3-compatible PMU. It's not currently clear whether 0x8-0xe imply the
same.
For the time being, treat the value as signed, and with 0x1-0x7 treated
as meaning PMUv3 is implemented. This may be relaxed by future patches.
Reported-by: Jayachandran C <jnair@caviumnetworks.com>
Tested-by: Jayachandran C <jnair@caviumnetworks.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Add fixed clock of 400MHz to system controller driver. This clock is
used as SD/eMMC clock source.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Omri Itach <omrii@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
[fixed up conflicts, added error handling --rmk]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
The PCI bus specification (rev 3.0, 3.2.5 "Transaction Ordering and
Posting") defines rules for PCI configuration space transactions ordering
and posting, that state that configuration writes are non-posted
transactions.
This rule is reinforced by the ARM v8 architecture reference manual (issue
A.k, Early Write Acknowledgment) that explicitly recommends that No Early
Write Acknowledgment attribute should be used to map PCI configuration
(write) transactions.
Current ioremap interface on ARM64 implements mapping functions where the
Early Write Acknowledgment hint is enabled, so they cannot be used to map
PCI configuration space in a PCI specs compliant way.
Implement an ARM64 specific pci_remap_cfgspace() interface that allows to
map PCI config region with nGnRnE attributes, providing a remap function
that complies with PCI specifications and the ARMv8 architecture reference
manual recommendations.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[k.kozlowski: Split patch per ARM and ARM64]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
We now trap accesses to CNTVCT_EL0 when the counter is broken
enough to require the kernel to mediate the access. But it
turns out that some existing userspace (such as OpenMPI) do
probe for the counter frequency, leading to an UNDEF exception
as CNTVCT_EL0 and CNTFRQ_EL0 share the same control bit.
The fix is to handle the exception the same way we do for CNTVCT_EL0.
Fixes: a86bd139f2 ("arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled")
Reported-by: Hanjun Guo <guohanjun@huawei.com>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This reverts commit 42ae2922a6. It
causes a regression with older versions of gcc. The consensus is
that this should instead be fixed in clang.
Reported-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
[k.kozlowski: Split patch per ARM and ARM64]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch adds the panel device tree node for s6e3hf2 display
controller to TM2e dts.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
A function in kernel/bpf/syscall.c which got a bug fix in 'net'
was moved to kernel/bpf/verifier.c in 'net-next'.
Signed-off-by: David S. Miller <davem@davemloft.net>
With arch_setup_dma_ops now being called late during device's probe after
the device's iommu is probed, the notifier trick required to handle the
early setup of dma_ops before the iommu group gets created is not
required. So removing the notifier's here.
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
[rm: clean up even more]
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Starting to leave behind the legacy of the pci_mmap_page_range() interface
which takes "user-visible" BAR addresses. This takes just the resource and
offset.
For now, both APIs coexist and depending on the platform, one is
implemented as a wrapper around the other.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This patch adds support for parsing arch timer info in GTDT,
provides some kernel APIs to parse all the PPIs and
always-on info in GTDT and export them.
By this driver, we can simplify arm_arch_timer drivers, and
separate the ACPI GTDT knowledge from it.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org>
Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Select two new drivers for ARM64 mvebu SoCs:
- Xenon SDHCI controller on Armada 37xx and Armada 7K/8K
- Safexcel crypto engine on Armada 7K/8K
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWO+j/yMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71SnoAJ9r0d9MIBvq
3TWmgUDmImgaucJ5HACggm9+Jqh/GgXTBlxFnszhN9/BuCM=
=Le5K
-----END PGP SIGNATURE-----
Merge tag 'mvebu-defconfig64-4.12-2' of git://git.infradead.org/linux-mvebu into next/arm64
mvebu defconfig64 for 4.12 (part 2)
Select two new drivers for ARM64 mvebu SoCs:
- Xenon SDHCI controller on Armada 37xx and Armada 7K/8K
- Safexcel crypto engine on Armada 7K/8K
* tag 'mvebu-defconfig64-4.12-2' of git://git.infradead.org/linux-mvebu:
arm64: defconfig: enable the Safexcel crypto engine as a module
arm64: configs: enable SDHCI driver for Xenon
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Exynos power management drivers support now ARMv8 SoC - Exynos5433 - so
select them in ARCH_EXYNOS.
2. Enable few Exynos drivers for supported ARMv8 SoCs.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY6OrIAAoJEME3ZuaGi4PXqGEP/AketlP7sWJncRV8GU5ynsfL
0hRfK1Nsiku9ngHn86PaRXKIEhxSo7zl3ruqNwWu8CIzfpVjZxsXe9qXxirEDtLq
yoDb3TuNfhPJoLRhw+B1zPjl3MuI1OCX2lBE4xr4p5yMajEuzYoMDNob5z/Faxaa
BQq/IOMtBxKhEe5LDU0Vzjl0cltgsx6issu5hVtdAgdPPC24WaNmV74rdDeUt6+y
9gUwxcmIj08DjExvKXILBCNUmFIcvHPLcWzcAcquDPMwRP2u1sd4M/S2W+Zr3rad
PpJ98VTbwvUOyzrLRXvgpq/DzQwdKAPnrucu5JjMY3GIzZaCffcC7MHrzTGGRePn
W8LHkcpX/K2OYYBZZCRpUF9+PnNOdQp+SmS/bOe0kg6+Cv1NrOHi1hsverNcHCDs
ZiS0Z6ag8SaRpbUW6xNPjWFexAvV4zecxh2N7ojy1AKxYnbEPojjsot/6moudiuF
HahOG38/aiEmUUs3jBbgFfEtzrUTuAP1c2aeBNil5cwTQQ9v9ihZJ8jaDI9if6je
iIk8A9VsB712bkFUfXm0lRB09keHOi662rSS0KvFANp4athxj6faFdLd4wsrkyWQ
nA/jAB3nQ30mD+MJx3MSN+AZci+zx+pmh/Wo8ehXTQKkQS0DJaSW6OWqo/Gpv59G
MuUj9PBf9IEArewadSWo
=lXKo
-----END PGP SIGNATURE-----
Merge tag 'samsung-soc64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64
Samsung ARM64 update for v4.12:
1. Exynos power management drivers support now ARMv8 SoC - Exynos5433 - so
select them in ARCH_EXYNOS.
2. Enable few Exynos drivers for supported ARMv8 SoCs.
* tag 'samsung-soc64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: defconfig: Enable video, DRM and LPASS drivers for Exynos5433 and Exynos7
arm64: exynos: Enable Exynos PMU and PM domains drivers
Signed-off-by: Olof Johansson <olof@lixom.net>
- crypto engine description for the Armada 7k/8k SoCs and the boards
using it
- SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards
using it
-----BEGIN PGP SIGNATURE-----
iIEEABECAEEWIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWO+ljCMcZ3JlZ29yeS5j
bGVtZW50QGZyZWUtZWxlY3Ryb25zLmNvbQAKCRALBhiOFHI71Q9dAJ4i+PBERM8X
wh0AI0kekOBF33L4YQCcDr5wYXQdCYgwnTBVYadOHvce61A=
=zSnq
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.12 (part 2)
- crypto engine description for the Armada 7k/8k SoCs and the boards
using it
- SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards
using it
* tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu:
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
Signed-off-by: Olof Johansson <olof@lixom.net>
- Reset the hi6220 mmc hosts to avoid hang
- Add the binding for the hi3798cv200 SoC and the poplar board
- Add basic dts files to support the hi3798cv200 poplar board
- Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
- Add driver strength MACRO for the hi3660 SoC
- Add the pinctrl dtsi file for hikey960 board to configure the pins
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY66cBAAoJEAvIV27ZiWZcSAAP/3qvcWDNVwc7Rg5JIcbvBP09
mBbcutrHmFVi5Swd3yuTyNErRFliVsdDV3dwanxlXOojqYgE4WpJQFKtXr8obQUa
q3yk+gzMIS3+P18dJPU+SFsCwLDaUF4PkiRm3vd4Oc6fgPfqCbWfYcS6jOhbBdzD
GWAMp6j/vn3Br3RSFe2NgH43kv2H4efEh0lrKj3wk2mCDF3s69PaMGPLgCfeV1F0
pYwyO/2v4TWuJkO8U7g1XyvK6LRO49mWDKdqhP0hZpr3DJP7T5u9E4bxScBwG2GY
ENURvZpl3Kd1thfR9+7FkwNg0Z7Y9hVNI5763JzLusd6pw1y2jDU9oEESpuVi1FH
9dwqloiLuonYSPvAM9XS84CXnguFoqjndf7Z3d9yliS86GRn4g5B5t20rlLtSE+4
o+IcLQy6z6CpDHugTzav3oBsscckEiWsmX0X6Jym23+buzFcHWOPOQldIUUSDDoq
9oct1AxBrQA9F9KspaiWRy38Bwi8qRT5FT+BfBai3y45FeEKdRFUghIwdeqm4F2v
1JulIiPelHUtELAcAEJFRVQzgfSVuGuXCAHVHpgXE018UnNvhfl3/VtUtvLI71wf
jukY2JIJsG9r/NHR1uZU8LGN70bNUjHXwuF0R/zh2zwZT+mDgxEe5zOlCbQyYJbt
uqVy7+asSKcbOLabW/Ae
=5zO6
-----END PGP SIGNATURE-----
Merge tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi into next/dt64
ARM64: DT: Hisilicon SoC DT updates for 4.12
- Reset the hi6220 mmc hosts to avoid hang
- Add the binding for the hi3798cv200 SoC and the poplar board
- Add basic dts files to support the hi3798cv200 poplar board
- Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
- Add driver strength MACRO for the hi3660 SoC
- Add the pinctrl dtsi file for hikey960 board to configure the pins
* tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
arm64: dts: hi6220: Reset the mmc hosts
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add mmc devices for ZX296718 SoC and enable those available on
zx296718-evb board.
- Add VOU controller device, output devices HDMI and TVENC, and enable
display support for zx296718-evb board.
- Remove pll_vga clock from ZX296718 device tree, as it's not a fixed
rate clock.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJY66HJAAoJEFBXWFqHsHzOUREH/RADjsUVP/5Jb1Dqs9FghOzK
DxIsFEc6TaeeDEzBA8p2jnd4xUi0vBSuJJw77QS/tYLt0eB+ermqw5MFYHknMyOY
OeDUx15fnC0n9WSkC4IFqlGXCnBuibcxjILSLwzsZ4jdVnvZtJ0nFAEckOpqeRDj
N9byLnK8fDZhlMP1A/opZhL51WKRSL/ImkqguoC5+Mm+/Lq2OuTtQukobfVHlTjc
lePX5uTPAujXoA9olHn0oliTPA/BDV9+ZWId4tqBSYxdJ06w0KqRiCk8xW04d1qF
BXEVOv4jo5HdTDa0ikUBcvvn0vD4RqZR6Wo/1I88nHY4mNJKF4ibqlMguL1mueA=
=d5as
-----END PGP SIGNATURE-----
Merge tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
ZTE arm64 device tree updates for 4.12:
- Add mmc devices for ZX296718 SoC and enable those available on
zx296718-evb board.
- Add VOU controller device, output devices HDMI and TVENC, and enable
display support for zx296718-evb board.
- Remove pll_vga clock from ZX296718 device tree, as it's not a fixed
rate clock.
* tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: zte: add tvenc device for zx296718
arm64: dts: zte: add vou and hdmi devices for zx296718
arm64: dts: zte: add mmc devices for zx296718
arm64: dts: zte: remove zx296718 pll_vga clock
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add support of LS2088A SoC, which is a derivative of existing
LS2080A SoC, and the major difference is on ARM cores.
- Add support of LS1088A SoC which includes eight Cortex-A53 cores
with 32 KB L1 D-cache and I-cache respectively.
- Add crypto and thermal device support for LS1012A platform.
- Add ECC register region for SATA device on LS1012A, LS1043A and
LS1046A platforms.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJY649rAAoJEFBXWFqHsHzO3O4H/Ry5BxyUsrIziFCMNv05chEw
/C5AJVGGHyZTc2q/nGeR+wkDXhB7p7xX9D4Fzl+lAss58J20yB403dbrc5r2cmPk
aataxt1q4wfH9KekGlEqkolkQrMPRb7i+j36xpjVUCeFww8C8rszFC3CJwcTLFX8
pdhykfIpKz/Osy1hWH4Nt9Ss3L+8DhmQGh1bueriggQ5f/MPkhZUk7goK4j8mlC+
i5oWcO6wWvTXg1HTW+PbtBFJWqQ7ztb0qHSikoJ8yWtIkzehlcgrO7qkdf8hI8pV
gj48OMrvS4b/aYsAKmfVGCDpNqedoJDVbPRXkES8/z1avkKUmGLnhr9Ftdw7saA=
=BYDv
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Freescale arm64 device tree updates for 4.12:
- Add support of LS2088A SoC, which is a derivative of existing
LS2080A SoC, and the major difference is on ARM cores.
- Add support of LS1088A SoC which includes eight Cortex-A53 cores
with 32 KB L1 D-cache and I-cache respectively.
- Add crypto and thermal device support for LS1012A platform.
- Add ECC register region for SATA device on LS1012A, LS1043A and
LS1046A platforms.
* tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards
dt-bindings: clockgen: Add compatible string for LS1088A
arm64: dts: Add support for FSL's LS1088A SoC
arm64: dts: ls1012a: add crypto node
arm64: dts: ls1012a: add thermal monitor node
arm64: dts: updated sata node on ls1012a platform
arm64: dts: added ecc register address to sata node on ls1046a
arm64: dts: added ecc register address to sata node on ls1043a
arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoC
arm64: dts: freescale: ls2080a: Split devicetree for code resuability
dt-bindings: Add compatible for LS2088A QDS and RDB board
Signed-off-by: Olof Johansson <olof@lixom.net>
default memory definition on the px5 eval board. While the bootloader
should already override it with the actual amount, it's better to not
carry around wrong values.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljpQgUQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgSriCACyesU9O1mz0CHWArxHY1O4UJ8SYdZqotOv
Q8XVWA7H9wrLMazyauHDGxZ63PbSMuhkOzpbUwBl6BEgUtVtr2j0c8JgvLk7IAqS
07ggX/7cYoqCLB8CKqkgdGKYjWIVwkGm0zL7lBwtlF6WnTl92B+gHEll8sv8R7ua
EO1Biq+o/XZrmsBoBBWtnaJdZYAcIMEU3qRtI4mInvOHkDCEvW0kaKuPT9A2h75j
7Asgpn0Na3sqX3UPAk5F1+YCEV40aZ10qPV1HurKL1E61HepDWs3rjymyXh0H12q
B9yzOGPfxdoU21rCAu1HtMu4ujo5ppvKRajeE4nyag92TTuP2lu4
=tcTl
-----END PGP SIGNATURE-----
Merge tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Basic support for new rk3328, a 4-core Cortex-A53 soc and a fix for the
default memory definition on the px5 eval board. While the bootloader
should already override it with the actual amount, it's better to not
carry around wrong values.
* tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: rockchip: add RK3328 eavluation board devicetree
dt-bindings: document rockchip rk3328-evb board
arm64: dts: rockchip: add core dtsi file for RK3328 SoCs
dt-bindings: add binding for rk3328-grf
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Add IR, touchscreen and panel to TM2/TM2E boards.
2. Add proper clock frequency properties to DSI nodes.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY6OyZAAoJEME3ZuaGi4PXMTUP/RErX9qqM49S4ygyFqgMcDy7
i7Zbkgxl9MfNOzzRLRUD9POsI7VjdCvOks1AWV6RMw1TOKHEjF/ChRsFoZBaneZu
UKSybe50sB+Xqok4Wo1RN+FRo9tVaOtOlPdQguR1f9salR40/eg6XC4tTdbsjzSE
m74+pnUdZuGTvXwkwrdXShKYgk0Z5fsBlM3QhOnG1XXfs+A/1yzpxDuDapB4WU/K
s+z2dQ7VtA5SaoAhpAwuejdlu41W7NkYVSp3Ejoc4eZiIqPQuzv7djb0uT6K+SPh
Wmq4m2UQX3UWU48aDHdFoEeS03mX0ILNZAuDOiW2ZrAmXUVIXwh94VVjp0j3pNGB
fda1mRGk85jZBBenAi0BIhqVYmK1oBRTpOHQpgriGM6SOcJMUhLCeQBcL6fJ+/hu
x1kI6+6bgC5s5lPeYGk/k+XFF6No1pbc6g4UAG/BlWQ8A9g5Uu5ZsvY9cIxHxEtx
2AAXWJ7uLpztxuAryENRVHiiMY7w+FJBXuNbtSW9TYQx3lsVjmEsyiDHaMIVy6V8
r/cuKPtcj0/pDNY1lg4N0DpjPZpISx66viFIzfM5Fg6fiLRtNurzuUCbDj75Xckl
Nx9vrxpgBFfwU4q++HItB2n8HykewusCC3TCs8YNOeHs1yRUvhlEwVswGqtNoKuc
5uGMtR4P0EqhwmU4AMXd
=kk6u
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Samsung DeviceTree ARM64 update for v4.12:
1. Add IR, touchscreen and panel to TM2/TM2E boards.
2. Add proper clock frequency properties to DSI nodes.
* tag 'samsung-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add the burst and esc clock frequency properties to DSI node
arm64: dts: exynos: Add support for S6E3HA2 panel device on TM2 board
arm64: dts: exynos: Add stmfts touchscreen node for TM2 and TM2E
arm64: dts: exynos: Enable ir-spi in the TM2 and TM2E boards
Signed-off-by: Olof Johansson <olof@lixom.net>
Corrections:
* r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC
Cleanup:
* Drop _clk suffix from X12 clock node name for r8a7795 SoC
Enhancements:
* Add reset control properties for r8a779[56]
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY569jAAoJENfPZGlqN0++4kIP/isnugtJf5N1dRc82mxIDd3e
8wAKOI3+gXK6dQPr5HP6nD7YgUWWgj+SKX8G8d/VRxWkBHKVdOBmSq6h/nkY2hg6
XcnbRu+dIB2fthXW4vdvnj1j5gIz1b0Y8aXL5cZSX+5nxeZPfdiZt0n7YSKU2Bg5
wlHXUWhkXYDZfz9wqRmqU2mjkbh5dwqHHYMLcrwazVhvS68XdJvAwUKzrtCfndKv
n727ypPZP5QX569r4Ub1AtY3J3y4F4aMl7eWbh8ZxTJoMYrtLhmq7gms1thmTp77
xVeHFHCDEThREY7NgubisI9oyVEssqkB/8cDbCo6IPvDNNuJ1M5FAfAHNcBQ+2Wg
3PiKDoVXkBL7zuQIl0JjiWPEBKWZkEnictXX+1CsgHZPLnQFAKncYilpvX3jz+Gq
2eETERdgNbx5pEej/mZsyLVFe6TQ5GoSz74YQQkS4KajfIGZmYAgUXL0sIlo3MKi
X1jhQy4Ux41nG+arJPYyx8R+Db9qrDhs43npfe+y5i9D/JbIxASDE4J0RypU993x
H6SEUMDoEG+1dcR4Ez7rCeWm8CG9eVDks0oMZlRaOXbqvPBsy43YvuiYdTEE3x+X
HSJubtalb1pDqe4Fi0DmuOU/2kQf74/mBmD971sjBNupT61e4Q3rW8bwz5pO+45Y
lgLStN9v8ptgyMr+hU4o
=HWqJ
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Second Round of Renesas ARM64 Based SoC DT Updates for v4.12
Corrections:
* r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC
Cleanup:
* Drop _clk suffix from X12 clock node name for r8a7795 SoC
Enhancements:
* Add reset control properties for r8a779[56]
* tag 'renesas-arm64-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name
arm64: dts: r8a7796: Add reset control properties
arm64: dts: r8a7795: Add reset control properties
arm64: dts: r8a7795: Correct SATA device size to 2MiB
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C,
SDHCI and GPIO. It also enables various features on the P2771 devkit.
A small fix is made to the compatible string list for the flow
controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAljmyEETHHRyZWRpbmdA
bnZpZGlhLmNvbQAKCRDdI6zXfz6zof6+D/4q3/aatnXbrQ+nYvcXdSYq+ISOaCEA
Ll23ePKJvTiPGE1+rIy64NyljAdiSFhul6PCFumCaX39J7QoOgY5AE3DvOgx/xEh
RhAqRxlq04rYqTqlNovwgbV0XI8TDYAnuelGrRp6f6gC8J2EqReFIWG9P+11MYcD
Zim6Xzyl42v0u//3oy/JOhE0iEK1/Mv35Wv8VTxHFsh+TMhhm2M+vAFDgFeVv6q0
863ooxrw935FbAR6LRm6cIiyF1EknQ5z7LgDnJVHFke/nAggcItldkgRqijA4C8c
ctJTvigOIZmhoCfF6Jh5fAuPCqhxsvZAoC5h8kWKmqw7tDS4Aysaf8cZDo034yrO
y6HC632iqP3UvNj5WMTExBC4FFwHx6wp/ESdYsxih00F0/hOPsObeorUiQ2DJkjc
0XMWKEXuBWzyRYYFSY1zgs9rq0nmqlX/TL6+Lrz1FPzgMWXFvt9B2cCnssDGa7U6
uzKezAbU8eTg5muawYnStttJROdxbHBaDbRNVkvbtYUV2mYfmfAqVD5RjrssYerD
cLoIU0jgjZa0wk1D0JUX6quT0rvRpmGo013G6Luk01D1jG2udTkNXIexyBtndJmr
ZEuzfRLAAdDo7OpirgcWxpja4m/17Dp/LnLg1tzksHk3UxnrFD83Hrtpgif+ci8x
+t8oScJqGFhgiQ==
=yRy3
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
arm64: tegra: Device tree changes for v4.12-rc1
This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C,
SDHCI and GPIO. It also enables various features on the P2771 devkit.
A small fix is made to the compatible string list for the flow
controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210.
* tag 'tegra-for-4.12-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Update the Tegra132 flowctrl compatible string
arm64: tegra: Add GPU node for Tegra186
arm64: tegra: Enable IOMMU for host1x on Tegra210
arm64: tegra: Enable VIC on Tegra210
arm64: tegra: Add GPIO expanders on P2771
arm64: tegra: Add power monitors on P2771
arm64: tegra: Add GPIO keys on P2771
arm64: tegra: Enable current monitors on P3310
arm64: tegra: Enable SD/MMC slot on P2771
arm64: tegra: Enable SDHCI controllers on P3110
arm64: tegra: Add initial power tree for P3310
arm64: tegra: Enable ethernet on P3310
arm64: tegra: Enable I2C controllers on P3310
arm64: tegra: Invert the PMC interrupt on P3310
arm64: tegra: Add ethernet support for Tegra186
arm64: tegra: Add PMC controller on Tegra186
Signed-off-by: Olof Johansson <olof@lixom.net>
H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.
We then have patches to support the H5 boards on top.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY5guIAAoJEBx+YmzsjxAgCOAP/izjrX7AD/lxwAQ1BtfIuNcK
rSpQ4TjF7hO1r0pN1XoIs538U5uYWiBPhpoL+bxu9cdv33i1jojM6MFMAGfyWES4
bjEHU/dI6zBGeJ/icwSEjP1Wl6N+h6eZwzJ01VQsdc91RZXXqgT2xCVXGIJDtuTw
H/+iwvpF6ZqyTFXzhhx8YH7Aqn0X9+nuy6WALyr7d4awa7uLw0QL54Lr3gJWaGvm
Si/o8SjZU6pLF3KyDlcOwlDem+YD6ghH+eZXa1323xoctPQRuFZTiinnolhxJWFc
w+yhK6PtfR8CJ/WlfEEtMjjYQxeefr6MCQjaPjrY67YwE61PlcOZADAB77DujZ/2
Na47Olqp7vJ1yg19X5W/GlxfWa9P0H0VuRE8ZPMfZXGIHFBTgjHuE+pGds38IDvd
Zr0z/fX9WjTUDK9qFD9JHDL9FAJo7gjNGMMMiUvEjR8xpTJhhmAeAzpgZj+Aa78f
ZOYzu8J1xYf2yT/Xj/lDz7FHcWJEc89go9fX+lc8ILaFcXYvokqjfGnD6+ODf0FW
sO54p1OhjEt8yIEnH2js9C+YCIsuMeZ6e6fHjfp/uVVLPb94fhXKSQGYKRmXPJkK
gEdd2OS+I+diM0BAd2mKRlr57mEoPtkl07yx2E2eqCjIG/8wBN0C76KM9p0yPWof
YAaV+iAHOdsvT43alrXp
=ilmt
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64
Allwinner H5 DT changes for 4.12
H5 patches for 4.12, which are mostly related to reworking the H3 DTSI to
be usable on the arm64 H5 DTSI, that shares almost everything with the H3
but the CPU cores.
We then have patches to support the H5 boards on top.
* tag 'sunxi-dt-h5-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: sunxi: h3/h5: switch apb0-related clocks to r_ccu
arm64: allwinner: h5: enable USB OTG on Orange Pi PC 2 board
arm64: allwinner: h5: add support for the Orange Pi PC 2 board
arm64: allwinner: h5: add Allwinner H5 .dtsi
ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5
arm: sun8i: h3: split Allwinner H3 .dtsi
arm: sun8i: h3: correct the GIC compatible in H3 to gic-400
arm: sun8i: h3: drop pinctrl-a10.h inclusion for H3 DTSI
arm: sun8i: h3: drop skeleton.dtsi inclusion in H3 DTSI
Signed-off-by: Olof Johansson <olof@lixom.net>
Some patches to enable the PRCM block in the A64
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY5gSTAAoJEBx+YmzsjxAguFkQAJkdxquuse8N15nl3E4zbnNs
SbuJt7eVluQgOs1EZUFxKCFfui0I90jzq0C5QDrmkld/+bF5aRU8YrQLetZc/xwg
TovxA2NtpgHlXv32/PKQsMNqSx1mFQuZgLlN+O7yL4q1E6mH2qZCHj/xOz40rrBi
kb3dRKGxJdRt9Hc5l2Sysy8kkQXnGDcn8lA4DuQvTvxDp/TanOKV86VdtMEw6LYR
4TKqnveXgDe48+5a8RdycgevX35HyULTSMJYIlmWXPtc6YtlL1VgzevGMUCcnGt4
EocPwh08ot+x2aQXOBVYgstMFG3RhdPq1VeYfZj32LXFDNCXvDXq0/iYE5u0UozM
m3njtzaQg5FH961NoXbghPwgdsvl2KBR3pjNHMA0LhCDepfIC3I+lDE74o+93kcK
DyKaA8k48pP1VS+K/vJkYwPuMGkJmfhgOrMRKV2ABFKczy6fCX6K5Hcbv2s7csPA
/o7EmG5oLKTBc1cfH3EXSi9uqJB533dxWh0xlahZE0m9h0bjHvCdzwEKqVGHUGJ2
Jz+tSMHNN89v11u6HnzCTJkAXXG5pRTP5khkh6JlI1+E3sOdF0rR0H77fsxjCKXt
2E4i5jUy92fFU0Gd/Jcbfa6T4wYKzFeAaaNd4DjsvvBDeFUU7933VNWd92buc8A7
im9JN0pRe+faD28BuJw9
=5XFn
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt64
Allwinner arm64 DT changes for 4.12
Some patches to enable the PRCM block in the A64
* tag 'sunxi-dt64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: allwinner: a64: add R_PIO pinctrl node
arm64: allwinner: a64: add r_ccu node
Signed-off-by: Olof Johansson <olof@lixom.net>
Two patches to change our Kconfig option and add new options in the
defconfig.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY5flvAAoJEBx+YmzsjxAgcLsP/105kRbJPtbjll3gYoDHZj12
OWBxQMW+bNHY0xGqblrpL5gyl5X7+35a+I1Q2R5TQAintS62YFvwJU0Jq5S7ZhPq
3G2lDGpa2oArOJX63X5ZgY7B9tUuAEzBCLOWtDmS00IMdcH0W7ZzuiJTgpQ9jXQz
bpvW/GvhooGvnzSmOihhqxLy6D1m6d/tV51+8ecZLULFrqPhKcJ6QuAra/fjiaaH
yZh/a3i96EJQEJ7Ksn71Z7deBz0tUZpvASjUvpave/ubIOUkD0hEXVm8P7tp13xt
VmcF+WY6yMmW64qJd/NqRcNBL7aFd8TKvv9siNmasIuLOg/r578mZcr4fKvySH6+
rGe9yxeQHgx06YjvtM6HKnZjzxRccAlbG4OPD9bdFds5SDBfuO92fCrvzYwIoovs
OBE6t5KfLd7gAZuQemlaOYyoGft7Iz0rdRYmwUEjzzHQ1ZvL64gXp7ZbBd84kRUr
B/EDD2LkC9RSST2tshMFnthJy6a8U0dpDagcpsBpLvf2NNhaeibWhvNnn7c4gp4+
UKtrTOSFAMLU0Sr+nwA5vYAlJgKMFce0NxeBD4f1/TA7NNzVkHv6MGh8ghdjsRDH
xUH/8LKX6M9zWB13LUxmOlcpzSeWQ63yYxRB1KpDajs5oUvJ7a0j50FIT+s0CWua
6/FsfcngS7J9uFnmScBh
=twCP
-----END PGP SIGNATURE-----
Merge tag 'sunxi-config64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/arm64
Allwinner arm64 config changes for 4.12
Two patches to change our Kconfig option and add new options in the
defconfig.
* tag 'sunxi-config64-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: defconfig: add Allwinner USB PHY
arm64: only select PINCTRL for Allwinner platforms
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit a8d4636f96 ("arm64: cacheinfo: Remove CCSIDR-based cache
information probing") removed mechanism to extract cache information
based on CCSIDR register as the architecture explicitly states no
inference about the actual sizes of caches based on CCSIDR registers.
Commit 9a802431c5 ("arm64: cacheinfo: add support to override cache
levels via device tree") had already provided options to override cache
information from the device tree.
This patch adds the information about L1 and L2 caches on all variants
of Juno platform.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This patch fixes the following set of warnings on juno.
smb@08000000 unit name should not have leading 0s
sysctl@020000 simple-bus unit address format error, expected "20000"
apbregs@010000 simple-bus unit address format error, expected "10000"
mmci@050000 simple-bus unit address format error, expected "50000"
kmi@060000 simple-bus unit address format error, expected "60000"
kmi@070000 simple-bus unit address format error, expected "70000"
wdt@0f0000 simple-bus unit address format error, expected "f0000"
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Johan Hedberg says:
====================
pull request: bluetooth-next 2017-04-14
Here's the main batch of Bluetooth & 802.15.4 patches for the 4.12
kernel.
- Many fixes to 6LoWPAN, in particular for BLE
- New CA8210 IEEE 802.15.4 device driver (accounting for most of the
lines of code added in this pull request)
- Added Nokia Bluetooth (UART) HCI driver
- Some serdev & TTY changes that are dependencies for the Nokia
driver (with acks from relevant maintainers and an agreement that
these come through the bluetooth tree)
- Support for new Intel Bluetooth device
- Various other minor cleanups/fixes here and there
Please let me know if there are any issues pulling. Thanks.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Unlike normal compat syscall variants, it is needed only for
biarch architectures that have different alignement requirements for
u64 in 32bit and 64bit ABI *and* have __put_user() that won't handle
a store of 64bit value at 32bit-aligned address. We used to have one
such (ia64), but its biarch support has been gone since 2010 (after
being broken in 2008, which went unnoticed since nobody had been using
it).
It had escaped removal at the same time only because back in 2004
a patch that switched several syscalls on amd64 from private wrappers to
generic compat ones had switched to use of compat_sys_getdents64(), which
hadn't needed (or used) a compat wrapper on amd64.
Let's bury it - it's at least 7 years overdue.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Again, a batch that's been sitting a couple of weeks, mostly because I
anticipated a bit more material but it didn't show up -- which is good.
These are all your garden variety fixes for ARM platforms. Most visible issue
fixed here is probably the SMP reset issue on OMAP, the rest are minor stuff.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY877PAAoJEIwa5zzehBx3TaUQAKtE8CSmvdWIk5grVb4MBDfF
rXQ2R7WJF17LtVhIGwz9BPCQXMK+/XcSuXZ8bvUIoMsmOFXutDao7m7COD0z4aNo
CPWk7ceQRzIWvsmturla6aYGmpAbWzdDgQj61LnaFbQrzmJOHVvcJN685+L5NGkZ
8GBrzNmrvVkWz5N+msnrZRIcKpSqGCXrkjUU1EfHgUgNNdTf6BQRQSzVEYBtILEb
9bC3WdS1fosmSdbsBjcxHsAtWMyO64KqhA691+gGTR93wyOuCRgqv+/ucoFB1oi+
yjuhUVHW7Y5/8KOi67+97PwoKpZYpUFHge1/5iPbgEN6SqhOLzPAALGCKT4ONEQz
KmLl//kX1IJZTD/87OegSLDbpS7h2sRYS7FpwgAa1kyYYOHdsZsECzKfhEvgZNHX
Gtl2XLmtELM9quKQ2X8xWvjU5grfSLkng9OhDJ6ZCFhGddvjtHegq8J5diFyq281
qf4n/Gp/OLC9IoPUyZefn5ya77K8UZPNppqtiWTBbT1IuXWbPUVPKmZoCpq3Qwu+
2fdcFa3sIfpzDg9vkTszFAUCFkRqH5Jzy8BfNIQtfSq+pxwyIRWh88a5CV2RvYFB
uHSt5B88YR2PwoyhV2oFpYNkx3vVu9g+A35ClzIRTLhSMi+Ngh2+DcppHY+LficP
m9Hes98dZOv92JgiSaoQ
=C+Hz
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Again, a batch that's been sitting a couple of weeks, mostly because
I anticipated a bit more material but it didn't show up -- which is
good.
These are all your garden variety fixes for ARM platforms.
The most visible issue fixed here is probably the SMP reset issue on
OMAP, the rest are minor stuff"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
arm64: allwinner: a64: add pmu0 regs for USB PHY
ARM: OMAP2+: omap_device: Sync omap_device and pm_runtime after probe defer
reset: add exported __reset_control_get, return NULL if optional
ARM: orion5x: only call into phylib when available
ARM: omap2+: Revert omap-smp.c changes resetting CPU1 during boot
ARM: dts: am335x-evmsk: adjust mmc2 param to allow suspend
ARM: dts: ti: fix PCI bus dtc warnings
ARM: dts: am335x-baltos: disable EEE for Atheros 8035 PHY
ARM: dts: OMAP3: Fix MFG ID EEPROM
ARM: sun8i: a33: add operating-points-v2 property to all nodes
ARM: sun8i: a33: remove highest OPP to fix CPU crashes
This adds the serial slave device for the WL1835 Bluetooth interface.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
The Safexcel EIP197 cryptographic engine is used on some Marvell SoCs,
such as Armada 7040 and Armada 8040. Enable this driver as a module in
the ARM64 defconfig.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Since bbb56c2722 ("arm64: Add detection code for broken .inst support
in binutils"), running any make target that doesn't involve the cross
compiler results in a spurious warning:
$ make ARCH=arm64 menuconfig
arch/arm64/Makefile:43: Detected assembler with broken .inst; disassembly will be unreliable
while
$ make ARCH=arm64 CROSS_COMPILE=aarch64-arm-linux- menuconfig
is silent (assuming your compiler is not affected). That's because
the code that tests for the workaround is always run, irrespective
of the current configuration being available or not.
An easy fix is to make the detection conditional on CONFIG_ARM64
being defined, which is only the case when actually building
something.
Fixes: bbb56c2722 ("arm64: Add detection code for broken .inst support in binutils")
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Enable the cryptographic engine available in the CP110 master on the
Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we
do not support multiple cryptographic engines yet.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Enable the cryptographic engine available in the CP110 master on the
Armada 7040 DB.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add the description of the crypto engine hardware block for the Marvell
Armada 7k and Armada 8k processors; for both the CP110 slave and master.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Now that we have a framework to handle the ACPI bits, make the PMUv3
code use this. The framework is a little different to what was
originally envisaged, and we can drop some unused support code in the
process of moving over to it.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
[will: make armv8_pmu_driver_init static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
When probing via ACPI, we won't know up-front whether a CPU has a PMUv3
compatible PMU. Thus we need to consult ID registers during probe time.
This patch updates our PMUv3 probing code to test for the presence of
PMUv3 functionality before touching an PMUv3-specific registers, and
before updating the struct arm_pmu with PMUv3 data.
When a PMUv3-compatible PMU is not present, probing will return -ENODEV.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Currently the ACPI parking protocol code needs to parse each CPU's MADT
GICC table to extract the mailbox address and so on. Each time we parse
a GICC table, we call back to the parking protocol code to parse it.
This has been fine so far, but we're about to have more code that needs
to extract data from the GICC tables, and adding a callback for each
user is going to get unwieldy.
Instead, this patch ensures that we stash a copy of each CPU's GICC
table at boot time, such that anything needing to parse it can later
request it. This will allow for other parsers of GICC, and for
simplification to the ACPI parking protocol code. Note that we must
store a copy, rather than a pointer, since the core ACPI code
temporarily maps/unmaps tables while iterating over them.
Since we parse the MADT before we know how many CPUs we have (and hence
before we setup the percpu areas), we must use an NR_CPUS sized array.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Jeremy Linton <jeremy.linton@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add pinctrl dtsi file for HiKey960 development board, enable
5 pinmux devices and 1 pinconf device, also include some nodes
of configurations for pins.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The operand is an integer constant, make the constness explicit by
adding the modifier. This is needed for clang to generate valid code
and also works with gcc.
Also change the constraint of the operand from 'I' ("Integer constant
that is valid as an immediate operand in an ADD instruction", AArch64)
to 'i' ("An immediate integer operand").
Based-on-patch-from: Greg Hackmann <ghackmann@google.com>
Signed-off-by: Greg Hackmann <ghackmann@google.com>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
We have 2 modes for dealing with interrupts in the ARM world. We can
either handle them all using hardware acceleration through the vgic or
we can emulate a gic in user space and only drive CPU IRQ pins from
there.
Unfortunately, when driving IRQs from user space, we never tell user
space about events from devices emulated inside the kernel, which may
result in interrupt line state changes, so we lose out on for example
timer and PMU events if we run with user space gic emulation.
Define an ABI to publish such device output levels to userspace.
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We now return HVC_STUB_ERR when a stub hypercall fails, but we
leave whatever was in x0 on success. Zeroing it on return seems
like a good idea.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
Nobody is using __hyp_get_vectors anymore, so let's remove both
implementations (hyp-stub and KVM).
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
With __cpu_reset_hyp_mode having become fairly dumb, there is no
need for kvm_get_idmap_start anymore.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
__cpu_reset_hyp_mode doesn't need to be passed any argument now,
as the hyp-stub implementations are self-contained, and is now
reduced to just calling __hyp_reset_vectors(). Let's drop the
wrapper and use the stub hypercall directly.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
Another missing stub hypercall is HVC_SOFT_RESTART. It turns out
that it is pretty easy to implement in terms of HVC_RESET_VECTORS
(since it needs to turn the MMU off).
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
We are now able to use the hyp stub to reset HYP mode. Time to
kiss __kvm_hyp_reset goodbye, and use __hyp_reset_vectors.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
We now have a full hyp-stub implementation in the KVM init code,
but the main KVM code only supports HVC_GET_VECTORS, which is not
enough.
Instead of reinventing the wheel, let's reuse the init implementation
by branching to the idmap page when called with a hyp-stub hypercall.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
Now that we have an infrastructure to handle hypercalls in the KVM
init code, let's implement HVC_GET_VECTORS there.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
In order to restore HYP mode to its original condition, KVM currently
implements __kvm_hyp_reset(). As we're moving towards a hyp-stub
defined API, it becomes necessary to implement HVC_RESET_VECTORS.
This patch adds the HVC_RESET_VECTORS hypercall to the KVM init
code, which so far lacked any form of hypercall support.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
Let's define a new stub hypercall that resets the HYP configuration
to its default: hyp-stub vectors, and MMU disabled.
Of course, for the hyp-stub itself, this is a trivial no-op.
Hypervisors will have a bit more work to do.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
Comments in asm/virt.h are slightly out of date, so let's align
them with the new behaviour of the code.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
Define a standard return value to be returned when a hyp stub
call fails, and make KVM use it for ARM_EXCEPTION_HYP_GONE
(instead of using a KVM-specific value).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
The EL2 code is not corrupting lr anymore, so don't bother preserving
it in the EL1 trampoline code.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
At the moment, we only save/restore lr if on VHE, as we rely only
the EL1 code to have preserved it in the non-VHE case.
As we're about to get rid of the latter, let's move the save/restore
code to the do_el2_call macro, unifying both code paths.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
When entering the kernel hyp stub, we check whether or not we've
made it here through an HVC instruction, clobbering lr (aka x30)
in the process.
This is completely pointless, as HVC is the only way to get here
(all traps to EL2 are disabled, no interrupt override is applied).
So let's remove this bit of code whose only point is to corrupt
a valuable register.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
If we fail to emulate a mrrc instruction, we:
1) deliver an exception,
2) spit a nastygram on the console,
3) write back some garbage to Rt/Rt2
While 1) and 2) are perfectly acceptable, 3) is out of the scope of
the architecture... Let's mimick the code in kvm_handle_cp_32 and
be more cautious.
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
Instead of considering that a sysreg accessor has failed when
returning false, let's consider that it is *always* successful
(after all, we won't stand for an incomplete emulation).
The return value now simply indicates whether we should skip
the instruction (because it has now been emulated), or if we
should leave the PC alone if the emulation has injected an
exception.
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
PMSWINC_EL0 is a WO register, so let's UNDEF when reading from it
(in the highly hypothetical case where this doesn't UNDEF at EL1).
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reads from write-only system registers are generally confined to
EL1 and not propagated to EL2 (that's what the architecture
mantates). In order to be sure that we have a sane behaviour
even in the unlikely event that we have a broken system, we still
handle it in KVM.
In that case, let's inject an undef into the guest.
Let's also remove write_to_read_only which isn't used anywhere.
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
access_pminten() and access_pmuserenr() can only be accessed when
the CPU is in a priviledged mode. If it is not, let's inject an
UNDEF exception.
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Both pmu_*_el0_disabled() and pmu_counter_idx_valid() perform checks
on the validity of an access, but only return a boolean indicating
if the access is valid or not.
Let's allow these functions to also inject an UNDEF exception if
the access was illegal.
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
There is a lot of duplication in the pmu_*_el0_disabled helpers,
and as we're going to modify them shortly, let's move all the
common stuff in a single function.
No functional change.
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
We don't have to save/restore the VMCR on every entry to/from the guest,
since on GICv2 we can access the control interface from EL1 and on VHE
systems with GICv3 we can access the control interface from KVM running
in EL2.
GICv3 systems without VHE becomes the rare case, which has to
save/restore the register on each round trip.
Note that userspace accesses may see out-of-date values if the VCPU is
running while accessing the VGIC state via the KVM device API, but this
is already the case and it is up to userspace to quiesce the CPUs before
reading the CPU registers from the GIC for an up-to-date view.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
Signed-off-by: Christoffer Dall <cdall@linaro.org>
Add 3 SAS host controller nodes and the dependent subctrl node
to enable the SAS and SATA function for the hip07 SoC.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Two fixes for the recent A33 cpufreq support, and one to fix a missing
register in the A64 USB PHY node.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY5e/6AAoJEBx+YmzsjxAgzZcQALIDcB8ZnbHib3NjHJUFYqLI
k2P32R93xCf1hiUhvhMB97dZNgOXqx4nyO2OabrUr9K++6ZNt7p+lIp1lnmNWnG1
Ali6xu02UHLGHlBjqePYc5FbNbpIOa+0TkiOYvqo6CmLycsjvcbb5Ia3dAILyR/K
NgkdGcsHV96EH4gPNzqchtaqBL/cTidHUZiIZv9Zg5zaSerRYG078VPSQ/qcA/sx
ji/JWta/hAGHpignUzXM9dkaw2a11LEOh7YWU78WPAjRZbidgo7d3Tw7wuvE5+hd
bUVG+T91Im3QEvOixaduw8gZ7R5345gQP2OFnm7eRRXnbQEx242z7lRnRwD/xor+
IHYDj+Psbspeaw1oR3KrVk76neCAOHnb9O8pIXu5eHrMwB34kgUNkRx/0wuvRzu8
fkwPtn403hzJdZa81OUGw3x8x1SndXgWPg2ez7z7Y2HjBF3U1585TvckWNrh+Xib
2dT2PLY7GKwCehAR/dAr/RY4jT95nZC6nfDTRkCchv4HOnSOTLr5W2jlhuwhmuMi
mcbIYhJrWRMZfe+3mg983g5DL4Z6k3lnn+Wv6AInk1TrP4TVsmgdmuCcyx116AsY
ikCtk2SMG6QYUiy2XV5mKokaf+ex2ms0qvEJQestx3yXtU3IXOuI2qqdbTPb8XQS
XsyqK7bEgpmLUe1y3W+z
=lFNZ
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-4.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into fixes
Allwinner fixes for 4.11, bis
Two fixes for the recent A33 cpufreq support, and one to fix a missing
register in the A64 USB PHY node.
* tag 'sunxi-fixes-for-4.11-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: allwinner: a64: add pmu0 regs for USB PHY
ARM: sun8i: a33: add operating-points-v2 property to all nodes
ARM: sun8i: a33: remove highest OPP to fix CPU crashes
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board")
sets the memory size to 2 GB, but this board only has 1 GB DRAM, so change
it to the correct value here.
Fixes: 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
- Allow checking of a CPU-local erratum
- Add CNTVCT_EL0 trap handler
- Define Cortex-A73 MIDR
- Allow an erratum to be match for all revisions of a core
- Add capability to advertise Cortex-A73 erratum 858921
-----BEGIN PGP SIGNATURE-----
iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAljnlbgVHG1hcmMuenlu
Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDx+YP/1OU8GnrVBR2cjEctaTz3s51sPRR
+7j1BZ3pbKnwY3XpM6GJpxc//sSBSphqWZXN5GJZW1lSgw7hpl02mA9rh62G4Xmh
wUqR2hmQ5UdenoR5tE39BZrzMFlef90bA7AZyatSqum6AEQcYPJZEgzOvEvfw/mY
Bc4w73At9OTILRXeZjJZabdeJ4aJLs+6xMfsc9ApgxiZIZ5xhJ7CQzcJFdQ2tFeB
9wYqxkt8i9aZfmj3IX14m3fXISQ4JlXoi8QTBqy7qunCMEFU6jtCwC5aZKj1U3Hh
zebVWomcWMQpFaJw3qxZgjVXftv5r2UsHbMoLo4wFa98Qerr7t9/bGifbFqpKm7S
hA0uzcftUHoQF+l/Qxt9rTlsPKrBMoXjY2XDkKiWP/hqXsXKDBnngKQb2ZFJFT5r
UABMBhqlBQpI2l0/Qn0fL7aEC1xZCVnSgGpAXFvg/Ci7X2K+HH37brt5uNh3vDZI
c5UaWUUycDa5GcCnmoK3QWVeitVW/ydJGaoIT06CKBDrktcpsoO4u4w6CI8xsIJL
RbJwCb72JU5HV7XDpdbc/lLzi30kWceOEUSHrs3dCEnkr41kOunDGm/Xxk/Sm8VL
SeYSx9UotuJvWWozZzVWpLiUSizjh6UB2XWnkSLkT++KA6YPX4L2/hYAw7E3bYVe
FAFoLL7jUYdrjpCF
=XSx4
-----END PGP SIGNATURE-----
Merge tag 'arch-timer-errata-prereq' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into for-next/core
Pre-requisites for the arch timer errata workarounds:
- Allow checking of a CPU-local erratum
- Add CNTVCT_EL0 trap handler
- Define Cortex-A73 MIDR
- Allow an erratum to be match for all revisions of a core
- Add capability to advertise Cortex-A73 erratum 858921
* tag 'arch-timer-errata-prereq' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms:
arm64: cpu_errata: Add capability to advertise Cortex-A73 erratum 858921
arm64: cpu_errata: Allow an erratum to be match for all revisions of a core
arm64: Define Cortex-A73 MIDR
arm64: Add CNTVCT_EL0 trap handler
arm64: Allow checking of a CPU-local erratum
Its value has never changed; we might as well make it part of the ABI instead
of using the return value of KVM_CHECK_EXTENSION(KVM_CAP_COALESCED_MMIO).
Because PPC does not always make MMIO available, the code has to be made
dependent on CONFIG_KVM_MMIO rather than KVM_COALESCED_MMIO_PAGE_OFFSET.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
The use of the contiguous bit by our hugetlb implementation violates
the break-before-make requirements of the architecture and can lead to
silent data corruption or TLB conflict aborts. Once again, disable these
hugetlb sizes whilst it gets worked out.
This reverts commit ab2e1b8923.
Conflicts:
arch/arm64/mm/hugetlbpage.c
Signed-off-by: Will Deacon <will.deacon@arm.com>
Just as we're able to identify a broken platform using some DT
information, let's enable a way to spot the offenders with ACPI.
The difference is that we can only match on some OEM info instead
of implementation-specific properties. So in order to avoid the
insane multiplication of errata structures, we allow an array
of OEM descriptions to be attached to an erratum structure.
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: dann frazier <dann.frazier@canonical.com>
Tested-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Instead of applying a CPU-specific workaround to all CPUs in the system,
allow it to only affect a subset of them (typical big-little case).
This is done by turning the erratum pointer into a per-CPU variable.
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Not all errata need to workaround all access types. Allow them to
be optional.
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Geert Uytterhoeven