mirror of https://gitee.com/openkylin/linux.git
238 Commits
| Author | SHA1 | Message | Date |
|---|---|---|---|
Linus Torvalds
|
e81b594cda |
regmap: Changes for v4.3
This has been a busy release for regmap. By far the biggest set of
changes here are those from Markus Pargmann which implement support for
block transfers in smbus devices. This required quite a bit of
refactoring but leaves us better able to handle odd restrictions that
controllers may have and with better performance on smbus.
Other new features include:
- Fix interactions with lockdep for nested regmaps (eg, when a device
using regmap is connected to a bus where the bus controller has a
separate regmap). Lockdep's default class identification is too
crude to work without help.
- Support for must write bitfield operations, useful for operations
which require writing a bit to trigger them from Kuniori Morimoto.
- Support for delaying during register patch application from Nariman
Poushin.
- Support for overriding cache state via the debugfs implementation
from Richard Fitzgerald.
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Merge tag 'regmap-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap
Pull regmap updates from Mark Brown:
"This has been a busy release for regmap.
By far the biggest set of changes here are those from Markus Pargmann
which implement support for block transfers in smbus devices. This
required quite a bit of refactoring but leaves us better able to
handle odd restrictions that controllers may have and with better
performance on smbus.
Other new features include:
- Fix interactions with lockdep for nested regmaps (eg, when a device
using regmap is connected to a bus where the bus controller has a
separate regmap). Lockdep's default class identification is too
crude to work without help.
- Support for must write bitfield operations, useful for operations
which require writing a bit to trigger them from Kuniori Morimoto.
- Support for delaying during register patch application from Nariman
Poushin.
- Support for overriding cache state via the debugfs implementation
from Richard Fitzgerald"
* tag 'regmap-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap: (25 commits)
regmap: fix a NULL pointer dereference in __regmap_init
regmap: Support bulk reads for devices without raw formatting
regmap-i2c: Add smbus i2c block support
regmap: Add raw_write/read checks for max_raw_write/read sizes
regmap: regmap max_raw_read/write getter functions
regmap: Introduce max_raw_read/write for regmap_bulk_read/write
regmap: Add missing comments about struct regmap_bus
regmap: No multi_write support if bus->write does not exist
regmap: Split use_single_rw internally into use_single_read/write
regmap: Fix regmap_bulk_write for bus writes
regmap: regmap_raw_read return error on !bus->read
regulator: core: Print at debug level on debugfs creation failure
regmap: Fix regmap_can_raw_write check
regmap: fix typos in regmap.c
regmap: Fix integertypes for register address and value
regmap: Move documentation to regmap.h
regmap: Use different lockdep class for each regmap init call
thermal: sti: Add parentheses around bridge->ops->regmap_init call
mfd: vexpress: Add parentheses around bridge->ops->regmap_init call
regmap: debugfs: Fix misuse of IS_ENABLED
...
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Bjorn Helgaas
|
e1d9749730 |
MIPS: Remove "weak" from mips_cdmm_phys_base() declaration
Weak header file declarations are error-prone because they make every
definition weak, and the linker chooses one based on link order (see
|
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Nicolas Boichat
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bbb4d872c7 |
mfd: vexpress: Add parentheses around bridge->ops->regmap_init call
regmap_init(...) is a macro since commit "regmap: Use different lockdep class for each regmap init call". That same name is used as a function pointer: prevent its expansion by adding parentheses around the function pointer. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org> |
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Linus Torvalds
|
f5dcb68086 |
ARM: SoC: driver updates for v4.2
Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses Conflicts: arch/arm64/boot/dts/arm/juno-motherboard.dtsi Trivial add/add conflict with our dt branch. Resolution: take both sides. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVi4RRAAoJEFk3GJrT+8ZljIcQAIsqxM/o0drd90xTJ6ex9h0B RmqVLTDgesHmBacJ+SBsa9/ybFIM1uErByftc1dmKankEQVXW3wcH7keQnoStPT2 zTEjadHgZ/ARYjV/oG5oohjfDZpO1kECVHL8O8RmcWxgzRB3az1IW2eD+dzrga/Y R7K6D8rDHMADIUmv0e0DzvQEbSUYdCx3rBND1qZznwZDP3NoivLkOG5MTraccLbQ ouCRoZtyNYD5Lxk+BHLBepnxAa0Ggc6IjEmiUv8fF2OYdu0OruMliT4rcAtOSmzg 2Y7pP85h8u0CxbJDkOyc+2BELyKo7Hv97XtDNNbRYABTMXdskRIadXt4Sh4mwFtM nvlhB4ovbIX7noECJToEkSAgmStLSUwA3R6+DVdLbeQY4uSuXuTRhiWHMyQB6va9 CdjJDk2RE0dZ77c5ZoUnUDtBe4cULU/n4agpYkKMf/HcpnqMUwZzP4KZbbPMBpgL 0CVTt3YrEcjoU7g0SFHhOGPSgl4yIXKU2eHEscokyFYLrS5zRWepmUEmlSoaWn+W p7pJE65TvOGf2xbaWI+UBeK/3ZG7XAP8qUfhsi7NS4bV6oFCk/foqsWAuru0H7OW 2Gk8fuF0qLgE1eFWQp8BHZ4IUeytoWbnGhhHXh8zH39SKAVncOiAGDNfuEP9CyXJ fZFfruYrnz2emOwj2v9m =02Gm -----END PGP SIGNATURE----- Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Kevin Hilman: "Some of these are for drivers/soc, where we're now putting SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. Some highlights: - simple-mfd: document DT bindings and misc updates - migrate mach-berlin to simple-mfd for clock, pinctrl and reset - memory: support for Tegra132 SoC - memory: introduce tegra EMC driver for scaling memory frequency - misc. updates for ARM CCI and CCN busses" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) drivers: soc: sunxi: Introduce SoC driver to map SRAMs arm-cci: Add aliases for PMU events arm-cci: Add CCI-500 PMU support arm-cci: Sanitise CCI400 PMU driver specific code arm-cci: Abstract handling for CCI events arm-cci: Abstract out the PMU counter details arm-cci: Cleanup PMU driver code arm-cci: Do not enable CCI-400 PMU by default firmware: qcom: scm: Add HDCP Support ARM: berlin: add an ADC node for the BG2Q ARM: berlin: remove useless chip and system ctrl compatibles clk: berlin: drop direct of_iomap of nodes reg property ARM: berlin: move BG2Q clock node ARM: berlin: move BG2CD clock node ARM: berlin: move BG2 clock node clk: berlin: prepare simple-mfd conversion pinctrl: berlin: drop SoC stub provided regmap ARM: berlin: move pinctrl to simple-mfd nodes pinctrl: berlin: prepare to use regmap provided by syscon reset: berlin: drop arch_initcall initialization ... |
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Linus Torvalds
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4aa705b18b |
ARM: SoC: platform support for v4.2
Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC Conflicts: arch/arm/mach-socfpga/core.h Trivial remove/remove conflict with our cleanup branch. Resolution: remove both sides -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVi4RMAAoJEFk3GJrT+8Zl6/kP/1Rv9O++1Kxua6R54Og6AF1J 0miFr2fnUrUWUYg/NVbseRH5bBe6N6ir3SQMfde8W2/QibEjOoEwSwrle+mC/eiq CE0x0gtyRvXMrMU/FWkOvbmmw9uv5oz1z3IHZV6AiecNuSMLUBPfamryikQ8C+d1 O/QZtX543tJQJDOBihO5cuhoVVM37UX0unNmqGsyswlyqTPF8FxcIJAYVNtnxjmj AFaOB0nDJKLKFTiX2Ype2wOxxJX1lrLatNo4W4T+YaaK+i1uCOhgTdSN+n49K7YA KNDFEgZFQqT8VMJyG+eJVeYF+cI7yWQ7lBzIftPUjPk/7+dIHBjWPz2QdjVz3U38 kxncf4S9xGAF5G2rcKe4mFrfT3Y8QLWQpA/jFs06yLwW1O3Hlfq3DzMdGNcF7hth 17LOP8namn9+NepZEp/vAlFzRRypxWWtbkPNBIItkImC6zn0IiGjBy50DE1io27W hmQcnMb7d+0wWl2Y8OmR2lZSB97JiRZkRYMCVHVt+0zGJzp4prLvl9wbjh1VXkPv ERCDJ9nCmZsl7ZVmIXMI7KNXYuPNp7R/QAzCvuSUueswF0qxTAQ0VSSBwRMqvQsQ UUNC6p63VnjUeMUdn2EBsUQZ0Uqw3t2U5TtvooHNt9FkiGsSpwjWrvVD+LItaPoJ GPeeJrJaYQsDvTrO8wjU =ZtPK -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform support updates from Kevin Hilman: "Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits) ARM: zx: Add basic defconfig support for ZX296702 ARM: dts: zx: add an initial zx296702 dts and doc clk: zx: add clock support to zx296702 dt-bindings: Add #defines for ZTE ZX296702 clocks ARM: socfpga: fix build error due to secondary_startup MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS ARM: ep93xx: simone: support for SPI-based MMC/SD cards MAINTAINERS: update Shawn's email to use kernel.org one ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5 ARM: EXYNOS: register power domain driver from core_initcall ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs ARM: SAMSUNG: Constify platform_device_id ARM: EXYNOS: Constify irq_domain_ops ARM: EXYNOS: add coupled cpuidle support for Exynos3250 ARM: EXYNOS: add exynos_get_boot_addr() helper ARM: EXYNOS: add exynos_set_boot_addr() helper ARM: EXYNOS: make exynos_core_restart() less verbose ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout ... |
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Linus Torvalds
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43c9fad942 |
Power management and ACPI material for v4.2-rc1
- ACPICA update to upstream revision 20150515 including basic
support for ACPI 6 features: new ACPI tables introduced by
ACPI 6 (STAO, XENV, WPBT, NFIT, IORT), changes related to the
other tables (DTRM, FADT, LPIT, MADT), new predefined names
(_BTH, _CR3, _DSD, _LPI, _MTL, _PRR, _RDI, _RST, _TFP, _TSN),
fixes and cleanups (Bob Moore, Lv Zheng).
- ACPI device power management core code update to follow ACPI 6
which reflects the ACPI device power management implementation
in Windows (Rafael J Wysocki).
- Rework of the backlight interface selection logic to reduce the
number of kernel command line options and improve the handling
of DMI quirks that may be involved in that and to make the
code generally more straightforward (Hans de Goede).
- Fixes for the ACPI Embedded Controller (EC) driver related to
the handling of EC transactions (Lv Zheng).
- Fix for a regression related to the ACPI resources management
and resulting from a recent change of ACPI initialization code
ordering (Rafael J Wysocki).
- Fix for a system initialization regression related to ACPI
introduced during the 3.14 cycle and caused by running the
code that switches the platform over to the ACPI mode too
early in the initialization sequence (Rafael J Wysocki).
- Support for the ACPI _CCA device configuration object related
to DMA cache coherence (Suravee Suthikulpanit).
- ACPI/APEI fixes and cleanups (Jiri Kosina, Borislav Petkov).
- ACPI battery driver cleanups (Luis Henriques, Mathias Krause).
- ACPI processor driver cleanups (Hanjun Guo).
- Cleanups and documentation update related to the ACPI device
properties interface based on _DSD (Rafael J Wysocki).
- ACPI device power management fixes (Rafael J Wysocki).
- Assorted cleanups related to ACPI (Dominik Brodowski. Fabian
Frederick, Lorenzo Pieralisi, Mathias Krause, Rafael J Wysocki).
- Fix for a long-standing issue causing General Protection Faults
to be generated occasionally on return to user space after resume
from ACPI-based suspend-to-RAM on 32-bit x86 (Ingo Molnar).
- Fix to make the suspend core code return -EBUSY consistently in
all cases when system suspend is aborted due to wakeup detection
(Ruchi Kandoi).
- Support for automated device wakeup IRQ handling allowing drivers
to make their PM support more starightforward (Tony Lindgren).
- New tracepoints for suspend-to-idle tracing and rework of the
prepare/complete callbacks tracing in the PM core (Todd E Brandt,
Rafael J Wysocki).
- Wakeup sources framework enhancements (Jin Qian).
- New macro for noirq system PM callbacks (Grygorii Strashko).
- Assorted cleanups related to system suspend (Rafael J Wysocki).
- cpuidle core cleanups to make the code more efficient (Rafael J
Wysocki).
- powernv/pseries cpuidle driver update (Shilpasri G Bhat).
- cpufreq core fixes related to CPU online/offline that should
reduce the overhead of these operations quite a bit, unless the
CPU in question is physically going away (Viresh Kumar, Saravana
Kannan).
- Serialization of cpufreq governor callbacks to avoid race
conditions in some cases (Viresh Kumar).
- intel_pstate driver fixes and cleanups (Doug Smythies, Prarit
Bhargava, Joe Konno).
- cpufreq driver (arm_big_little, cpufreq-dt, qoriq) updates (Sudeep
Holla, Felipe Balbi, Tang Yuantian).
- Assorted cleanups in cpufreq drivers and core (Shailendra Verma,
Fabian Frederick, Wang Long).
- New Device Tree bindings for representing Operating Performance
Points (Viresh Kumar).
- Updates for the common clock operations support code in the PM
core (Rajendra Nayak, Geert Uytterhoeven).
- PM domains core code update (Geert Uytterhoeven).
- Intel Knights Landing support for the RAPL (Running Average Power
Limit) power capping driver (Dasaratharaman Chandramouli).
- Fixes related to the floor frequency setting on Atom SoCs in the
RAPL power capping driver (Ajay Thomas).
- Runtime PM framework documentation update (Ben Dooks).
- cpupower tool fix (Herton R Krzesinski).
/
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Merge tag 'pm+acpi-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull power management and ACPI updates from Rafael Wysocki:
"The rework of backlight interface selection API from Hans de Goede
stands out from the number of commits and the number of affected
places perspective. The cpufreq core fixes from Viresh Kumar are
quite significant too as far as the number of commits goes and because
they should reduce CPU online/offline overhead quite a bit in the
majority of cases.
From the new featues point of view, the ACPICA update (to upstream
revision 20150515) adding support for new ACPI 6 material to ACPICA is
the one that matters the most as some new significant features will be
based on it going forward. Also included is an update of the ACPI
device power management core to follow ACPI 6 (which in turn reflects
the Windows' device PM implementation), a PM core extension to support
wakeup interrupts in a more generic way and support for the ACPI _CCA
device configuration object.
The rest is mostly fixes and cleanups all over and some documentation
updates, including new DT bindings for Operating Performance Points.
There is one fix for a regression introduced in the 4.1 cycle, but it
adds quite a number of lines of code, it wasn't really ready before
Thursday and you were on vacation, so I refrained from pushing it on
the last minute for 4.1.
Specifics:
- ACPICA update to upstream revision 20150515 including basic support
for ACPI 6 features: new ACPI tables introduced by ACPI 6 (STAO,
XENV, WPBT, NFIT, IORT), changes related to the other tables (DTRM,
FADT, LPIT, MADT), new predefined names (_BTH, _CR3, _DSD, _LPI,
_MTL, _PRR, _RDI, _RST, _TFP, _TSN), fixes and cleanups (Bob Moore,
Lv Zheng).
- ACPI device power management core code update to follow ACPI 6
which reflects the ACPI device power management implementation in
Windows (Rafael J Wysocki).
- rework of the backlight interface selection logic to reduce the
number of kernel command line options and improve the handling of
DMI quirks that may be involved in that and to make the code
generally more straightforward (Hans de Goede).
- fixes for the ACPI Embedded Controller (EC) driver related to the
handling of EC transactions (Lv Zheng).
- fix for a regression related to the ACPI resources management and
resulting from a recent change of ACPI initialization code ordering
(Rafael J Wysocki).
- fix for a system initialization regression related to ACPI
introduced during the 3.14 cycle and caused by running the code
that switches the platform over to the ACPI mode too early in the
initialization sequence (Rafael J Wysocki).
- support for the ACPI _CCA device configuration object related to
DMA cache coherence (Suravee Suthikulpanit).
- ACPI/APEI fixes and cleanups (Jiri Kosina, Borislav Petkov).
- ACPI battery driver cleanups (Luis Henriques, Mathias Krause).
- ACPI processor driver cleanups (Hanjun Guo).
- cleanups and documentation update related to the ACPI device
properties interface based on _DSD (Rafael J Wysocki).
- ACPI device power management fixes (Rafael J Wysocki).
- assorted cleanups related to ACPI (Dominik Brodowski, Fabian
Frederick, Lorenzo Pieralisi, Mathias Krause, Rafael J Wysocki).
- fix for a long-standing issue causing General Protection Faults to
be generated occasionally on return to user space after resume from
ACPI-based suspend-to-RAM on 32-bit x86 (Ingo Molnar).
- fix to make the suspend core code return -EBUSY consistently in all
cases when system suspend is aborted due to wakeup detection (Ruchi
Kandoi).
- support for automated device wakeup IRQ handling allowing drivers
to make their PM support more starightforward (Tony Lindgren).
- new tracepoints for suspend-to-idle tracing and rework of the
prepare/complete callbacks tracing in the PM core (Todd E Brandt,
Rafael J Wysocki).
- wakeup sources framework enhancements (Jin Qian).
- new macro for noirq system PM callbacks (Grygorii Strashko).
- assorted cleanups related to system suspend (Rafael J Wysocki).
- cpuidle core cleanups to make the code more efficient (Rafael J
Wysocki).
- powernv/pseries cpuidle driver update (Shilpasri G Bhat).
- cpufreq core fixes related to CPU online/offline that should reduce
the overhead of these operations quite a bit, unless the CPU in
question is physically going away (Viresh Kumar, Saravana Kannan).
- serialization of cpufreq governor callbacks to avoid race
conditions in some cases (Viresh Kumar).
- intel_pstate driver fixes and cleanups (Doug Smythies, Prarit
Bhargava, Joe Konno).
- cpufreq driver (arm_big_little, cpufreq-dt, qoriq) updates (Sudeep
Holla, Felipe Balbi, Tang Yuantian).
- assorted cleanups in cpufreq drivers and core (Shailendra Verma,
Fabian Frederick, Wang Long).
- new Device Tree bindings for representing Operating Performance
Points (Viresh Kumar).
- updates for the common clock operations support code in the PM core
(Rajendra Nayak, Geert Uytterhoeven).
- PM domains core code update (Geert Uytterhoeven).
- Intel Knights Landing support for the RAPL (Running Average Power
Limit) power capping driver (Dasaratharaman Chandramouli).
- fixes related to the floor frequency setting on Atom SoCs in the
RAPL power capping driver (Ajay Thomas).
- runtime PM framework documentation update (Ben Dooks).
- cpupower tool fix (Herton R Krzesinski)"
* tag 'pm+acpi-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (194 commits)
cpuidle: powernv/pseries: Auto-promotion of snooze to deeper idle state
x86: Load __USER_DS into DS/ES after resume
PM / OPP: Add binding for 'opp-suspend'
PM / OPP: Allow multiple OPP tables to be passed via DT
PM / OPP: Add new bindings to address shortcomings of existing bindings
ACPI: Constify ACPI device IDs in documentation
ACPI / enumeration: Document the rules regarding the PRP0001 device ID
ACPI / video: Make acpi_video_unregister_backlight() private
acpi-video-detect: Remove old API
toshiba-acpi: Port to new backlight interface selection API
thinkpad-acpi: Port to new backlight interface selection API
sony-laptop: Port to new backlight interface selection API
samsung-laptop: Port to new backlight interface selection API
msi-wmi: Port to new backlight interface selection API
msi-laptop: Port to new backlight interface selection API
intel-oaktrail: Port to new backlight interface selection API
ideapad-laptop: Port to new backlight interface selection API
fujitsu-laptop: Port to new backlight interface selection API
eeepc-laptop: Port to new backlight interface selection API
dell-wmi: Port to new backlight interface selection API
...
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Linus Torvalds
|
44d21c3f3a |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto update from Herbert Xu:
"Here is the crypto update for 4.2:
API:
- Convert RNG interface to new style.
- New AEAD interface with one SG list for AD and plain/cipher text.
All external AEAD users have been converted.
- New asymmetric key interface (akcipher).
Algorithms:
- Chacha20, Poly1305 and RFC7539 support.
- New RSA implementation.
- Jitter RNG.
- DRBG is now seeded with both /dev/random and Jitter RNG. If kernel
pool isn't ready then DRBG will be reseeded when it is.
- DRBG is now the default crypto API RNG, replacing krng.
- 842 compression (previously part of powerpc nx driver).
Drivers:
- Accelerated SHA-512 for arm64.
- New Marvell CESA driver that supports DMA and more algorithms.
- Updated powerpc nx 842 support.
- Added support for SEC1 hardware to talitos"
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (292 commits)
crypto: marvell/cesa - remove COMPILE_TEST dependency
crypto: algif_aead - Temporarily disable all AEAD algorithms
crypto: af_alg - Forbid the use internal algorithms
crypto: echainiv - Only hold RNG during initialisation
crypto: seqiv - Add compatibility support without RNG
crypto: eseqiv - Offer normal cipher functionality without RNG
crypto: chainiv - Offer normal cipher functionality without RNG
crypto: user - Add CRYPTO_MSG_DELRNG
crypto: user - Move cryptouser.h to uapi
crypto: rng - Do not free default RNG when it becomes unused
crypto: skcipher - Allow givencrypt to be NULL
crypto: sahara - propagate the error on clk_disable_unprepare() failure
crypto: rsa - fix invalid select for AKCIPHER
crypto: picoxcell - Update to the current clk API
crypto: nx - Check for bogus firmware properties
crypto: marvell/cesa - add DT bindings documentation
crypto: marvell/cesa - add support for Kirkwood and Dove SoCs
crypto: marvell/cesa - add support for Orion SoCs
crypto: marvell/cesa - add allhwsupport module parameter
crypto: marvell/cesa - add support for all armada SoCs
...
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Rafael J. Wysocki
|
ab232ba570 |
Merge branches 'pm-sleep' and 'pm-runtime'
* pm-sleep: PM / sleep: trace_device_pm_callback coverage in dpm_prepare/complete PM / wakeup: add a dummy wakeup_source to record statistics PM / sleep: Make suspend-to-idle-specific code depend on CONFIG_SUSPEND PM / sleep: Return -EBUSY from suspend_enter() on wakeup detection PM / tick: Add tracepoints for suspend-to-idle diagnostics PM / sleep: Fix symbol name in a comment in kernel/power/main.c leds / PM: fix hibernation on arm when gpio-led used with CPU led trigger ARM: omap-device: use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS bus: omap_l3_noc: add missed callbacks for suspend-to-disk PM / sleep: Add macro to define common noirq system PM callbacks PM / sleep: Refine diagnostic messages in enter_state() PM / wakeup: validate wakeup source before activating it. * pm-runtime: PM / Runtime: Update last_busy in rpm_resume PM / runtime: add note about re-calling in during device probe() |
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Arnd Bergmann
|
c9531b4f15 |
Merge tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux into next/soc
Merge "changes for Broadcom SoCs": - Dan fixes an error path in the BCM63xx SMP code - Ray adds the relevant Kconfig selects to enable the Broadcom NAND driver on Cygnus - Kevin provides a change to the Broadcom GISB arbiter driver to make it work with MIPS-based big-endian STB SoCs (this was a long-standing change that had dependencies on code in drivers/of/*) - Gregory enables the use of GPIOLIB for brcmstb SoCs and bumps the number of GPIOs for these platforms * tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux: ARM: brcmstb: Add default gpio number ARM: brcmstb: Select ARCH_WANT_OPTIONAL_GPIOLIB bus: brcmstb_gisb: Honor the "big-endian" and "native-endian" DT properties ARM: BCM: Enable NAND support for iProc SoCs ARM: BCM63xx: fix an error path in bcm63xx_pmb_power_on_cpu() |
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Arnd Bergmann
|
72275b4c08 |
mvebu drivers change for 4.2
mvebu-mbus: add mv_mbus_dram_info_nooverlap() needed for the new Marvell crypto driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlVo26sACgkQCwYYjhRyO9UQ4gCeLb6E7RWXGXtLBXRvRi+1a5Vm GckAn2a/4vAQExwlDsiqHMsM2Iw9Phc7 =1es8 -----END PGP SIGNATURE----- Merge tag 'mvebu-drivers-4.2' of git://git.infradead.org/linux-mvebu into next/drivers Merge "mvebu drivers change for 4.2" from Gregory CLEMENT: mvebu-mbus: add mv_mbus_dram_info_nooverlap() needed for the new Marvell crypto driver * tag 'mvebu-drivers-4.2' of git://git.infradead.org/linux-mvebu: bus: mvebu-mbus: add mv_mbus_dram_info_nooverlap() Based on the earlier bug fixes branch, which contains six other patches already merged into 4.1. |
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Arnd Bergmann
|
8f1ab524b1 |
mvebu fixes for 4.1 (part 3)
Disable unused internal RTC for Mamba from linksys (Armada XP) And 2 commits fixing regressions on mvebu-mbus: - the first one for Kirkwood or Orion SoC - the second one for DMA when the platform have more than 4GB (only possible on Armada XP as far as I know) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlVo2BIACgkQCwYYjhRyO9Vf4ACZAUuChGNGu5zOwme4AHCuimp6 TnYAn2n7DjGJ+0aOHCY6qAsVGCUdnda9 =FvVk -----END PGP SIGNATURE----- Merge tag 'mvebu-fixes-4.1-3' of git://git.infradead.org/linux-mvebu into fixes Merge "mvebu fixes for 4.1 (part 3)" from Gregory CLEMENT: Disable unused internal RTC for Mamba from linksys (Armada XP) And 2 commits fixing regressions on mvebu-mbus: - the first one for Kirkwood or Orion SoC - the second one for DMA when the platform have more than 4GB (only possible on Armada XP as far as I know) * tag 'mvebu-fixes-4.1-3' of git://git.infradead.org/linux-mvebu: Revert "bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window" bus: mvebu-mbus: do not set WIN_CTRL_SYNCBARRIER on non io-coherent platforms. ARM: mvebu: armada-xp-linksys-mamba: Disable internal RTC |
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Suzuki K. Poulose
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e14cfad3fe |
arm-cci: Add aliases for PMU events
Each CCI model have different event/source codes and formats. This patch exports this information via the sysfs, which includes the aliases for the events. The aliases are listed by 'perf list', helping the users to specify the name of the event instead of the binary config values. Each event alias must accompany the 'source' code except for the following cases : 1) CCI-400 - cycles event, doesn't relate to an interface. 2) CCI-500 - Global events to the CCI. (Fixed source code = 0xf) Each CCI model provides two sets of attributes(format and event), which are dynamically populated before registering the PMU, to allow for the appropriate information. Cc: Punit Agrawal <punit.agrawal@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Suzuki K. Poulose
|
a95791efa7 |
arm-cci: Add CCI-500 PMU support
CCI-500 provides 8 event counters which can count any of the supported events independently. The PMU event id is a 9-bit value made of two parts. bits [8:5] - Source port 0x0-0x6 Slave Ports 0x8-0xD Master Ports 0xf Global Events to CCI 0x7,0xe Reserved bits [0:4] - Event code (specific to each type of port) The generic CCI-500 controlling interface remains the same with CCI-400. However there are some differences in the PMU event counters. - No cycle counter - Upto 8 counters(4 in CCI-400) - Each counter area is 64K(4K in CCI400) - The counter0 starts at offset 0x10000 from the base of CCI Cc: Punit Agrawal <punit.agrawal@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Suzuki K. Poulose
|
f4d58938ad |
arm-cci: Sanitise CCI400 PMU driver specific code
Rename CCI400 specific defintions from CCI_xxx to CCI400_xxx. Introduce generic ARM_CCI_PMU to cover common code for handling the CCI PMU. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Suzuki K. Poulose
|
312162900c |
arm-cci: Abstract handling for CCI events
Given that each CCI has different set of interfaces and its associated events, it is good to abstract the validation of the event codes to make it easier to add support for a new CCI model. This patch also abstracts the mapping of a given event to a counter, as there are some special counters for certain specific events. We assume that the fixed hardware counters are always at the beginning, so that we can use cci_model->fixed_hw_events as an upper bound to given idx to check if we need to program the counter for an event. Cc: Punit Agrawal <punit.agrawal@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Suzuki K. Poulose
|
ab5b316d4b |
arm-cci: Abstract out the PMU counter details
Adds the PMU model specific counters to the PMU model abstraction to make it easier to add a new PMU. The patch cleans up the naming convention used all over the code. e.g, CCI_PMU_MAX_HW_EVENTS => maximum number of events that can be counted at any time, which is in fact the maximum number of counters available. Change all such namings to use 'counters' instead of events. This patch also abstracts the following: 1) Size of a PMU event counter area. 2) Maximum number of programmable counters supported by the PMU model 3) Number of counters which counts fixed events (e.g, cycle counter on CCI-400). Also changes some of the static allocation of the data structures to dynamic, to accommodate the number of events supported by a PMU. Gets rid ofthe CCI_PMU_* defines for the model. All such data should be accessed via the model abstraction. Limits the number of counters to the maximum supported by the 'model'. Cc: Punit Agrawal <punit.agrawal@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
|
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Suzuki K. Poulose
|
a1a076d767 |
arm-cci: Cleanup PMU driver code
This patch gets rid of the global struct cci_pmu variable and makes the code use the cci_pmu explicitly. Makes code a bit more robust and reader friendly. Cc: Punit Agrawal <punit.agrawal@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
|
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Suzuki K. Poulose
|
85bbba709d |
arm-cci: Do not enable CCI-400 PMU by default
Do not enable CCI-400 PMU by default and fix the dependency on PERF_EVENTS than HW_PERF_EVENTS. Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Cc: arm@kernel.org Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Kevin Cernekee
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fbf4e262bb |
bus: brcmstb_gisb: Honor the "big-endian" and "native-endian" DT properties
On chips strapped for BE, we'll need to use ioread32be/iowrite32be instead of ioread32/iowrite32. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> |
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Thomas Petazzoni
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bfa1ce5f38 |
bus: mvebu-mbus: add mv_mbus_dram_info_nooverlap()
This commit introduces a variant of the mv_mbus_dram_info() function
called mv_mbus_dram_info_nooverlap(). Both functions are used by
Marvell drivers supporting devices doing DMA, and provide them a
description the DRAM ranges that they need to configure their DRAM
windows.
The ranges provided by the mv_mbus_dram_info() function may overlap
with the I/O windows if there is a lot (>= 4 GB) of RAM
installed. This is not a problem for most of the DMA masters, except
for the upcoming new CESA crypto driver because it does DMA to the
SRAM, which is mapped through an I/O window. For this unit, we need to
have DRAM ranges that do not overlap with the I/O windows.
A first implementation done in commit
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Thomas Petazzoni
|
885dbd154b |
Revert "bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window"
This reverts commit |
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Nicolas Schichan
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8c9e06e647 |
bus: mvebu-mbus: do not set WIN_CTRL_SYNCBARRIER on non io-coherent platforms.
Commit |
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James Hogan
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e21422de81 |
MIPS: Fix CDMM to use native endian MMIO reads
The MIPS Common Device Memory Map (CDMM) is internal to the core and has
native endianness. There is therefore no need to byte swap the accesses
on big endian targets, so convert the CDMM bus driver to use
__raw_readl() rather than readl().
Fixes:
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Pawel Moll
|
e532ffea4a |
bus: arm-ccn: Use hrtimer_start() again
hrtimer_start() will no longer defer already expired timers to the softirq in 4.2, and the __hrtimer_start_range_ns() function is getting removed, causing build errors when both the tip tree and the arm-ccn changes are merged. This changes the code back to using hrtimer_start, which will do the right thing after this branch gets merged with the timers update from tip. As pointed out after a discussion on the mailing list, the result will not be worse than the what was there before you pulled my updates, as the code was using normal hrtimer_start(). It's just when I realised that it should be pinned I looked at what x86 uncore pmu is doing and shamelessly (and probably a bit mindlessly) copied the "do not wakeup" version from there. [arnd: update commit message] Reported-by: Mark Brown <mark.brown@arm.com> Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Grygorii Strashko
|
258d2a1095 |
bus: omap_l3_noc: add missed callbacks for suspend-to-disk
Add missed callbacks needed for proper supporting of suspend-to-disk by using recently introduced macro SET_NOIRQ_SYSTEM_SLEEP_PM_OPS. Signed-off-by: Grygorii Strashko <Grygorii.Strashko@linaro.org> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Pavel Machek <pavel@ucw.cz> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> |
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Arnd Bergmann
|
11f52002bf |
Set of ARM CCN PMU driver updates:
- fixed a nasty bitfield mangling bug - added new hints to the perf userspace tool - pinned events processing to a single PMU - modified events initialisation so they can be rotated now -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJVQ7fuAAoJEL9jRaJfXa5Pr6EH+wd92YXgpFHy4x0O77GdK/gk ErzfFlq/3GX6V+1WkMn0Nfj1vhl/Mq9RF4nSbmEU4c5x0ov48J67b94peo9RChfF +BjaLw0mNijpCvcFYNIOW4qvJr5LKizvaq3uzw7h7AFl24MwRIKrNXJP6qON04sB 9TCekVCWutKORkEmVpl4Wltsb3LpqNwo/ziby2dmgRCsxPeXnOycsk45/4Tc0GSg oR5MXLAuvxvNivNMF83FphiAeqPu1eeSWYkT468qqarr4NWKpbYd6uNTMViVHUcW Yd6pxUwB7dphmLckDOIuJ9QJOfxL263uHaq1taUm1HVp15ldKfWapgVH4hIsUj8= =mXhn -----END PGP SIGNATURE----- Merge tag 'ccn/updates-for-4.2' of git://git.linaro.org/people/pawel.moll/linux into next/drivers Pull "Set of ARM CCN PMU driver updates" from Pawel Moll: - fixed a nasty bitfield mangling bug - added new hints to the perf userspace tool - pinned events processing to a single PMU - modified events initialisation so they can be rotated now * tag 'ccn/updates-for-4.2' of git://git.linaro.org/people/pawel.moll/linux: bus: arm-ccn: Allocate event when it is being added, not initialised bus: arm-ccn: Do not group CCN events with other PMUs bus: arm-ccn: Provide required event arguments bus: arm-ccn: cpumask attribute bus: arm-ccn: Fix node->XP config conversion |
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Mark Salter
|
454be2af5b |
drivers: CCI: fix used_mask init in validate_group()
Currently in validate_group(), there is a static initializer for fake_pmu.used_mask which is based on CPU_BITS_NONE but the used_mask array size is based on CCI_PMU_MAX_HW_EVENTS. CCI_PMU_MAX_HW_EVENTS is not based on NR_CPUS, so CPU_BITS_NONE is not correct and will cause a build failure if NR_CPUS is set high enough to make CPU_BITS_NONE larger than used_mask. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Suman Anna
|
e7309c2673 |
bus: omap_l3_noc: Fix master id address decoding for OMAP5
The L3 Error handling on OMAP5 for the most part is very similar
to that of OMAP4, and had leveraged common data structures and
register layout definitions so far. Upon closer inspection, there
are a few minor differences causing an incorrect decoding and
reporting of the master NIU upon an error:
1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies
11 bits on OMAP5 as against 8 bits on OMAP4, with the master
NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR
field.
2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3
input sources on OMAP5. The common DEBUGSS source is at a
different input on each SoC.
Fix the above issues by using a OMAP5-specific compatible property
and using SoC-specific data where there are differences.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Illia Smyrnov
|
4adf82c355 |
bus: omap_l3_noc: Fix offset for DRA7 CLK1_HOST_CLK1_2 instance
The base address for DRA7 CLK1_HOST_CLK1_2 host instance is 0x44800000, so correct offset is 0x800000. DRA7 TRM rev X(fewb 2015) has updates for this information. With wrong offset these errors are not correctly cleared by the L3 IRQ handler and cause an continuous interrupt scenario and system lockup. Signed-off-by: Illia Smyrnov <illia.smyrnov@globallogic.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> |
|
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Pawel Moll
|
57006d3e6f |
bus: arm-ccn: Allocate event when it is being added, not initialised
To make events rotation possible, they should be allocated when event is being ->added(), not during initialisation. This patch moves the respective code. Signed-off-by: Pawel Moll <pawel.moll@arm.com> |
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Pawel Moll
|
9ce1aa869e |
bus: arm-ccn: Do not group CCN events with other PMUs
Groups must not mix events from different PMUs (software events are allowed). Unfortunately the core does not ensures that, so it is necessary to validate the group at the PMU driver level. Signed-off-by: Pawel Moll <pawel.moll@arm.com> |
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Pawel Moll
|
8f06c51fac |
bus: arm-ccn: Provide required event arguments
Since
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|
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Pawel Moll
|
ffa415245b |
bus: arm-ccn: cpumask attribute
This patch adds a "cpumask" attribute to CCN's event_source class sysfs
directory. Perf user tool uses it to restrict events to the
processor(s) enumerated in this mask.
This patch provides a single CPU mask, making it possible to run "-a"
perf session (previously it would request the same CCN event, for
example cycle counter, on each available core and most likely fail).
Initially the mask is set to the CPU that happened to probe the driver,
but it will be changed when it is hot-un-plugged (active events are
migrated to another CPU then).
Example:
Performance counter stats for 'system wide':
CPU0 2968148 cycles
CPU1 2236736 cycles
CPU2 1797968 cycles
CPU3 1831715 cycles
CPU1 1201850868 ccn/cycles/
1.001241383 seconds time elapsed
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
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Pawel Moll
|
a18f8e97fe |
bus: arm-ccn: Fix node->XP config conversion
Events defined as watchpoints on nodes must have their config values converted so that they apply to the respective node's XP. The function setting new values was using wrong mask for the "port" field, resulting in corrupted value. Fixed now. Cc: stable@vger.kernel.org # 3.17+ Signed-off-by: Pawel Moll <pawel.moll@arm.com> |
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Linus Torvalds
|
7d2b6ef19c |
ARM: SoC driver updates for v4.1
Driver updates for v4.1. Some of these are for drivers/soc, where we find more
and more SoC-specific drivers these days. Some are for other driver subsystems
where we have received acks from the appropriate maintainers.
The larger parts of this branch are:
- MediaTek support for their PMIC wrapper interface, a high-level interface
for talking to the system PMIC over a dedicated I2C interface.
- Qualcomm SCM driver has been moved to drivers/firmware. It's used for CPU
up/down and needs to be in a shared location for arm/arm64 common code.
- Cleanup of ARM-CCI PMU code.
- Anoter set of cleanusp to the OMAP GPMC code.
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for v4.1. Some of these are for drivers/soc, where we
find more and more SoC-specific drivers these days. Some are for
other driver subsystems where we have received acks from the
appropriate maintainers.
The larger parts of this branch are:
- MediaTek support for their PMIC wrapper interface, a high-level
interface for talking to the system PMIC over a dedicated I2C
interface.
- Qualcomm SCM driver has been moved to drivers/firmware. It's used
for CPU up/down and needs to be in a shared location for arm/arm64
common code.
- cleanup of ARM-CCI PMU code.
- another set of cleanusp to the OMAP GPMC code"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits)
soc/mediatek: Remove unused variables
clocksource: atmel-st: select MFD_SYSCON
soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs
arm-cci: Fix CCI PMU event validation
arm-cci: Split the code for PMU vs driver support
arm-cci: Get rid of secure transactions for PMU driver
arm-cci: Abstract the CCI400 PMU specific definitions
arm-cci: Rearrange code for splitting PMU vs driver code
drivers: cci: reject groups spanning multiple HW PMUs
ARM: at91: remove useless include
clocksource: atmel-st: remove mach/hardware dependency
clocksource: atmel-st: use syscon/regmap
ARM: at91: time: move the system timer driver to drivers/clocksource
ARM: at91: properly initialize timer
ARM: at91: at91rm9200: remove deprecated arm_pm_restart
watchdog: at91rm9200: implement restart handler
watchdog: at91rm9200: use the system timer syscon
mfd: syscon: Add atmel system timer registers definition
ARM: at91/dt: declare atmel,at91rm9200-st as a syscon
soc: qcom: gsbi: Add support for ADM CRCI muxing
...
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Linus Torvalds
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e6c81cce56 |
ARM: SoC platform updates for v4.1
Our SoC branch usually contains expanded support for new SoCs and other core
platform code. In this case, that includes:
- Support for the new Annapurna Labs "Alpine" platform
- A rework greatly simplifying adding new platform support to the MCPM
subsystem (Multi-cluster power management)
- Cpuidle and PM improvements for Exynos3250
- Misc updates for Renesas, OMAP, Meson, i.MX. Some of these could have
gone in other branches but ended up here for various reasons.
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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson:
"Our SoC branch usually contains expanded support for new SoCs and
other core platform code. In this case, that includes:
- support for the new Annapurna Labs "Alpine" platform
- a rework greatly simplifying adding new platform support to the
MCPM subsystem (Multi-cluster power management)
- cpuidle and PM improvements for Exynos3250
- misc updates for Renesas, OMAP, Meson, i.MX. Some of these could
have gone in other branches but ended up here for various reasons"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits)
ARM: alpine: add support for generic pci
ARM: Exynos: migrate DCSCB to the new MCPM backend abstraction
ARM: vexpress: migrate DCSCB to the new MCPM backend abstraction
ARM: vexpress: DCSCB: tighten CPU validity assertion
ARM: vexpress: migrate TC2 to the new MCPM backend abstraction
ARM: MCPM: move the algorithmic complexity to the core code
ARM: EXYNOS: allow cpuidle driver usage on Exynos3250 SoC
ARM: EXYNOS: add AFTR mode support for Exynos3250
ARM: EXYNOS: add code for setting/clearing boot flag
ARM: EXYNOS: fix CPU1 hotplug on Exynos3250
ARM: S3C64XX: Use fixed IRQ bases to avoid conflicts on Cragganmore
ARM: cygnus: fix const declaration bcm_cygnus_dt_compat
ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4
ARM: DRA7: hwmod: Add data for GPTimers 13 through 16
ARM: EXYNOS: Remove left over 'extra_save'
ARM: EXYNOS: Constify exynos_pm_data array
ARM: EXYNOS: use static in suspend.c
ARM: EXYNOS: Use platform device name as power domain name
ARM: EXYNOS: add support for async-bridge clocks for pm_domains
ARM: omap-device: add missed callback for suspend-to-disk
...
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Linus Torvalds
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38eb1dbb0d |
ARM: SoC fixes for v4.1
Here's the usual "low-priority fixes that didn't make it into the last
few -rcs, with a twist: We had a fixes pull request that I didn't send
in time to get into 4.0, so we'll send some of them to Greg for -stable as
well.
Contents here is as usual not all that controversial:
- A handful of randconfig fixes from Arnd, in particular for older Samsung
platforms
- Exynos fixes, !SMP building, DTS updates for MMC and lid switch
- Kbuild fix to create output subdirectory for DTB files
- Misc minor fixes for OMAP
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Here's the usual "low-priority fixes that didn't make it into the last
few -rcs, with a twist: We had a fixes pull request that I didn't send
in time to get into 4.0, so we'll send some of them to Greg for
-stable as well.
Contents here is as usual not all that controversial:
- a handful of randconfig fixes from Arnd, in particular for older
Samsung platforms
- Exynos fixes, !SMP building, DTS updates for MMC and lid switch
- Kbuild fix to create output subdirectory for DTB files
- misc minor fixes for OMAP"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
ARM: at91/dt: sama5d3 xplained: add phy address for macb1
kbuild: Create directory for target DTB
ARM: mvebu: Disable CPU Idle on Armada 38x
ARM: DRA7: Enable Cortex A15 errata 798181
ARM: dts: am57xx-beagle-x15: Add thermal map to include fan and tmp102
ARM: dts: DRA7: Add bandgap and related thermal nodes
bus: ocp2scp: SYNC2 value should be changed to 0x6
ARM: dts: am4372: Add "ti,am437x-ocp2scp" as compatible string for OCP2SCP
ARM: OMAP2+: remove superfluous NULL pointer check
ARM: EXYNOS: Fix build breakage cpuidle on !SMP
ARM: dts: fix lid and power pin-functions for exynos5250-spring
ARM: dts: fix mmc node updates for exynos5250-spring
ARM: OMAP4: remove dead kconfig option OMAP4_ERRATA_I688
MAINTAINERS: add OMAP defconfigs under OMAP SUPPORT
ARM: OMAP1: PM: fix some build warnings on 1510-only Kconfigs
ARM: cns3xxx: don't export static symbol
ARM: S3C24XX: avoid a Kconfig warning
ARM: S3C24XX: fix header file inclusions
ARM: S3C24XX: fix building without PM_SLEEP
ARM: S3C24XX: use SAMSUNG_WAKEMASK for s3c2416
...
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Linus Torvalds
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bfaf245022 |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for Linux 4.1. Most
noteworthy:
- Add more Octeon-optimized crypto functions
- Octeon crypto preemption and locking fixes
- Little endian support for Octeon
- Use correct CSR to soft reset Octeons
- Support LEDs on the Octeon-based DSR-1000N
- Fix PCI interrupt mapping for the Octeon-based DSR-1000N
- Mark prom_free_prom_memory() as __init for a number of systems
- Support for Imagination's Pistachio SOC. This includes arch and
CLK bits. I'd like to merge pinctrl bits later
- Improve parallelism of csum_partial for certain pipelines
- Organize DTB files in subdirs like other architectures
- Implement read_sched_clock for all MIPS platforms other than
Octeon
- Massive series of 38 fixes and cleanups for the FPU emulator /
kernel
- Further FPU remulator work to support new features. This sits on a
separate branch which also has been pulled into the 4.1 KVM branch
- Clean up and fixes for the SEAD3 eval board; remove unused file
- Various updates for Netlogic platforms
- A number of small updates for Loongson 3 platforms
- Increase the memory limit for ATH79 platforms to 256MB
- A fair number of fixes and updates for BCM47xx platforms
- Finish the implementation of XPA support
- MIPS FDC support. No, not floppy controller but Fast Debug Channel :)
- Detect the R16000 used in SGI legacy platforms
- Fix Kconfig dependencies for the SSB bus support"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits)
MIPS: Makefile: Fix MIPS ASE detection code
MIPS: asm: elf: Set O32 default FPU flags
MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G
MIPS: Kconfig: Disable SMP/CPS for 64-bit
MIPS: Hibernate: flush TLB entries earlier
MIPS: smp-cps: cpu_set FPU mask if FPU present
MIPS: lose_fpu(): Disable FPU when MSA enabled
MIPS: ralink: add missing symbol for RALINK_ILL_ACC
MIPS: ralink: Fix bad config symbol in PCI makefile.
SSB: fix Kconfig dependencies
MIPS: Malta: Detect and fix bad memsize values
Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores."
MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard.
MIPS: Fix cpu_has_mips_r2_exec_hazard.
MIPS: kernel: entry.S: Set correct ISA level for mips_ihb
MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case
MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes
MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter
MIPS: unaligned: Fix regular load/store instruction emulation for EVA
MIPS: unaligned: Surround load/store macros in do {} while statements
...
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Olof Johansson
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47f36e4921 |
CCI-400 PMU updates
This series reworks some of the CCI-400 PMU code so that it can be used on both ARM and ARM64-based systems, without the need to boot in secure mode on the latter. This paves the way for CCI-500 support in future. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJVFWAiAAoJELescNyEwWM0pK8IALUinCT+Ec/Oi5WwGJaLgQgw exlDFAcmml0xisxglGL7eHcvNBs/j4wFD37mqDUszrGW3jrM+Ex+/cvUzWIlEyZl LjG99ZF2j51LFxDHMgpRwg1aD/NNQsQjwsuHHdCr+NHB5R2C0M4umsgX6Kt6/PE4 95LOnnjBOx4FkMOG9mZElzldUlqnhWd6drjQ9qZQar9VVVewfbR1LH/xQhjrCL0w nwRzJwYj1LnLFO0hBVUAJSfvYltMF9PxBEx0FkyzN7QcuP1tLQ25NmGEvarHP6iZ XpvTZ7akzButyUQbvz/kf6a0agPNUv1HHEqh7/Zddvgm//+p8nEBORuJ/cC6g1E= =UHCi -----END PGP SIGNATURE----- Merge tag 'arm-perf-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/drivers Merge "arm-cci PMU updates for 4.1" from Will Deacon: CCI-400 PMU updates This series reworks some of the CCI-400 PMU code so that it can be used on both ARM and ARM64-based systems, without the need to boot in secure mode on the latter. This paves the way for CCI-500 support in future. * tag 'arm-perf-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: arm-cci: Fix CCI PMU event validation arm-cci: Split the code for PMU vs driver support arm-cci: Get rid of secure transactions for PMU driver arm-cci: Abstract the CCI400 PMU specific definitions arm-cci: Rearrange code for splitting PMU vs driver code drivers: cci: reject groups spanning multiple HW PMUs + Linux 4.0-rc4 Signed-off-by: Olof Johansson <olof@lixom.net> |
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James Hogan
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8286ae0330 |
MIPS: Add CDMM bus support
Add MIPS Common Device Memory Map (CDMM) support in the form of a bus in the standard Linux device model. Each device attached via CDMM is discoverable via an 8-bit type identifier and may contain a number of blocks of memory mapped registers in the CDMM region. IRQs are expected to be handled separately. Due to the per-cpu (per-VPE for MT cores) nature of the CDMM devices, all the driver callbacks take place from workqueues which are run on the right CPU for the device in question, so that the driver doesn't need to be as concerned about which CPU it is running on. Callbacks also exist for when CPUs are taken offline, so that any per-CPU resources used by the driver can be disabled so they don't get forcefully migrated. CDMM devices are created as children of the CPU device they are attached to. Any existing CDMM configuration by the bootloader will be inherited, however platforms wishing to enable CDMM should implement the weak mips_cdmm_phys_base() function (see asm/cdmm.h) so that the bus driver knows where it should put the CDMM region in the physical address space if the bootloader hasn't already enabled it. A mips_cdmm_early_probe() function is also provided to allow early boot or particularly low level code to set up the CDMM region and probe for a specific device type, for example early console or KGDB IO drivers for the EJTAG Fast Debug Channel (FDC) CDMM device. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9599/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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Suzuki K. Poulose
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874c571414 |
arm-cci: Fix CCI PMU event validation
We mask the event with the CCI_PMU_EVENT_MASK, before passing
the config to pmu_validate_hw_event(), which causes extra bits
to be ignored and qualifies an invalid event code as valid.
e.g,
$ perf stat -a -C 0 -e CCI_400/config=0x1ff,name=cycles/ sleep 1
Performance counter stats for 'system wide':
506951142 cycles
1.013879626 seconds time elapsed
where, cycles has an event coding of 0xff. This patch also removes
the unnecessary 'event' mask in pmu_write_register, since the config_base
is set by the pmu code after the event is validated.
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Suzuki K. Poulose
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ee8e5d5fbe |
arm-cci: Split the code for PMU vs driver support
This patch separates the PMU driver code from the low level CCI driver code and enables the PMU driver for ARM64. Introduces config options for both. ARM_CCI400_PORT_CTRL - controls the low level driver code for CCI400 ports. ARM_CCI400_PMU - controls the PMU driver code ARM_CCI400_COMMON - Common defintions for CCI400 This patch also changes: ARM_CCI - common code for probing the CCI devices. This can be used for adding support for newer CCI versions(e.g, CCI-500). Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> |
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Suzuki K. Poulose
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772742a6c7 |
arm-cci: Get rid of secure transactions for PMU driver
Avoid secure transactions while probing the CCI PMU. The existing code makes use of the Peripheral ID2 (PID2) register to determine the revision of the CCI400, which requires a secure transaction. This puts a limitation on the usage of the driver on systems running non-secure Linux(e.g, ARM64). Updated the device-tree binding for cci pmu node to add the explicit revision number for the compatible field. The supported strings are : arm,cci-400-pmu,r0 arm,cci-400-pmu,r1 arm,cci-400-pmu - DEPRECATED. See NOTE below NOTE: If the revision is not mentioned, we need to probe the cci revision, which could be fatal on a platform running non-secure. We need a reliable way to know if we can poke the CCI registers at runtime on ARM32. We depend on 'mcpm_is_available()' when it is available. mcpm_is_available() returns true only when there is a registered driver for mcpm. Otherwise, we assume that we don't have secure access, and skips probing the revision number(ARM64 case). The MCPM should figure out if it is safe to access the CCI. Unfortunately there isn't a reliable way to indicate the same via dtb. This patch doesn't address/change the current situation. It only deals with the CCI-PMU, leaving the assumptions about the secure access as it has been, prior to this patch. Cc: devicetree@vger.kernel.org Cc: Punit Agrawal <punit.agrawal@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> |
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Suzuki K. Poulose
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fc17c83944 |
arm-cci: Abstract the CCI400 PMU specific definitions
CCI400 has different event specifications for PMU, for revsion 0 and revision 1. As of now, we check the revision every single time before using the parameters for the PMU. This patch abstracts the details of the pmu models in a struct (cci_pmu_model) and stores the information in cci_pmu at initialisation time, avoiding multiple probe operations. Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> |
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Suzuki K. Poulose
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f6b9e83ce0 |
arm-cci: Rearrange code for splitting PMU vs driver code
No functional changes, only code re-arrangements for easier split of the PMU code vs low level driver code. Extracts the port handling code to cci_probe_ports(). Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> |
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Suzuki K. Poulose
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b1862199be |
drivers: cci: reject groups spanning multiple HW PMUs
The perf core implicitly rejects events spanning multiple HW PMUs, as in these cases the event->ctx will differ. However this validation is performed after pmu::event_init() is called in perf_init_event(), and thus pmu::event_init() may be called with a group leader from a different HW PMU. The CCI PMU driver does not take this fact into account, and assumes that the any other hardware event belongs to the CCI. There are two issues with it : 1) It is wrong and we should reject such groups. 2) Validation allocates an temporary idx for this non-cci event, which leads to wrong calculation of the counter availability, and eventually lesser number of events in the group. This patch updates the CCI PMU driver to first test for and reject events from other PMUs, which is the right thing to do. Cc: Will Deacon <will.deacon@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Peter Ziljstra (Intel) <peterz@infradead.org> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> |
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Kishon Vijay Abraham I
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cdf61240e1 |
bus: ocp2scp: SYNC2 value should be changed to 0x6
As per the TRMs of AM572x, OMAP4430, OMAP4460, OMAP543x, the value of SYNC2 must be set to 0x6 in order to ensure correct operation. So modified the SYNC2 value of OCP2SCP TIMING register to 0x6 in all the platforms that use OCP2SCP driver except AM437x. Also introduced a new compatible property since we don't want to modify the OCP2SCP TIMING register for AM437x. The sections in TRM where the above caution can be found is mentioned below. AM572x TRM SPRUHZ6 (http://www.ti.com/lit/ug/spruhz6/spruhz6.pdf) under section 26.3.2.2, table 26-26. OMAP4430 TRM SWPU231AP (http://www.ti.com/lit/ug/swpu231ap/swpu231ap.pdf) under section 23.12.6.2.2 , Table 23-1213. OMAP4460 TRM SWPU235AB (http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf) under section 23.12.6.2.2, Table 23-1213. OMAP543x TRM SWPU249 (http://www.ti.com/lit/pdf/swpu249) under section 27.3.2.2, Table 27-27. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> |
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Valentin Rothberg
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d8bf368d06 |
genirq: Remove the deprecated 'IRQF_DISABLED' request_irq() flag entirely
The IRQF_DISABLED flag is a NOOP and has been scheduled for removal since Linux v2.6.36 by commit |
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Alison Chaiken
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52c47b6341 |
bus: imx-weim: improve error handling upon child probe-failure
Probe all children of the WEIM node, reporting any failures. Report failure from parsing of WEIM node itself if probes of all children fail. Signed-off-by: Alison Chaiken <alison_chaiken@mentor.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> |
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Geert Uytterhoeven
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89d463ea10 |
drivers: bus: Add Simple Power-Managed Bus Driver
Add a driver for transparent busses that don't need a real driver, but where the bus controller is part of a PM domain, or under the control of a functional clock. Typically, the bus controller's PM domain and/or clock must be enabled for child devices connected to the bus (either on-SoC or externally) to function. Hence the sole purpose of this driver is to enable its clock and PM domain (if exist(s)), which are specified in the DT and managed from platform and PM domain code, and to probe for child devices. Due to the child-parent relationship with devices connected to the bus, PM domain and clock state transitions are handled in the correct order. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
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Geert Uytterhoeven
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6320c41198 |
drivers: bus: Sort Makefile entries alphabetically
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
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Geert Uytterhoeven
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13fbf3c8d0 |
drivers: bus: Sort Kconfig entries alphabetically
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
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Linus Torvalds
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878ba61aa9 |
ARM: SoC platform changes
New and updated SoC support. Also included are some cleanups where the
platform maintainers hadn't separated cleanups from new developent in
separate branches.
Some of the larger things worth pointing out:
- A large set of changes from Alexandre Belloni and Nicolas Ferre
preparing at91 platforms for multiplatform and cleaning up quite a
bit in the process.
- Removal of CSR's "Marco" SoC platform that never made it out to the
market. We love seeing these since it means the vendor published
support before product was out, which is exactly what we want!
New platforms this release are:
- Conexant Digicolor (CX92755 SoC)
- Hisilicon HiP01 SoC
- CSR/sirf Atlas7 SoC
- ST STiH418 SoC
- Common code changes for Nvidia Tegra132 (64-bit SoC)
We're seeing more and more platforms having a harder time labelling
changes as cleanups vs new development -- which is a good sign that
we've come quite far on the cleanup effort. So over time we might start
combining the cleanup and new-development branches more.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"New and updated SoC support. Also included are some cleanups where
the platform maintainers hadn't separated cleanups from new developent
in separate branches.
Some of the larger things worth pointing out:
- A large set of changes from Alexandre Belloni and Nicolas Ferre
preparing at91 platforms for multiplatform and cleaning up quite a
bit in the process.
- Removal of CSR's "Marco" SoC platform that never made it out to the
market. We love seeing these since it means the vendor published
support before product was out, which is exactly what we want!
New platforms this release are:
- Conexant Digicolor (CX92755 SoC)
- Hisilicon HiP01 SoC
- CSR/sirf Atlas7 SoC
- ST STiH418 SoC
- Common code changes for Nvidia Tegra132 (64-bit SoC)
We're seeing more and more platforms having a harder time labelling
changes as cleanups vs new development -- which is a good sign that
we've come quite far on the cleanup effort. So over time we might
start combining the cleanup and new-development branches more"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits)
ARM: at91/trivial: unify functions and machine names
ARM: at91: remove at91_dt_initialize and machine init_early()
ARM: at91: change board files into SoC files
ARM: at91: remove at91_boot_soc
ARM: at91: move alternative initial mapping to board-dt-sama5.c
ARM: at91: merge all SOC_AT91SAM9xxx
ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init()
ARM: digicolor: select syscon and timer
ARM: zynq: Simplify SLCR initialization
ARM: zynq: PM: Fixed simple typo.
ARM: zynq: Setup default gpio number for Xilinx Zynq
ARM: digicolor: add low level debug support
ARM: initial support for Conexant Digicolor CX92755 SoC
ARM: OMAP2+: Add dm816x hwmod support
ARM: OMAP2+: Add clock domain support for dm816x
ARM: OMAP2+: Add board-generic.c entry for ti81xx
ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
ARM: at91: remove unused mach/system_rev.h
ARM: at91: stop using HAVE_AT91_DBGUx
ARM: at91: fix ordering of SRAM and PM initialization
...
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Tejun Heo
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660e5ec02d |
arm: use %*pb[l] to print bitmaps including cpumasks and nodemasks
printk and friends can now format bitmaps using '%*pb[l]'. cpumask and nodemask also provide cpumask_pr_args() and nodemask_pr_args() respectively which can be used to generate the two printf arguments necessary to format the specified cpu/nodemask. * Line termination only requires one extra space at the end of the buffer. Use PAGE_SIZE - 1 instead of PAGE_SIZE - 2 when formatting. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> |
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Olof Johansson
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5cf920619e |
mvebu fixes for 3.19. (Part 4)
bus: mvebu-mbus: fix support of MBus window 13 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJUwDNwAAoJEOa/DcumaUyEkx0QALyev1odfUDjlRqbpsmIh6c4 sdQFjmIyAoK2SZBsYZE51sFiEBuCw4hF7jMKjgG0JUVOEcrl1pzS6AzdojexinBr +b761WDXNsSijls3Uks7NATtuzY2MMqFhTYgXVHLLmw8/vdu3ZWcK6qXtHpIplbH yw9GzSN5eZtQ10vx4dwCiAONfHbIFGWeeq57kojIvasCutLwWcEWE96s38hAVYFd Vrm7xEng3A+0WOLx6zhTIOZggrNLrv7mAhyhegW7r6PQE44yzyuVeRSnm8ezQ+Rw pcLTt92iVVmA8O8dC7MFWr3/0G2zzCZRpKtRwt1iBhfvtb3cDx8qzWfPSiTwFK80 6sJfFvxrO08qdiduIsJof8sPb/OrcdvCqEw32nOepfrDiv5HP1Z6ReCu98Avitih T42OcFc05NY68A72urr0LXJpx3QA8TDkopBmc8H4Z9E+W9sU0ik2MNhUjkUB+biW 1ll/t1RmFUEENrF+9zKUiqOIvZNacT4kuPPqNx0m9oKB4KhpxuST8qkV79Hthsic ayxsfNWys+wOlips9QBVpdOPd2WMDLOD1WSUpd9D8tATJa8N7J7yFHXo3KJrnwvf CnKTTh37TrZ/Ddd0KRKvAqLLwWrIkgg+xNzaJIpjeewkwtdDDH2ZlhHLg/uUIQ/h wWF0OM0DVmWU5Tq+3kjd =9jyZ -----END PGP SIGNATURE----- Merge tag 'mvebu-fixes-3.19-4' of git://git.infradead.org/linux-mvebu into fixes Merge "mvebu/fixes #3" from Andrew Lunn: mvebu fixes for 3.19. (Part 4) bus: mvebu-mbus: fix support of MBus window 13 * tag 'mvebu-fixes-3.19-4' of git://git.infradead.org/linux-mvebu: bus: mvebu-mbus: fix support of MBus window 13 ARM: mvebu: completely disable hardware I/O coherency Signed-off-by: Olof Johansson <olof@lixom.net> |
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Thomas Petazzoni
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1737cac693 |
bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window
The mvebu-mbus driver reads the SDRAM window registers, and make the information about the DRAM CS configuration available to device drivers using the mv_mbus_dram_info() API. This information is used by the DMA-capable device drivers to program their address decoding windows. Until now, we were basically providing the SDRAM window register details as is. However, it turns out that the DMA capability of the CESA cryptographic engine consists in doing DMA being the DRAM and the crypto SRAM mapped as a MBus window. For this case, it is very important that the SDRAM CS information does not overlap with the MBus bridge window. Therefore, this commit improves the mvebu-mbus driver to make sure we adjust the SDRAM CS information so that it doesn't overlap with the MBus bridge window. This problem was reported by Boris Brezillon, while working on the mv_cesa driver for Armada 37x/38x/XP. We use the memblock memory information to know where the usable RAM is located, as this information is guaranteed to be correct on all SoC variants. We could have used the MBus bridge window registers on Armada 370/XP, but they are not really used on Armada 375/38x (Cortex-A9 based), since the PL310 L2 filtering is used instead to discriminate between RAM accesses and I/O accesses. Therefore, using the memblock information is more generic and works accross the different platforms. Reported-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [Andrew Lunn <andrew@lunn.ch>: Fixed merge conflict] Signed-off-by: Andrew Lunn <andrew@lunn.ch> |
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Michal Mazur
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7fdf3d8a03 |
bus: mvebu-mbus: fix support of MBus window 13 on Armada XP/375/38x
On Armada XP, 375 and 38x the MBus window 13 has the remap capability, like windows 0 to 7. However, the mvebu-mbus driver isn't currently taking into account this special case, which means that when window 13 is actually used, the remap registers are left to 0, making the device using this MBus window unavailable. To make things even more fun, the hardware designers have chosen to put the window 13 remap registers in a completely custom location, using a logic that differs from the one used for all other remappable windows. To solve this problem, this commit: * Adds a SoC specific function to calculate offset of remap registers to the mvebu_mbus_soc_data structure. This function, ->win_remap_offset(), returns the offset of the remap registers, or MVEBU_MBUS_NO_REMAP if the window does not have the remap capability. This new function replaces the previous integer field num_remappable_wins, which was insufficient to encode the special case of window 13. * Adds an implementation of the ->win_remap_offset() function for the various SoC families. Some have 2 first windows that are remapable, some the 4 first, some the 8 first, and then the Armada XP/375/38x case where the 8 first are remapable plus the special window 13. This is implemented in functions generic_mbus_win_remap_2_offset(), generic_mbus_win_remap_4_offset(), generic_mbus_win_remap_8_offset() and armada_xp_mbus_win_remap_offset() respectively. * Change the code to use the ->win_remap_offset() function when accessing the remap registers, and also to use a newly introduced mvebu_mbus_window_is_remappable() helper function that tells whether a given window is remapable or not. * Separate Armada 370 from XP/375/38X because the window 13 of Armada 370 does not support the remap capability. [Thomas: adapted for the mainline kernel, minor clarifications in the code, reword the commit log.] Signed-off-by: Michal Mazur <arg@semihalf.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [Andrew Lunn <andrew@lunn.ch>: Undo the simple fix for stable] Signed-off-by: Andrew Lunn <andrew@lunn.ch> |
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Thomas Petazzoni
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a0b5cd4ac2 |
bus: mvebu-mbus: use automatic I/O synchronization barriers
Instead of using explicit I/O synchronization barriers shoehorned inside the streaming DMA mappings API (in arch/arm/mach-mvebu/coherency.c), we are switching to use automatic I/O synchronization barrier. The primary motivation for this change is that explicit I/O synchronization barriers are not only needed for streaming DMA mappings (which can easily be done by overriding the dma_map_ops), but also for coherent DMA mappings (which is a lot less easy to do, since the kernel assumes such mappings are coherent and don't require any sort of cache maintenance operation to ensure the consistency of the buffers). Switching to automatic I/O synchronization barriers will also allow us to use the existing arm_coherent_dma_ops instead of our custom arm_dma_ops. In order to use automatic I/O synchronization barriers, this commit changes mvebu-mbus in two ways: - It enables automatic I/O synchronization barriers in the 0x84 register of the MBus bridge, by enabling such barriers for all MBus units. This enables automatic barriers for the on-SoC peripherals that are doing DMA. - It enables the SyncEnable bit in the MBus windows, so that PCIe devices also use automatic I/O synchronization barrier. This automatic synchronization barrier relies on the assumption that at least one register of a given hardware unit is read before the driver accesses the DMA mappings modified by this unit. This assumption is guaranteed for PCI devices by vertue of the PCI standard, and we can reasonably verify that this assumption is also true for the limited number of platform drivers doing DMA used on Marvell EBU platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> |
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Andrew Lunn
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38bdf45f4a |
bus: mvebu-mbus: fix support of MBus window 13
On Armada XP, 375 and 38x the MBus window 13 has the remap capability,
like windows 0 to 7. However, the mvebu-mbus driver isn't currently
taking into account this special case, which means that when window 13
is actually used, the remap registers are left to 0, making the device
using this MBus window unavailable.
As a minimal fix for stable, don't use window 13. A full fix will
follow later.
Fixes:
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Abhilash Kesavan
|
896ddd600b |
drivers: bus: check cci device tree node status
The arm-cci driver completes the probe sequence even if the cci node is marked as disabled. Add a check in the driver to honour the cci status in the device tree. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net> |
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Linus Torvalds
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e6b5be2be4 |
Driver core patches for 3.19-rc1
Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEABECAAYFAlSOD20ACgkQMUfUDdst+ylLPACg2QrW1oHhdTMT9WI8jihlHVRM 53kAoLeteByQ3iVwWurwwseRPiWa8+MI =OVRS -----END PGP SIGNATURE----- Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ... |
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Linus Torvalds
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3a647c1d7a |
ARM: SoC driver updates for 3.19
These are changes for drivers that are intimately tied to some SoC
and for some reason could not get merged through the respective
subsystem maintainer tree.
The largest single change here this time around is the Tegra
iommu/memory controller driver, which gets updated to the new
iommu DT binding. More drivers like this are likely to follow
for the following merge window, but we should be able to do
those through the iommu maintainer.
Other notable changes are:
* reset controller drivers from the reset maintainer (socfpga, sti, berlin)
* fixes for the keystone navigator driver merged last time
* at91 rtc driver changes related to the at91 cleanups
* ARM perf driver changes from Will Deacon
* updates for the brcmstb_gisb driver
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"These are changes for drivers that are intimately tied to some SoC and
for some reason could not get merged through the respective subsystem
maintainer tree.
The largest single change here this time around is the Tegra
iommu/memory controller driver, which gets updated to the new iommu DT
binding. More drivers like this are likely to follow for the
following merge window, but we should be able to do those through the
iommu maintainer.
Other notable changes are:
- reset controller drivers from the reset maintainer (socfpga, sti,
berlin)
- fixes for the keystone navigator driver merged last time
- at91 rtc driver changes related to the at91 cleanups
- ARM perf driver changes from Will Deacon
- updates for the brcmstb_gisb driver"
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits)
clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers
clocksource: arch_timer: Fix code to use physical timers when requested
memory: Add NVIDIA Tegra memory controller support
bus: brcmstb_gisb: Add register offset tables for older chips
bus: brcmstb_gisb: Look up register offsets in a table
bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses
bus: brcmstb_gisb: Make the driver buildable on MIPS
of: Add NVIDIA Tegra memory controller binding
ARM: tegra: Move AHB Kconfig to drivers/amba
amba: Add Kconfig file
clk: tegra: Implement memory-controller clock
serial: samsung: Fix serial config dependencies for exynos7
bus: brcmstb_gisb: resolve section mismatch
ARM: common: edma: edma_pm_resume may be unused
ARM: common: edma: add suspend resume hook
powerpc/iommu: Rename iommu_[un]map_sg functions
rtc: at91sam9: add DT bindings documentation
rtc: at91sam9: use clk API instead of relying on AT91_SLOW_CLOCK
ARM: at91: add clk_lookup entry for RTT devices
rtc: at91sam9: rework the Kconfig description
...
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Linus Torvalds
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6cd94d5e57 |
ARM: SoC platform changes for 3.19
New and updated SoC support, notable changes include:
* bcm: brcmstb SMP support
* bcm: initial iproc/cygnus support
* exynos: Exynos4415 SoC support
* exynos: PMU and suspend support for Exynos5420
* exynos: PMU support for Exynos3250
* exynos: pm related maintenance
* imx: new LS1021A SoC support
* imx: vybrid 610 global timer support
* integrator: convert to using multiplatform configuration
* mediatek: earlyprintk support for mt8127/mt8135
* meson: meson8 soc and l2 cache controller support
* mvebu: Armada 38x CPU hotplug support
* mvebu: drop support for prerelease Armada 375 Z1 stepping
* mvebu: extended suspend support, now works on Armada 370/XP
* omap: hwmod related maintenance
* omap: prcm cleanup
* pxa: initial pxa27x DT handling
* rockchip: SMP support for rk3288
* rockchip: add cpu frequency scaling support
* shmobile: r8a7740 power domain support
* shmobile: various small restart, timer, pci apmu changes
* sunxi: Allwinner A80 (sun9i) earlyprintk support
* ux500: power domain support
Overall, a significant chunk of changes, coming mostly from
the usual suspects: omap, shmobile, samsung and mvebu, all of
which already contain a lot of platform specific code in
arch/arm.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
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Arnd Bergmann
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7135466151 |
Merge branch 'brcm/stb-smp-uart' into next/drivers
This resolves a nonobvious merge conflict that I got wrong the first time. * brcm/stb-smp-uart: bus: brcmstb_gisb: save and restore GISB timeout bus: brcmstb_gisb: register the fault code hook ARM: brcmstb: Kconfig: drop unneeded symbol selections ARM: brcmstb: reintroduce SMP support ARM: brcmstb: add debug UART for earlyprintk support Conflicts: drivers/bus/brcmstb_gisb.c Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Florian Fainelli <f.fainelli@gmail.com> |
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Arnd Bergmann
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ab64920c37 |
mvebu SoC suspend changes for v3.19
- Armada 370/XP suspend/resume support
- mvebu SoC driver suspend/resume support
- irqchip
- clocksource
- mbus
- clk
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Merge tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu into next/soc
Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper:
- Armada 370/XP suspend/resume support
- mvebu SoC driver suspend/resume support
- irqchip
- clocksource
- mbus
- clk
* tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann
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136a713d80 |
Merge tag 'arm-soc/for-3.19/brcmstb-drivers' of https://github.com/brcm/linux into next/drivers
This pull request contains the following changes to the Broadcom GISB bus arbiter from Kevin Cernekee: - Extend brcmstb GISB bus driver to work on MIPS (currently ARM-only) and support 65nm and 40nm MIPS-based chips such as: BCM7038, BCM7400 and BCM7435 * tag 'arm-soc/for-3.19/brcmstb-drivers' of https://github.com/brcm/linux: bus: brcmstb_gisb: Add register offset tables for older chips bus: brcmstb_gisb: Look up register offsets in a table bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses bus: brcmstb_gisb: Make the driver buildable on MIPS Conflicts: drivers/bus/brcmstb_gisb.c Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Thomas Petazzoni
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4749c02b8d |
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
On Marvell EBU platforms, when doing suspend/resume, the SDRAM window configuration must be saved on suspend, and restored on resume. However, it needs to be restored on resume *before* re-entering the kernel, because the SDRAM window configuration defines the layout of the memory. For this reason, it cannot simply be done in the ->suspend() and ->resume() hooks of the mvebu-mbus driver. Instead, it needs to be restored by the bootloader "boot info" mechanism used when resuming. This mechanism allows the kernel to define a list of (address, value) pairs when suspending, that the bootloader will restore on resume before jumping back into the kernel. This commit therefore adds a new function to the mvebu-mbus driver, called mvebu_mbus_save_cpu_target(), which will be called by the platform code to make the mvebu-mbus driver save the SDRAM window configuration in a way that can be understood by the bootloader "boot info" mechanism. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-8-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Thomas Petazzoni
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a0e89c02da |
bus: mvebu-mbus: suspend/resume support
This commit extends the mvebu-mbus driver to provide suspend/resume support. Since mvebu-mbus is not a platform_driver, the syscore_ops mechanism is used to get ->suspend() and ->resume() hooks called into the driver. In those hooks, we save and restore the MBus windows state, to make sure after resume all Mbus windows are properly restored. Note that while the state of some windows could be gathered by looking again at the Device Tree (for statically described windows), it is not the case of dynamically described windows such as the PCIe memory and I/O windows. Therefore, we take the simple approach of saving and restoring the registers for all MBus windows. In addition, the commit extends the Device Tree binding of the MBus controller, to control the MBus bridge registers (which define which parts of the physical address space is routed to MBus windows vs. normal RAM memory). Those registers must be saved and restored during suspend/resume. The Device Tree binding extension is made is a backward compatible fashion, but of course, suspend/resume will not work without the Device Tree update. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Kevin Cernekee
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d1d6786846 |
bus: brcmstb_gisb: Add register offset tables for older chips
This will select the appropriate register layout based on the DT "compatible" string. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> |
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Kevin Cernekee
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f80835875d |
bus: brcmstb_gisb: Look up register offsets in a table
There are at least 4 incompatible variations of this hardware block, so let's use the ARB_* constants as a table index instead of hardcoding specific register offsets. Also, allow for the possibility of adding old devices that are missing some of the registers. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> |
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Kevin Cernekee
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2b53eadcea |
bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses
These will be used to abstract out chip-to-chip differences. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> |
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Kevin Cernekee
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dd1d78a11a |
bus: brcmstb_gisb: Make the driver buildable on MIPS
BCM7xxx ARM and MIPS platforms share a similar hardware block for reporting GISB errors, so they both benefit from the use of this driver. Conditionally compile the ARM-specific bus error handler so that the GISB error IRQ handler works on other architectures. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> |
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Florian Fainelli
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2e8a29a1c9 |
bus: brcmstb_gisb: resolve section mismatch
Commit |
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Arnd Bergmann
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b9e0e5a9e0 |
This patch series takes us slightly further on the road to big.LITTLE
support in perf. The main change enabling this is moving the CCI PMU driver away from the arm-pmu abstraction, allowing the arch code to focus specifically on support for CPU PMUs. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJUZeYuAAoJELescNyEwWM0u7QH/1AOiUjffkY3kKFyI4STU2Dw EO/ReouiSfmGpB5VHFwndGweQJPrw1ihViropEZyRo7tlHFJVFxTS8a2HxF+Pv6y JcvGVMrCKvsk1slsuq0hHpOs3SFj6b0EX+fg4iggUo5oNrgSo/qgNeQtNOnUpR7v ZAcMm/N6dKS6ZVwpzmayT0MCwg1HLr8iFuHXWOnwZIQ8WhXSlF6CUOIoRDO/63Ta Dsz/NX6vAGnY1tInKRV/gTcuTihku0qbkLTCMKnd9+jZhZrOIHOtV5XqGvRrlq+t 66oJgsUFtG2FbkmAwnm+sep8Frztj2NLqKIxnKI+72AthrSvmGiPXh8kyUrQRGQ= =gOqc -----END PGP SIGNATURE----- Merge tag 'arm-perf-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/drivers Pull "ARM: perf: updates for 3.19" from Will Deacon: This patch series takes us slightly further on the road to big.LITTLE support in perf. The main change enabling this is moving the CCI PMU driver away from the arm-pmu abstraction, allowing the arch code to focus specifically on support for CPU PMUs. * tag 'arm-perf-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: arm: perf: fold hotplug notifier into arm_pmu arm: perf: dynamically allocate cpu hardware data arm: perf: fold percpu_pmu into pmu_hw_events arm: perf: kill get_hw_events() arm: perf: limit size of accounting data arm: perf: use IDR types for CPU PMUs arm: perf: make PMU probing data-driven arm: perf: add missing pr_info newlines arm: perf: factor out callchain code ARM: perf: use pr_* instead of printk ARM: perf: remove useless return and check of idx in counter handling bus: cci: move away from arm_pmu framework Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Keerthy
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c4cf0935a2 |
bus: omap_l3_noc: Correct returning IRQ_HANDLED unconditionally in the irq handler
Correct returning IRQ_HANDLED unconditionally in the irq handler.
Return IRQ_NONE for some interrupt which we do not expect to be
handled in this handler. This prevents kernel stalling with back
to back spurious interrupts.
Fixes:
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Keerthy
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61b43d4e91 |
bus: omap_l3_noc: Add resume hook to restore context
On certain SoCs such as AM437x SoC, L3_noc error registers are
maintained in power domain such as per domain which looses context as part
of low power state such as RTC+DDR mode. On these platforms when we
mask interrupts which we cannot handle, the source of these interrupts
still remain on resume, however, the flag mux registers now contain
their reset value (unmasked) - this breaks the system with infinite
interrupts since we do not these interrupts to take place ever again.
To handle this: restore the masking of interrupts which we have
already recorded in the system as ones we cannot handle.
Fixes:
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Tony Lindgren
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aa25729cfd |
ARM: OMAP3: Fix errors for omap_l3_smx when booted with device tree
When booting omap3 in device tree mode, we're currently getting the following errors: omap_l3_smx omap_l3_smx.0: couldn't request debug irq omap_l3_smx: probe of omap_l3_smx.0 failed with error -22 This is because we don't have handling in the driver for the compatible property and instead assume platform data being passed. Note that this binding is already documented, and implemented for the related omap_l3_noc driver for omap4 and later. Looks like the binding somehow never got never implemented for this omap_l3_smx driver though. Let's also remove __exit_p to allow binding and unbinding of the driver while at it. Reported-by: Pavel Machek <pavel@ucw.cz> Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> |
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Mark Rutland
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c6f85cb430 |
bus: cci: move away from arm_pmu framework
The ARM CPU PMUs and the ARM CCI PMU are using the same framework despite being substantially different in programming model, which makes it difficult to handle either particularly well. This patch migrates the ARM CCI PMU driver away from the arm_pmu framework, matching the style of the CCN PMU driver and other 'uncore' PMU drivers. This will enable refactoring of the arm_pmu framework to better support CPU PMUs. Event context migration on hotplug is not yet added due to a race on event->ctx in the core perf code. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Will Deacon <will.deacon@arm.com> [will: fix whitespace issues] Signed-off-by: Will Deacon <will.deacon@arm.com> |
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Florian Fainelli
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203bb85ed6 |
bus: brcmstb_gisb: save and restore GISB timeout
When the system enters S3, we will lose the GISB timeout value we have configured, make sure that we do save this timeout value, and restore this timeout value prior to re-enabling interrupts such that the GISB timeout interrupt will fire with the expected timeout. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> |
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Florian Fainelli
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f1bee783dd |
bus: brcmstb_gisb: register the fault code hook
Commit
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Wolfram Sang
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571b8c6adb |
bus: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de> |
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Linus Torvalds
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8b45bc892e |
ARM: SoC driver updates for 3.18
These are changes for drivers that are intimately tied to some SoC
and for some reason could not get merged through the respective
subsystem maintainer tree.
Most of the new code is for the Keystone Navigator driver, which is
new base support that is going to be needed for their hardware
accelerated network driver and other units.
Most of the commits are for moving old code around from at91 and omap
for things that are done in device drivers nowadays.
- at91: move reset, poweroff, memory and clocksource code into drivers
directories
- socfpga: add edac driver (through arm-soc, as requested by Boris)
- omap: move omap-intc code to drivers/irqchip
- sunxi: added an RTC driver for sun6i
- omap: mailbox driver related changes
- keystone: support for the "Navigator" component
- versatile: new reboot, led and soc drivers
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"These are changes for drivers that are intimately tied to some SoC and
for some reason could not get merged through the respective subsystem
maintainer tree.
Most of the new code is for the Keystone Navigator driver, which is
new base support that is going to be needed for their hardware
accelerated network driver and other units.
Most of the commits are for moving old code around from at91 and omap
for things that are done in device drivers nowadays.
- at91: move reset, poweroff, memory and clocksource code into
drivers directories
- socfpga: add edac driver (through arm-soc, as requested by Boris)
- omap: move omap-intc code to drivers/irqchip
- sunxi: added an RTC driver for sun6i
- omap: mailbox driver related changes
- keystone: support for the "Navigator" component
- versatile: new reboot, led and soc drivers"
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (92 commits)
bus: arm-ccn: Fix spurious warning message
leds: add device tree bindings for register bit LEDs
soc: add driver for the ARM RealView
power: reset: driver for the Versatile syscon reboot
leds: add a driver for syscon-based LEDs
drivers/soc: ti: fix build break with modules
MAINTAINERS: Add Keystone Multicore Navigator drivers entry
soc: ti: add Keystone Navigator DMA support
Documentation: dt: soc: add Keystone Navigator DMA bindings
soc: ti: add Keystone Navigator QMSS driver
Documentation: dt: soc: add Keystone Navigator QMSS bindings
rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc
rtc: sun6i: Add sun6i RTC driver
irqchip: omap-intc: remove unnecessary comments
irqchip: omap-intc: correct maximum number or MIR registers
irqchip: omap-intc: enable TURBO idle mode
irqchip: omap-intc: enable IP protection
irqchip: omap-intc: remove unnecesary of_address_to_resource() call
irqchip: omap-intc: comment style cleanup
irqchip: omap-intc: minor improvement to omap_irq_pending()
...
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Pawel Moll
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fa637bf059 |
bus: arm-ccn: Fix spurious warning message
Because CCN's cycle counter always runs, it will generate an interrupt on overflow even if the relevant perf event was not requested, causing a spurious warning message. Fixed now by warning on only normal counter unwanted overflows. Also cleaning the overflow mask at init now, not to warn on event previously requested by firmware. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
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Nishanth Menon
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41fc619dd5 |
bus: omap_l3_noc: Fix connID for OMAP4
Commit |
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Pawel Moll
|
8fb2226435 |
bus: arm-ccn: Move event cleanup routine
The function cleaning up an initialized event was called from the "event_del" handler, instead of being used as the "destroy" callback. In case of events group allocation this caused NULL pointer dereference (as events are added and deleted multiple times then). Fixed now. Signed-off-by: Pawel Moll <mail@pawelmoll.com> Signed-off-by: Kevin Hilman <khilman@linaro.org> |
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Pawel Moll
|
bf87bb12bd |
bus: arm-ccn: Fix warning message
A message warning a user about wrong vc value was printing out port instead. Reported-by: Drew Richardson <drew.richardson@arm.com> Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net> |
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Linus Torvalds
|
10c8e05620 |
ARM: SoC driver changes for 3.17
A handful of driver-related changes. We've had a bunch of them going in through
other branches as well, so it's only a part of what we really have this release.
Larger pieces are:
* Removal of a now unused PWM driver for atmel
- This includes AVR32 changes that have been appropriately acked.
* Performance counter support for the arm CCN interconnect
* OMAP mailbox driver cleanups and consolidation
* PCI and SATA PHY drivers for SPEAr 13xx platforms
* Redefinition (with backwards compatibility!) of PCI DT bindings for Tegra to
better model regulators/power.
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Merge tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson:
"A handful of driver-related changes. We've had a bunch of them going
in through other branches as well, so it's only a part of what we
really have this release.
Larger pieces are:
- Removal of a now unused PWM driver for atmel
[ This includes AVR32 changes that have been appropriately acked ]
- Performance counter support for the arm CCN interconnect
- OMAP mailbox driver cleanups and consolidation
- PCI and SATA PHY drivers for SPEAr 13xx platforms
- Redefinition (with backwards compatibility!) of PCI DT bindings for
Tegra to better model regulators/power"
Note: this merge also fixes up the semantic conflict with the new
calling convention for devm_phy_create(), see commit
|
|
|
Linus Torvalds
|
b3345d7c57 |
ARM: SoC platform changes for 3.17
This is the bulk of new SoC enablement and other platform changes for 3.17:
* Samsung S5PV210 has been converted to DT and multiplatform
* Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
* Kirkwood, one of the popular Marvell platforms, is folded into the
mvebu platform code, removing mach-kirkwood.
* Hwmod data for TI AM43xx and DRA7 platforms.
* More additions of Renesas shmobile platform support
* Removal of plat-samsung contents that can be removed with S5PV210 being
multiplatform/DT-enabled and the other two old platforms being removed.
New platforms (most with only basic support right now):
* Hisilicon X5HD2 settop box chipset is introduced
* Mediatek MT6589 (mobile chipset) is introduced
* Broadcom BCM7xxx settop box chipset is introduced
+ as usual a lot other pieces all over the platform code.
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Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"This is the bulk of new SoC enablement and other platform changes for
3.17:
- Samsung S5PV210 has been converted to DT and multiplatform
- Clock drivers and bindings for some of the lower-end i.MX 1/2
platforms
- Kirkwood, one of the popular Marvell platforms, is folded into the
mvebu platform code, removing mach-kirkwood
- Hwmod data for TI AM43xx and DRA7 platforms
- More additions of Renesas shmobile platform support
- Removal of plat-samsung contents that can be removed with S5PV210
being multiplatform/DT-enabled and the other two old platforms
being removed
New platforms (most with only basic support right now):
- Hisilicon X5HD2 settop box chipset is introduced
- Mediatek MT6589 (mobile chipset) is introduced
- Broadcom BCM7xxx settop box chipset is introduced
+ as usual a lot other pieces all over the platform code"
* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
ARM: hisi: remove smp from machine descriptor
power: reset: move hisilicon reboot code
ARM: dts: Add hix5hd2-dkb dts file.
ARM: debug: Rename Hi3716 to HIX5HD2
ARM: hisi: enable hix5hd2 SoC
ARM: hisi: add ARCH_HISI
MAINTAINERS: add entry for Broadcom ARM STB architecture
ARM: brcmstb: select GISB arbiter and interrupt drivers
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
ARM: configs: enable SMP in bcm_defconfig
ARM: add SMP support for Broadcom mobile SoCs
Documentation: arm: misc updates to Marvell EBU SoC status
Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
ARM: mvebu: fix build without platforms selected
ARM: mvebu: add cpuidle support for Armada 38x
ARM: mvebu: add cpuidle support for Armada 370
cpuidle: mvebu: add Armada 38x support
cpuidle: mvebu: add Armada 370 support
cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
ARM: mvebu: export the SCU address
...
|
|
|
Linus Torvalds
|
44c916d58b |
ARM: SoC cleanups for 3.17
This merge window brings a good size of cleanups on various
platforms. Among the bigger ones:
* Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have
lacked active support for quite a while, and after asking around nobody
showed interest in keeping them around. If needed, they could be
resurrected in the future but it's more likely that we would prefer
reintroduction of them as DT and multiplatform-enabled platforms
instead.
* OMAP4 controller code register define diet. They defined a lot of registers
that were never actually used, etc.
* Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate)
to drivers/soc so it can be shared with 64-bit code. This also converts them
over to traditional driver models where possible.
* Removal of legacy gpio-samsung driver, since the last users have been
removed (moved to pinctrl)
Plus a bunch of smaller changes for various platforms that sort of
dissapear in the diffstat for the above. clps711x cleanups, shmobile
header file refactoring/moves for multiplatform friendliness, some misc
cleanups, etc.
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Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"This merge window brings a good size of cleanups on various platforms.
Among the bigger ones:
- Removal of Samsung s5pc100 and s5p64xx platforms. Both of these
have lacked active support for quite a while, and after asking
around nobody showed interest in keeping them around. If needed,
they could be resurrected in the future but it's more likely that
we would prefer reintroduction of them as DT and
multiplatform-enabled platforms instead.
- OMAP4 controller code register define diet. They defined a lot of
registers that were never actually used, etc.
- Move of some of the Tegra platform code (PMC, APBIO, fuse,
powergate) to drivers/soc so it can be shared with 64-bit code.
This also converts them over to traditional driver models where
possible.
- Removal of legacy gpio-samsung driver, since the last users have
been removed (moved to pinctrl)
Plus a bunch of smaller changes for various platforms that sort of
dissapear in the diffstat for the above. clps711x cleanups, shmobile
header file refactoring/moves for multiplatform friendliness, some
misc cleanups, etc"
* tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits)
drivers: CCI: Correct use of ! and &
video: clcd-versatile: Depend on ARM
video: fix up versatile CLCD helper move
MAINTAINERS: Add sdhci-st file to ARCH/STI architecture
ARM: EXYNOS: Fix build breakge with PM_SLEEP=n
MAINTAINERS: Remove Kirkwood
ARM: tegra: Convert PMC to a driver
soc/tegra: fuse: Set up in early initcall
ARM: tegra: Always lock the CPU reset vector
ARM: tegra: Setup CPU hotplug in a pure initcall
soc/tegra: Implement runtime check for Tegra SoCs
soc/tegra: fuse: fix dummy functions
soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
soc/tegra: Add efuse and apbmisc bindings
soc/tegra: Add efuse driver for Tegra
ARM: tegra: move fuse exports to soc/tegra/fuse.h
ARM: tegra: export apb dma readl/writel
ARM: tegra: Use a function to get the chip ID
ARM: tegra: Sort includes alphabetically
ARM: tegra: Move includes to include/soc/tegra
...
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Pawel Moll
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3e528cb7ba |
bus: arm-ccn: Fix error handling at event allocation
The bitfield allocation function returns error condition as a negative value, but in two cases its result was assigned to an unsigned member of the hw_perf_event structure, thus the error would not be ever detected. Fixed by using an intermediate, signed variable. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net> |
|
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Himangi Saraogi
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fc5130de83 |
drivers: CCI: Correct use of ! and &
In commit
|
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Arnd Bergmann
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ce58d2baf5 |
bus: ARM CCN: add PERF_EVENTS dependency
The CCN driver makes no sense without PERF_EVENTS, and trying to build it when that option is disabled results in compile errors, so it's best to just add a strong Kconfig dependency. Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
|
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Pawel Moll
|
a33b0daab7 |
bus: ARM CCN PMU driver
Driver providing perf backend for ARM Cache Coherent Network interconnect. Supports counting all hardware events and crosspoint watchpoints. Currently works with CCN-504 only, although there should be no changes required for CCN-508 (just impossible to test it now). Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> |
|
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Liu Ying
|
26651c4376 |
bus: imx-weim: populate devices on a simple bus
There could be some memory map devices located in a certain chip select region of the i.MX WEIM. The devices could be attached to a simple bus(for example, a AXI bus) whose root node is one child device tree node of the i.MX WEIM device tree node. There should be a bridge(very likely, software transparent) bewteen the i.MX WEIM and the simple bus. This patch makes the i.MX WEIM driver possible to populate devices on a simple bus. In this way, people may try various IPs(in a FPGA, maybe) outside of i.MX chips with the i.MX WEIM embedded. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> |
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Greg Kroah-Hartman
|
868b60e055 |
Merge branch 'component-for-driver' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into driver-core-next
Russell writes: These updates fix one bug in the component helper where the matched components are not properly cleaned up when the master fails to bind. I'll provide a version of this for stable trees if it's deemed that we need to backport it. The second patch causes the component helper to ignore duplicate matches when adding components - this is something that was originally needed for imx-drm, but since that has now been updated, we no longer need to skip over a component which has already been matched. The final patch starts the process of updating the component helper API to achieve two goals: to allow the API to be more efficient when deferred probing occurs, and to allow for future improvements to the component helper without having a major impact on the users. This represents groundwork for some other changes; once this has been merged, I will then send two further pull requests (one for the staging tree, and one for the DRM tree) to update the drivers to the new API. This will result in these three commits being shared with those trees. |
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Jingoo Han
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c9d53c0f2d |
devres: remove devm_request_and_ioremap()
devm_request_and_ioremap() was obsoleted by the commit
|
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Arnd Bergmann
|
30b6f37df6 |
bus/arm-cci: add dependency on OF && CPU_V7
The arm-cci code uses device tree helpers for initialization that don't work on kernels built without CONFIG_OF. Further, it contains an inline assembly in cci_enable_port_for_self() that uses ARMv7 instructions and fails to build when targetting other ARM instruction set versions. This works around both issues by limiting the scope of the Kconfig symbol to platforms that can actually build this driver cleanly. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Shawn Guo <shawn.guo@linaro.org> |
|
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Linus Torvalds
|
a727eaf64f |
ARM: SoC driver changes
SoC-near driver changes that we're merging through our tree. Mostly because they depend on other changes we have staged, but in some cases because the driver maintainers preferred that we did it this way. This contains a largeish cleanup series of the omap_l3_noc bus driver, cpuidle rework for Exynos, some reset driver conversions and a long branch of TI EDMA fixes and cleanups, with more to come next release. The TI EDMA cleanups is a shared branch with the dmaengine tree, with a handful of Davinci-specific fixes on top. After discussion at last year's KS (and some more on the mailing lists), we are here adding a drivers/soc directory. The purpose of this is to keep per-vendor shared code that's needed by different drivers but that doesn't fit into the MFD (nor drivers/platform) model. We expect to keep merging contents for this hierarchy through arm-soc so we can keep an eye on what the vendors keep adding here and not making it a free-for-all to shove in crazy stuff. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTjOFiAAoJEIwa5zzehBx30RYP/0UE+R8ccdsodunmIDrmQ7QP qFWe1YTWlyXtGBDaPCNfdcU09UYatPKuCv5dJ2ToQCyyFI26PIIhFtnCNXmMuYz+ XPCuqAlJ9hZWx7+j2hXRlyhoZMAaJ5EVVxaK5tnVYXDIfy1Y3xG7i069HD/qGrQp xrV+XofFmpU2VAds6S+SpecFFfYD7n/pJ1bTSgzPfaUsEUyV882dJ3skgs1VpTzQ PnL/0Z2t4ePoP3+6p+F7EnJxemLF5IXrlL0c7hODxQKuMqlzoUluywh6SwOHfCQL u2cc5SFUbbKhExwlGOVibdQMiC0HUOXyRvyYFOIdbv+xNH+Zc/tcoQQ22PWm4Yy1 08qOm3Fr6yw5nH5IT+1wCIFCzJEC/ZHM5B2t+RISFybAMk6Bg1TDYJLmd570zkEL aTLtS5hdmy4h8Ad5FBtwKNyL//6FJJxhbHUu/m0qaE0phq94+78B2M6vbx6757xC kCFlpJsHoN0Tn5c9Q1hpTqI/BHxb4UR7Nf+b8Ox8Veuc9JrS35lzi/rWnGxB5WB0 +1KCA8eih9KXTtksxAte1TmSbMciqW559RUR7dNAPXAMPksY2mJV1I+rg0cRsY3i F90Lnc6LWUM5PYpc4VwiC0sUCLKzTFnpZUELqMOiws3PUblbb0StXuoNo6owbtsK mp1Juxi1n7VhoN9AFVpL =SC+e -----END PGP SIGNATURE----- Merge tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next Pull ARM SoC driver changes from Olof Johansson: "SoC-near driver changes that we're merging through our tree. Mostly because they depend on other changes we have staged, but in some cases because the driver maintainers preferred that we did it this way. This contains a largeish cleanup series of the omap_l3_noc bus driver, cpuidle rework for Exynos, some reset driver conversions and a long branch of TI EDMA fixes and cleanups, with more to come next release. The TI EDMA cleanups is a shared branch with the dmaengine tree, with a handful of Davinci-specific fixes on top. After discussion at last year's KS (and some more on the mailing lists), we are here adding a drivers/soc directory. The purpose of this is to keep per-vendor shared code that's needed by different drivers but that doesn't fit into the MFD (nor drivers/platform) model. We expect to keep merging contents for this hierarchy through arm-soc so we can keep an eye on what the vendors keep adding here and not making it a free-for-all to shove in crazy stuff" * tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits) cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM tty: serial: msm: Remove direct access to GSBI power: reset: keystone-reset: introduce keystone reset driver Documentation: dt: add bindings for keystone pll control controller Documentation: dt: add bindings for keystone reset driver soc: qcom: fix of_device_id table ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos ARM: EXYNOS: Move the driver to drivers/cpuidle directory ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c ARM: EXYNOS: Pass the AFTR callback to the platform_data ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier ARM: EXYNOS: Move the AFTR state function into pm.c ARM: EXYNOS: Encapsulate the AFTR code into a function ARM: EXYNOS: Disable cpuidle for exynos5440 ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle ARM: EXYNOS: Remove ifdef for scu_enable in pm ARM: EXYNOS: Move scu_enable in the cpu_pm notifier ARM: EXYNOS: Use the cpu_pm notifier for pm ... |
|
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Linus Torvalds
|
825f4e0271 |
ARM: SoC updates for 3.16 (part 1)
A quite large set of SoC updates this cycle. In no particular order:
- Multi-cluster power management for Samsung Exynos, adding support for
big.LITTLE CPU switching on EXYNOS5
- SMP support for Marvell Armada 375 and 38x
- SMP rework on Allwinner A31
- Xilinx Zynq support for SOC_BUS, big endian
- Marvell orion5x platform cleanup, modernizing the implementation and
moving to DT.
- _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
that their platform can be enabled in the same kernel binary as most
of the other v7 platforms in the tree. \o/ The work isn't quite complete,
there's some driver fixes still needed, but the basics now work.
New SoC support added:
- Freescale i.MX6SX
- LSI Axxia AXM55xx SoCs
- Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
- STi STIH407
Plus a large set of various smaller updates for different platforms. I'm
probably missing some important one here.
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Merge tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull part one of ARM SoC updates from Olof Johansson:
"A quite large set of SoC updates this cycle. In no particular order:
- Multi-cluster power management for Samsung Exynos, adding support
for big.LITTLE CPU switching on EXYNOS5
- SMP support for Marvell Armada 375 and 38x
- SMP rework on Allwinner A31
- Xilinx Zynq support for SOC_BUS, big endian
- Marvell orion5x platform cleanup, modernizing the implementation
and moving to DT.
- _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
that their platform can be enabled in the same kernel binary as
most of the other v7 platforms in the tree. \o/
The work isn't quite complete, there's some driver fixes still
needed, but the basics now work.
New SoC support added:
- Freescale i.MX6SX
- LSI Axxia AXM55xx SoCs
- Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
- STi STIH407
plus a large set of various smaller updates for different platforms.
I'm probably missing some important one here"
* tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits)
ARM: exynos: don't run exynos4 l2x0 setup on other platforms
ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug
ARM: EXYNOS: mcpm rename the power_down_finish
ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC
ARM: EXYNOS: Enable multi-platform build support
ARM: EXYNOS: Consolidate Kconfig entries
ARM: EXYNOS: Add support for EXYNOS5410 SoC
ARM: EXYNOS: Support secondary CPU boot of Exynos3250
ARM: EXYNOS: Add Exynos3250 SoC ID
ARM: EXYNOS: Add 5800 SoC support
ARM: EXYNOS: initial board support for exynos5260 SoC
clk: exynos5410: register clocks using common clock framework
ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084
ARM: sunxi: allow building without reset controller
Documentation: devicetree: arm: sort enable-method entries
ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE
clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
ARM: dts: axxia: Add reset controller
power: reset: Add Axxia system reset driver
ARM: axxia: Adding defconfig for AXM55xx
...
|
|
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Linus Torvalds
|
0a58471541 |
ARM: SoC cleanups for 3.16
Cleanups for 3.16. Among these are:
- A bunch of misc cleanups for Broadcom platforms, mostly housekeeping
- Enabling Common Clock Framework on the older s3c24xx Samsung chipsets
- Cleanup of the Versatile Express system controller code, moving it to syscon
- Power management cleanups for OMAP platforms
+ a handful of other cleanups across the place
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Merge tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next
Pull ARM SoC cleanups from Olof Johansson:
"Cleanups for 3.16. Among these are:
- a bunch of misc cleanups for Broadcom platforms, mostly
housekeeping
- enabling Common Clock Framework on the older s3c24xx Samsung
chipsets
- cleanup of the Versatile Express system controller code, moving it
to syscon
- power management cleanups for OMAP platforms
plus a handful of other cleanups across the place"
* tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM
clk: samsung: fix build error
ARM: vexpress: refine dependencies for new code
clk: samsung: clk-s3c2410-dlck: do not use PNAME macro as it declares __initdata
cpufreq: exynos: Fix the compile error
ARM: S3C24XX: move debug-macro.S into the common space
ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
ARM: S3C24XX: trim down debug uart handling
ARM: compressed/head.S: remove s3c24xx special case
ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
ARM: EXYNOS: Remove exynos_subsys registration
ARM: EXYNOS: Remove duplicate lines in Makefile
ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
ARM: OMAP4: PRCM: remove references to cm-regbits-44xx.h from PRCM core files
ARM: OMAP3/4: PRM: add support of late_init call to prm_ll_ops
ARM: OMAP3/OMAP4: PRM: add prm_features flags and add IO wakeup under it
ARM: OMAP3/4: PRM: provide io chain reconfig function through irq setup
ARM: OMAP2+: PRM: remove unnecessary cpu_is_XXX calls from prm_init / exit
ARM: OMAP2+: PRCM: cleanup some header includes
...
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