Commit Graph

133 Commits

Author SHA1 Message Date
Ralf Baechle 4483b15916 MIPS: Provide more elevant interface cu2_notifier for CP2 extensions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/1504/
2010-08-05 13:25:59 +01:00
Jesper Nilsson 55dc9d51a8 MIPS: Return after handling coprocessor 2 exception
Breaking here dropped us to the default code which always sends a SIGILL
to the current process, no matter what the CU2 notifier says.

[Ralf: Currently this only hurts on Cavium and possibly some out of tree
platforms.]

Signed-off-by: Jesper Nilsson <jesper@jni.nu>
To: linux-mips@linux-mips.org
To: linux-kernel@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/1391/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05 17:17:33 +01:00
Linus Torvalds 6969a43473 Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (25 commits)
  MIPS: Use GCC __builtin_prefetch() to implement prefetch().
  MIPS: Octeon: Serial port fixes for OCTEON simulator.
  MIPS: Octeon: Get rid of early serial.
  MIPS: AR7: prevent race between clock initialization and devices registration
  MIPS: AR7: use ar7_has_high_vlynq() to determine watchdog base address
  MIPS: BCM63xx: Avoid namespace clash on GPIO_DIR_{IN,OUT}
  MIPS: MTX-1: Update defconfig
  MIPS: BCM47xx: Update defconfig
  MIPS: RB532: Update defconfig
  MIPS: AR7: Update defconfig
  RTC: rtc-cmos: Fix binary mode support
  MIPS: Oprofile: Loongson: Cleanup the comments
  MIPS: Oprofile: Loongson: Cleanup of the macros
  MIPS: Oprofile: Loongson: Remove unused variable from loongson2_cpu_setup()
  MIPS: Oprofile: Loongson: Remove useless parentheses
  MIPS: Oprofile: Loongson: Unify macro for setting events
  MIPS: nofpu and nodsp only affect CPU0
  MIPS: Clean up tables for bootmem allocation
  MIPS: Coding style cleanups of access of FCSR rounding mode bits
  MIPS: Loongson 2F: Add gpio/gpioilb support
  ...
2010-05-21 15:23:54 -07:00
Julia Lawall ed1bbdefc3 MIPS: Use set_cpus_allowed_ptr
From: Julia Lawall <julia@diku.dk>

Use set_cpus_allowed_ptr rather than set_cpus_allowed.

The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@@
expression E1,E2;
@@

- set_cpus_allowed(E1, cpumask_of_cpu(E2))
+ set_cpus_allowed_ptr(E1, cpumask_of(E2))

@@
expression E;
identifier I;
@@

- set_cpus_allowed(E, I)
+ set_cpus_allowed_ptr(E, &I)
// </smpl>

Signed-off-by: Julia Lawall <julia@diku.dk>
To: peterz@infradead.org
To: mingo@elte.hu
To: tglx@linutronix.de
To: oleg@redhat.com
To: linux-mips@linux-mips.org
To: linux-kernel@vger.kernel.org
To: kernel-janitors@vger.kernel.org
Patchwork: http://patchwork.linux-mips.org/patch/1087/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-21 21:31:14 +01:00
Jason Wessel 5dd11d5d47 mips,kgdb: kdb low level trap catch and stack trace
The only way the debugger can handle a trap in inside rcu_lock,
notify_die, or atomic_notifier_call_chain without a recursive fault is
to have a low level "first opportunity handler" do_trap_or_bp() handler.

Generally this will be something the vast majority of folks will not
need, but for those who need it, it is added as a kernel .config
option called KGDB_LOW_LEVEL_TRAP.

Also added was a die notification for oops such that kdb can catch an
oops for analysis.

There appeared to be no obvious way to pass the struct pt_regs from
the original exception back to the stack back tracer, so a special
case was added to show_stack() for when kdb is active because you
generally desire to generally look at the back trace of the original
exception.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-20 21:04:26 -05:00
Sebastian Andrzej Siewior 4f81b01a30 MIPS: Use CKSEG1ADDR for uncached handler
"MIPS: Calculate proper ebase value for 64-bit kernels"
9af43ea080dd5d6c7b34f38261780e5dd43537bc (lmo) rsp.
f6be75d03c (kernel.org) broke some 64-bit
MIPS systems.

Before this we were using XKPHYS/cached as ebase and computed the uncached
xphsys/unchached address for that area. After that commit ebase became a
32-bit compat address and convert does not work anymore.  We now should use
CKSEG1 for this. CKSEG1ADDR does just that in 32-bit and 64-bit.

Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
To: Ralf Baechle <ralf@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/1149/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-04-30 20:52:48 +01:00
Yury Polyanskiy ce384d83d0 MIPS: die() does not call die notifier chain
The MIPS implementation of die() forgets to call notify_die() and thus notifiers
registered via register_die_notifier() are not called.  This results in kgdb not
being activated on exceptions.

The only subtlety is that notify_die declares its regs argument w/o const, so
the const had to be removed from mips die() as well.

[Ralf: Fixed build error for SGI IP22 and IP28 platforms.]

Signed-off-by: Yury Polyanskiy <ypolyans@princeton.edu>
Cc: linux-mips@linux-mips.org
Patchworks: http://patchwork.linux-mips.org/patch/1142/
Acked-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2010-04-30 20:52:45 +01:00
David Daney f6be75d03c MIPS: Calculate proper ebase value for 64-bit kernels
The ebase is relative to CKSEG0 not CAC_BASE.  On a 32-bit kernel they
are the same thing, for a 64-bit kernel they are not.

It happens to kind of work on a 64-bit kernel as they both reference
the same physical memory.  However since the CPU uses the CKSEG0 base,
determining if a J instruction will reach always gives the wrong result
unless we use the same number the CPU uses.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1093/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-04-12 17:26:22 +01:00
Florian Fainelli 92bbe1b988 MIPS: Deal with larger physical offsets
AR7 has a larger physical offset than other MIPS based systems and therefore
needs to setup its handlers beyond the usual KSEG0 range. When running the
kernel in mapped mode this modification is also required. Remove function
comment which is now incorrect.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/889/
Patchwork: http://patchwork.linux-mips.org/patch/932/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:19 +01:00
Florian Fainelli 2d1b6e9551 MIPS: Annotate set_except_vector with __init
All call sites of set_except_vector are already annotated with __init, so
annotate that one too.

Signed-off-by: Regards, Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
To: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/888/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-27 12:53:19 +01:00
Wu Zhangjin f4fc580bec MIPS: Fixup of the r4k timer
As reported by Maxime Bizon, the commit "MIPS: PowerTV: Fix support for
timer interrupts with > 64 external IRQs" have broken the r4k timer
since it didn't initialize the cp0_compare_irq_shift variable used in
c0_compare_int_pending() on the architectures whose cpu_has_mips_r2 is
false.

This patch fixes it via initializing the cp0_compare_irq_shift as the
cp0_compare_irq used in the old c0_compare_int_pending().

Reported-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: David VomLehn <dvomlehn@cisco.com>
Cc: mbizon@freebox.fr
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/922/
Tested-by: Shane McDonald <mcdonald.shane@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-02-10 22:15:42 +01:00
David VomLehn 010c108d7a MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs
The MIPS processor is limited to 64 external interrupt sources. Using a
greater number without IRQ sharing requires reading platform-specific
registers. On such platforms, reading the IntCtl register to determine
which interrupt corresponds to a timer interrupt will not work.

On MIPSR2 systems there is a solution - the TI bit in the Cause register,
specifically indicates that a timer interrupt has occured. This patch uses
that bit to detect interrupts for MIPSR2 processors, which may be expected
to work regardless of how the timer interrupt may be routed in the hardware.

Signed-off-by: David VomLehn (dvomlehn@cisco.com)
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/804/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-01-28 00:03:31 +01:00
Ralf Baechle 137f6f3e28 MIPS: Cleanup signal code initialization
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/709/
2009-12-17 01:57:32 +00:00
Ralf Baechle 69f3a7de1f MIPS: Modularize COP2 handling
Away with the daemons of ifdef; get ready for future COP2 users.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-12-17 01:57:30 +00:00
Ralf Baechle f1e39a4a61 MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler
This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-17 20:07:49 +02:00
David Daney 4bb1a1089e MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.h
We had an ugly #ifdef for Cavium Octeon hwrena bits in traps.c, remove
it to mach-cavium-octeon/cpu-feature-overrides.h

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:31 +01:00
David Daney fbeda19f82 MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.
Some CPUs have implementation dependent rdhwr registers.  Allow them
to be enabled on a per CPU basis.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:31 +01:00
Ralf Baechle b72b7092f8 MIPS: Use BUG_ON() where possible.
Based on original patch by Stoyan Gaydarov <stoyboyker@gmail.com> which
missed a few places.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-30 14:49:44 +02:00
Chris Dearman 9fb4c2b9e0 MIPS: R2: Fix problem with code that incorrectly modifies ebase.
Commit 566f74f6b2 had a change that
incorrectly modified ebase. This backs out the lines that modified
ebase.
In addition, the ebase exception vector is now allocated with correct
alignment and the ebase register updated according to the architecture
specification.

Based on original patch by David VomLehn <dvomlehn@cisco.com>.

Signed-off-by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-23 23:38:05 +01:00
David Daney 8bc6d05b48 MIPS: Read watch registers with interrupts disabled.
If a context switch occurred between the watch exception and reading the
watch registers, it would be possible for the new process to corrupt their
state.  Enabling interrupts only after the watch registers are read avoids
this race.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30 21:32:58 +00:00
Ralf Baechle 42fe7ee31f MIPS: R2: Fix broken installation of cache error handler.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-30 21:32:58 +00:00
David Daney f9bb4cf37a MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.
If on Cavium, be aware of cop2 and hwrena during do_cpu().

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11 09:57:21 +00:00
Ralf Baechle ba3049ed40 MIPS: Switch FPU emulator trap to BREAK instruction.
Arguably using the address error handler has always been ugly.  But with
processors that handle unaligned loads and stores in hardware the
current mechanism ceases to work so switch it to a BREAK instruction and
allocate break code 514 to the FPU emulator.

Yoichi Yuasa provided a build fix for CONFIG_BUG=n.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
2008-10-30 14:44:34 +00:00
David Daney 566f74f6b2 MIPS: Consider value of c0_ebase when computing value of exception base.
It just so happens to be zero on all currently supported systems so this
hasn't bitten yet ...

[Ralf: Original patch from Cavium; handling of set_uncached_handler() and
de-ifdef'ed trap_init() implementation by me.]

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-30 14:44:33 +00:00
David Daney b67b2b7030 MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.
Here we hook up the watch exception handler so that it sends SIGTRAP when
the hardware watch registers are triggered.

Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11 16:18:56 +01:00
Kevin D. Kissell 9cc123631b [MIPS] SMTC: Fix holes in SMTC and FPU affinity support.
Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-03 17:58:58 +01:00
Atsushi Nemoto c65a5480ff [MIPS] Fix potential latency problem due to non-atomic cpu_wait.
If an interrupt happened between checking of NEED_RESCHED and WAIT
instruction, adjust EPC to restart from checking of NEED_RESCHED.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-21 14:52:57 +02:00
Thomas Bogendoerfer e0cee3eea7 [MIPS] Fix WARNING: at kernel/smp.c:290
trap_init issues flush_icache_range(), which uses ipi functions to
get icache flushing done on all cpus. But this is done before interrupts
are enabled and caused WARN_ON messages. This changeset introduces
a new local_flush_icache_range() and uses it before interrupts (and
additional CPUs) are enabled to avoid this problem.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-05 21:24:11 +01:00
Thomas Bogendoerfer 0510617b85 [MIPS] Fix data bus error recovery
With -ffunction-section the entries in __dbe_table aren't no longer
sorted, so the lookup of exception addresses in do_be() failed for
some addresses. To avoid this we now sort __dbe_table.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-05 21:24:11 +01:00
Jason Wessel 8854700115 [MIPS] kgdb: add arch support for the kernel's kgdb core
The new kgdb architecture specific handler registers and unregisters
dynamically for exceptions depending on when you configure a kgdb I/O
driver.

Aside from initializing the exceptions earlier in the boot process,
kgdb should have no impact on a device when it is compiled in so long
as an I/O module is not configured for use.

There have been quite a number of contributors during the existence of
this patch (see arch/mips/kernel/kgdb.c).  Most recently Jason
re-wrote the mips kgdb logic to use the die notification handlers.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-30 21:54:42 +01:00
Ralf Baechle b012cffe7f [MIPS] Replace use of print_symbol with new %sP pointer format.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-15 18:44:33 +01:00
David Daney cb11dfa024 [MIPS] Remove board_watchpoint_handler
It is not used anywhere in tree.

Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-15 18:44:29 +01:00
Thomas Bogendoerfer 10220c8844 [MIPS] Fix check for valid stack pointer during backtrace
The newly added check for valid stack pointer address breaks at least for
64bit kernels.  Use __get_user() for accessing stack content to avoid crashes,
when doing the backtrace.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-06-05 18:13:14 +01:00
Ralf Baechle df2700519c [MIPS] Fix handling of trap and breakpoint instructions
With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp).

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 17:14:33 +01:00
Ralf Baechle 39b8d52542 [MIPS] Add support for MIPS CMP platform.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 17:14:26 +01:00
Chris Dearman bdc94eb41e [MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 17:14:26 +01:00
Ralf Baechle 234fcd1484 [MIPS] Fix loads of section missmatches
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12 14:14:41 +00:00
Chris Dearman 1f5826bd0e [MIPS] Added missing cases for rdhwr emulation
Some of these are architecturally required for R2 processors so lets try
to be bit closer to the real thing.  This also provides access to the
CPU cycle timer, even on multiprocessors.  In that aspect its currently
bug compatible to what would happen on a R2-based SMP.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12 14:14:40 +00:00
Chris Dearman bbaf238b5f [MIPS] Ensure that ST0_FR is never set on a 32 bit kernel
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-12-14 17:34:30 +00:00
Ralf Baechle f6771dbb27 [MIPS] Fix shadow register support.
Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:49 +00:00
Alexey Dobriyan 19c5870c0e Use helpers to obtain task pid in printks (arch code)
One of the easiest things to isolate is the pid printed in kernel log.
There was a patch, that made this for arch-independent code, this one makes
so for arch/xxx files.

It took some time to cross-compile it, but hopefully these are all the
printks in arch code.

Signed-off-by: Alexey Dobriyan <adobriyan@openvz.org>
Signed-off-by: Pavel Emelyanov <xemul@openvz.org>
Cc: <linux-arch@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-10-19 11:53:43 -07:00
Ralf Baechle 42f77542f4 [MIPS] time: Move R4000 clockevent device code to separate configurable file
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-18 18:11:47 +01:00
Maciej W. Rozycki 60b0d65541 [MIPS] SYNC emulation for MIPS I processors
Userland, including the C library and the dynamic linker, is keen to use
the SYNC instruction, even for "generic" MIPS I binaries these days.
Which makes it less than useful on MIPS I processors.

This change adds the emulation, but as our do_ri() infrastructure was not
really prepared to take yet another instruction, I have rewritten it and
its callees slightly as follows.

Now there is only a single place a possible signal is thrown from.  The
place is at the end of do_ri().  The instruction word is fetched in
do_ri() and passed down to handlers.  The handlers are called in sequence
and return a result that lets the caller decide upon further processing.
If the result is positive, then the handler has picked the instruction,
but a signal should be thrown and the result is the signal number.  If the
result is zero, then the handler has successfully simulated the
instruction.  If the result is negative, then the handler did not handle
the instruction; to make it more obvious the calls do not follow the usual
0/-Exxx result convention they now return -1 instead of -EFAULT.

The calculation of the return EPC is now at the beginning.  The reason is
it is easier to handle it there as emulation callees may modify a register
and an instruction may be located in delay slot of a branch whose result
depends on the register.  It has to be undone if a signal is to be raised,
but it is not a problem as this is the slow-path case, and both actions
are done in single places now rather than the former being scattered
through emulation handlers.

The part of do_cpu() being covered follows the changes to do_ri().

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2007-10-17 18:28:47 +01:00
Ralf Baechle eae23f2c2a [MIPS] IP22: Fix warning.
CC      arch/mips/sgi-ip22/ip22-berr.o
arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt':
arch/mips/sgi-ip22/ip22-berr.c💯 warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-16 18:23:47 +01:00
Ralf Baechle 9966db25de [MIPS] Make facility to convert CPU types to strings generally available.
So far /proc/cpuinfo has been the only user but human readable processor
name are more useful than that for proc.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:17 +01:00
Ralf Baechle 49a89efbbb [MIPS] Fix "no space between function name and open parenthesis" warnings.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:15 +01:00
Ralf Baechle 10cc352907 [MIPS] Allow hardwiring of the CPU type to a single type for optimization.
This saves a few k on systems which only ever ship with a single CPU type.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:15 +01:00
Ralf Baechle 641e97f318 [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:05 +01:00
Ralf Baechle ec70f65e3b [MIPS] Kill useless volatile keyword
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:03 +01:00
Thiemo Seufer 948a34cf39 [MIPS] Maintain si_code field properly for FP exceptions
The appended patch adds code to update siginfo_t's si_code field. It
fixes e.g. a floating point overflow regression in the SBCL testsuite.

Signed-off-By: Thiemo Seufer <ths@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-27 02:16:59 +01:00