Suspend to RAM on Odroid XU3/XU4/HC1 family (Exynos5422) causes
imprecise abort:
PM: Syncing filesystems ... done.
Freezing user space processes ... (elapsed 0.003 seconds) done.
OOM killer disabled.
Freezing remaining freezable tasks ... (elapsed 0.003 seconds) done.
wake enabled for irq 139
Disabling non-boot CPUs ...
IRQ51 no longer affine to CPU1
IRQ52 no longer affine to CPU2
IRQ53 no longer affine to CPU3
IRQ54 no longer affine to CPU4
IRQ55 no longer affine to CPU5
IRQ56 no longer affine to CPU6
cpu cpu4: Dropping the link to regulator.40
IRQ57 no longer affine to CPU7
Unhandled fault: external abort on non-linefetch (0x1008) at 0xf081a028
Internal error: : 1008 [#1] PREEMPT SMP ARM
with last call trace in exynos_suspend_enter().
The abort is caused by writing to register in secure part of sysram.
Boards booted under secure firmware (e.g. Hardkernel Odroid boards)
should access non-secure sysram.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Update the documentation about:
1. Usage of PMU_SPARE2 register.
Bootloaders on Exynos542x-based boards often use the register
PMU_SPARE2 (0x908) in the same way as on Exynos3250: as a indicator
the secondary CPU was booted on. The bootloader will set this value
to non-zero, after sucessfull power up of secondary CPU. In the same
time this booted CPU will stuck (spin) waiting for software reset.
2. Exynos542x entry address for secondary CPU boot up after system
suspend (with MCPM enabled and in non-secure mode).
See arch/arm/mach-exynos/mcpm-exynos.c for source code.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Extend the kernel-bootloader interface documentation with usage of
register INFORM1 (0x0804) and different CPU resume address on Exynos542x
family (with Multi-Cluster Power Management enabled).
Additionally add glossary and reformat section titles.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Various boot loaders for Exynos based boards use certain memory
addresses during booting for different purposes. Mostly this is one of
following :
1. as a CPU boot address,
2. for storing magic cookie related to low power mode (AFTR, sleep).
The document, based solely on kernel source code, tries to group the
information scattered over different files. This would help in the
future when adding support for new SoC or when extending features
related to low power modes.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Krzysztof Kozlowski