Commit Graph

57435 Commits

Author SHA1 Message Date
Christoph Hellwig c67fdc1f00 arch: mostly remove <asm/segment.h>
A few architectures use <asm/segment.h> internally, but nothing in
common code does. Remove all the empty or almost empty versions of it,
including the asm-generic one.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-04-23 21:51:40 +02:00
Enric Balletbo i Serra 366391f041 ARM: multi_v7_defconfig: Enable missing drivers for supported Chromebooks
Enable following drivers for merged devices:
- Batteries with BQ27XXX chips for Minnie boards.
- Elan eKTH I2C touchscreen for Minnie boards.
- GPIO charger for all Veyron boards.
- Rockchip SARADC driver for all rk3288 boards.
- Rockchip eFUSE driver for all rk3288 boards.
- TPM security chip for all Veyron boards.
- ChromeOS EC userspace interface for all chromebooks boards.
- ChromeOS EC light and proximity sensors for some chromebooks.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-23 19:53:29 +02:00
Wen Yang fbd7af0415 ARM: rockchip: add missing of_node_put in rockchip_smp_prepare_pmu
The call to of_get_next_child returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.

Detected by coccinelle with the following warnings:
./arch/arm/mach-rockchip/platsmp.c:250:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 241, but without a corresponding object release within this function.
./arch/arm/mach-rockchip/platsmp.c:260:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 241, but without a corresponding object release within this function.
./arch/arm/mach-rockchip/platsmp.c:263:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 241, but without a corresponding object release within this function.

Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-23 19:52:37 +02:00
Ard Biesheuvel e17b1af96b ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache
The EFI stub is entered with the caches and MMU enabled by the
firmware, and once the stub is ready to hand over to the decompressor,
we clean and disable the caches.

The cache clean routines use CP15 barrier instructions, which can be
disabled via SCTLR. Normally, when using the provided cache handling
routines to enable the caches and MMU, this bit is enabled as well.
However, but since we entered the stub with the caches already enabled,
this routine is not executed before we call the cache clean routines,
resulting in undefined instruction exceptions if the firmware never
enabled this bit.

So set the bit explicitly in the EFI entry code, but do so in a way that
guarantees that the resulting code can still run on v6 cores as well
(which are guaranteed to have CP15 barriers enabled)

Cc: <stable@vger.kernel.org> # v4.9+
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:28:37 +01:00
Tigran Tadevosyan c314396780 ARM: 8856/1: NOMMU: Fix CCR register faulty initialization when MPU is disabled
When CONFIG_ARM_MPU is not defined, the base address of v7M SCB register
is not initialized with correct value. This prevents enabling I/D caches
when the L1 cache poilcy is applied in kernel.

Fixes: 3c24121039 ("ARM: 8756/1: NOMMU: Postpone MPU activation till __after_proc_init")
Signed-off-by: Tigran Tadevosyan <tigran.tadevosyan@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:28:37 +01:00
Russell King 503621628b ARM: fix function graph tracer and unwinder dependencies
Naresh Kamboju recently reported that the function-graph tracer crashes
on ARM. The function-graph tracer assumes that the kernel is built with
frame pointers.

We explicitly disabled the function-graph tracer when building Thumb2,
since the Thumb2 ABI doesn't have frame pointers.

We recently changed the way the unwinder method was selected, which
seems to have made it more likely that we can end up with the function-
graph tracer enabled but without the kernel built with frame pointers.

Fix up the function graph tracer dependencies so the option is not
available when we have no possibility of having frame pointers, and
adjust the dependencies on the unwinder option to hide the non-frame
pointer unwinder options if the function-graph tracer is enabled.

Reviewed-by: Masami Hiramatsu <mhiramat@kernel.org>
Tested-by: Masami Hiramatsu <mhiramat@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:28:32 +01:00
Masahiro Yamada fe00e50b2d ARM: 8858/1: vdso: use $(LD) instead of $(CC) to link VDSO
We use $(LD) to link vmlinux, modules, decompressors, etc.

VDSO is the only exceptional case where $(CC) is used as the linker
driver, but I do not know why we need to do so. VDSO uses a special
linker script, and does not link standard libraries at all.

I changed the Makefile to use $(LD) rather than $(CC). I confirmed
the same vdso.so.raw was still produced.

Users will be able to use their favorite linker (e.g. lld instead of
of bfd) by passing LD= from the command line.

My plan is to rewrite all VDSO Makefiles to use $(LD), then delete

cc-ldoption.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:22:10 +01:00
Masahiro Yamada 32b25e9b98 ARM: 8855/1: remove unused <asm/limits.h>
No one includes this.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:22:09 +01:00
Peng Fan 14b5f54b78 ARM: 8850/1: use memblocks_present
arm_memory_present is doing same thing as memblocks_present, so
let's use common code memblocks_present instead of platform
specific arm_memory_present.

Patchwork: https://patchwork.kernel.org/patch/10805693/

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:22:07 +01:00
Stefan Agner fe4fb99020 ARM: 8854/1: drop -mauto-it
The assembler option -mauto-it is no longer a valid option. The last
remaining references have been removed from the documentation in
July 2009 [0].

The currently supported binutils version is 2.20 (released in
September 2009) or higher where gas supports -mimplicit-it=always.
Drop the fallback to -mauto-it and use -mimplicit-it=always only.

[0] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=529707530657a333a304c651c808ea630c955223

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:21:30 +01:00
Stefan Agner e8c24bbda7 ARM: 8846/1: warn if divided syntax assembler is used
Remove the -mno-warn-deprecated assembler flag to make sure the GNU
assembler warns in case non-unified syntax is used.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:21:24 +01:00
Stefan Agner 43947b8890 ARM: 8853/1: drop WASM to work around LLVM issue
Currently LLVM's integrated assembler does not recognize .w form
of the pld instructions (LLVM Bug 40972 [0]):

  ./arch/arm/include/asm/processor.h:133:5: error: invalid instruction
                          "pldw.wt%a0 n"
                           ^
  <inline asm>:2:1: note: instantiated into assembly here
  pldw.w  [r0]
  ^
  1 error generated.

The W macro for generating wide instructions when targeting Thumb-2
is not strictly required for the preload data instructions (pld, pldw)
since they are only available as wide instructions. The GNU assembler
works with or without the .w appended when compiling an Thumb-2 kernel.

Drop the macro to work around LLVM Bug 40972 issue.

[0] https://bugs.llvm.org/show_bug.cgi?id=40972

Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:20:53 +01:00
Stefan Agner fe09d9c641 ARM: 8852/1: uaccess: use unified assembler language syntax
Convert the conditional infix to a postfix to make sure this inline
assembly is unified syntax. Since gcc assumes non-unified syntax
when emitting ARM instructions, make sure to define the syntax as
unified.

This allows to use LLVM's integrated assembler.

Additionally, for GCC ".syntax unified" for inline assembly.
When compiling non-Thumb2 GCC always emits a ".syntax divided"
at the beginning of the inline assembly which makes the
assembler fail. Since GCC 5 there is the -masm-syntax-unified
GCC option which make GCC assume unified syntax asm and hence
emits ".syntax unified" even in ARM mode. However, the option
is broken since GCC version 6 (see GCC PR88648 [1]). Work
around by adding ".syntax unified" as part of the inline
assembly.

[0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:20:52 +01:00
Stefan Agner a6c9e96bf8 ARM: 8851/1: add TUSERCOND() macro for conditional postfix
Unified assembly syntax requires conditionals to be postfixes.
TUSER() currently only takes a single argument which then gets
appended t (with translation) on every instruction.

This fixes a build error when using LLVM's integrated assembler:
  In file included from kernel/futex.c:72:
  ./arch/arm/include/asm/futex.h:116:3: error: invalid instruction, did you mean: strt?
          "2:     " TUSER(streq) "        %3, [%4]n"
           ^
  <inline asm>:5:4: note: instantiated into assembly here
  2:      streqt  r2, [r4]
          ^~~~~~

Additionally, for GCC ".syntax unified" for inline assembly.
When compiling non-Thumb2 GCC always emits a ".syntax divided"
at the beginning of the inline assembly which makes the
assembler fail. Since GCC 5 there is the -masm-syntax-unified
GCC option which make GCC assume unified syntax asm and hence
emits ".syntax unified" even in ARM mode. However, the option
is broken since GCC version 6 (see GCC PR88648 [1]). Work
around by adding ".syntax unified" as part of the inline
assembly.

[0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23 17:20:51 +01:00
Linus Walleij 1fae0ad1e2 ARM: dts: Add queue manager and NPE to the IXP4xx DTSI
The AHB queue manager and Network Processing Engines are
present on all IXP4xx SoCs, so we add them to the overarching
device tree include.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:16 +02:00
Linus Walleij ecc133c6da soc: ixp4xx: qmgr: Pass resources
Instead of using hardcoded base address implicitly
obtained through <linux/io.h>, pass the physical base
for the QMGR block as a memory resource and remap
it in the driver.

Also pass the two IRQs as resources and obtain them
in the driver.

Use devm_* accessors and simplify the error path in the
process. Drop memory region request as this is done by
the devm_ioremap* functions.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:16 +02:00
Linus Walleij 0b458d7b10 soc: ixp4xx: npe: Pass addresses as resources
Instead of using hardcoded base addresses implicitly
obtained through <linux/io.h>, pass the physical base
for the three NPE blocks as memory resources and remap
these in the driver.

Drop the memory request region business, this will
anyways be done by devm_* remapping functions.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij 81bca32fcc ARM: ixp4xx: Turn the QMGR into a platform device
Instead of registering everything related to the QMGR
unconditionally in the module_init() call (which will
never work with multiplatform) create a platform device
and probe the QMGR like any other device.

Put the device second in the list of devices added for
the platform so it is there when the dependent network
and crypto drivers probe later on.

This probe() path will not be taken unconditionally on
device tree boots, so remove the DT guard.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij bc4d7eafb7 ARM: ixp4xx: Turn the NPE into a platform device
Instead of registering everything related to the NPE
unconditionally in the module_init() call (which will
never work with multiplatform) create a platform device
and probe the NPE like any other device.

Put the device first in the list of devices added for
the platform so it is there when the dependent network
and crypto drivers probe later on.

This probe() path will not be taken unconditionally on
device tree boots, so remove the DT guard.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij 4af20dc583 ARM: ixp4xx: Move IXP4xx QMGR and NPE headers
This moves the IXP4xx Queue Manager and Network Processing
Engine headers out of the <mack/*> include path as that is
incompatible with multiplatform.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij fcf2d8978c ARM: ixp4xx: Move NPE and QMGR to drivers/soc
The Network Processing Engine and Queue Manager are
versatile firmware components used by several IXP4xx
drivers.

Drivers are relying on getting access to these components
using <mach/*> headers which does not work with
multiplatform. We need to find a better place for the
drivers to live.

Let's first move them to drivers/soc and the start to
refactor a bit by passing resources and moving headers.

This patch introduce static IRQ assignments but that
will be fixed by later patches in this series.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij b9a35d705a ARM: dts: Add some initial IXP4xx device trees
This adds a device tree for the IXP4xx-based Linksys
NSLU2 and Gateworks GW2358 which encompass the Gateworks
Cambria family.

These will be the first IXP4xx device tree platforms.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij 9540724ca2 ARM: ixp4xx: Add device tree boot support
This adds a minimal support for booting IXP4xx systems
from device tree.

We have to add hacks to the QMGR, NPE and notably also
ethernet and watchdog drivers so that they don't crash
the platform: these drivers are unconditionally starting
to grab regions of statically remapped IO space with no
concern of the device model or other platforms.

We will go in and properly fix these drivers as we go
along but for now this hack gets us to a place where we
can start working on proper device tree support for these
platforms.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:15 +02:00
Linus Walleij 65af666713 ARM: ixp4xx: Switch to use new timer driver
This augments the IXP4xx to select and use the new
timer driver in drivers/clocksource and removes the old
code in the machine.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:14 +02:00
Linus Walleij 55ec465e73 ARM: ixp4xx: Switch to use new IRQ+GPIO drivers
This deletes the old irq+gpiochip combo from the IXP4xx
machine and switches it over to use the new drivers merged
in respective subsystem.

Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23 16:02:13 +02:00
Andrey Smirnov 4171797ff7 ARM: dts: imx7s: Specify #io-channel-cells in ADC nodes
Specify #io-channel-cells in ADC nodes. Needed to be able to reference
them by phandle.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-23 09:48:26 +08:00
Jens Axboe 5c61ee2cd5 Linux 5.1-rc6
-----BEGIN PGP SIGNATURE-----
 
 iQFSBAABCAA8FiEEq68RxlopcLEwq+PEeb4+QwBBGIYFAly8rGYeHHRvcnZhbGRz
 QGxpbnV4LWZvdW5kYXRpb24ub3JnAAoJEHm+PkMAQRiGmZMH/1IRB0E1Qmzz8yzw
 wj79UuRGYPqxDDSWW+wNc8sU4Ic7iYirn9APHAztCdQqsjmzU/OVLfSa3JhdBe5w
 THo7pbGKBqEDcWnKfNk/21jXFNLZ1vr9BoQv2DGU2MMhHAyo/NZbalo2YVtpQPmM
 OCRth5n+LzvH7rGrX7RYgWu24G9l3NMfgtaDAXBNXesCGFAjVRrdkU5CBAaabvtU
 4GWh/nnutndOOLdByL3x+VZ3H3fIBnbNjcIGCglvvqzk7h3hrfGEl4UCULldTxcM
 IFsfMUhSw1ENy7F6DHGbKIG90cdCJcrQ8J/ziEzjj/KLGALluutfFhVvr6YCM2J6
 2RgU8CY=
 =CfY1
 -----END PGP SIGNATURE-----

Merge tag 'v5.1-rc6' into for-5.2/block

Pull in v5.1-rc6 to resolve two conflicts. One is in BFQ, in just a
comment, and is trivial. The other one is a conflict due to a later fix
in the bio multi-page work, and needs a bit more care.

* tag 'v5.1-rc6': (770 commits)
  Linux 5.1-rc6
  block: make sure that bvec length can't be overflow
  block: kill all_q_node in request_queue
  x86/cpu/intel: Lower the "ENERGY_PERF_BIAS: Set to normal" message's log priority
  coredump: fix race condition between mmget_not_zero()/get_task_mm() and core dumping
  mm/kmemleak.c: fix unused-function warning
  init: initialize jump labels before command line option parsing
  kernel/watchdog_hld.c: hard lockup message should end with a newline
  kcov: improve CONFIG_ARCH_HAS_KCOV help text
  mm: fix inactive list balancing between NUMA nodes and cgroups
  mm/hotplug: treat CMA pages as unmovable
  proc: fixup proc-pid-vm test
  proc: fix map_files test on F29
  mm/vmstat.c: fix /proc/vmstat format for CONFIG_DEBUG_TLBFLUSH=y CONFIG_SMP=n
  mm/memory_hotplug: do not unlock after failing to take the device_hotplug_lock
  mm: swapoff: shmem_unuse() stop eviction without igrab()
  mm: swapoff: take notice of completion sooner
  mm: swapoff: remove too limiting SWAP_UNUSE_MAX_TRIES
  mm: swapoff: shmem_find_swap_entries() filter out other types
  slab: store tagged freelist for off-slab slabmgmt
  ...

Signed-off-by: Jens Axboe <axboe@kernel.dk>
2019-04-22 09:47:36 -06:00
Andrey Smirnov 2ea5c9b28f ARM: dts: vf610-zii-dev-rev-b: Specify CS as GPIO_ACTIVE_LOW in spi0
Specify CS as GPIO_ACTIVE_LOW in spi0 to fix the following warning:

m25p128@0 enforce active low on chipselect handle

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22 09:16:15 +08:00
Andrey Smirnov 1437626ec4 ARM: dts: vf610-zii-dev: Mark i2c0 SCL as GPIO_OPEN_DRAIN
Mark i2c0 SCL as GPIO_OPEN_DRAIN to fix the following warning:

gpio-36 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22 09:15:59 +08:00
Andrey Smirnov 69ab5392f5 ARM: dts: Add support for ZII i.MX7 RPU2 board
Add support for ZII's i.MX7 based Remote Peripheral Unit 2 (RPU2)
board.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22 09:03:35 +08:00
Bruno Thomsen 5ea0c200bd ARM: dts: bugfix tqma7 soft reset issue
Running reboot command on the TQMa7 board would just hang infinite
at the end of the system shutdown process.

Handling of i.MX7 errata e10574:
Watchdog: A watchdog timeout or software trigger will not reset the SOC.

Moved pinctrl from common mba7 to common tqma7 dtsi as it improves
readability of errata handling. Most integrators of this SoM will
likely use the development board as inspiration for handling this
SoC issue.

Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22 08:51:49 +08:00
Chris Packham 7971cc408d ARM: mvebu: kirkwood: remove error message when retrieving mac address
Kirkwood has always had the ability to retrieve the local-mac-address
from the hardware (usually this was configured by the bootloader). This
is particularly useful when dealing with a legacy non-DT aware
bootloader.

The "error" message just indicated that the board used an old bootloader
and in many cases users can't do anything about this. The message
probably should have been pr_info() to inform the user that the kernel
has been helpful but rather than than let's remove it entirely to make
the kernel less noisy.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21 19:01:41 +02:00
Chris Packham 71f2b9957d ARM: dts: armada-38x: add interrupts for watchdog
The first interrupt is for the regular watchdog timeout. Normally the
RSTOUT line will trigger a reset before this interrupt fires but on
systems with a non-standard reset it may still trigger.

The second interrupt is for a timer1 which is used as a pre-timeout for
the watchdog.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21 18:26:20 +02:00
Marek Vasut 716be61d18 ARM: dts: imx53: Add Menlosystems M53 board
Add device tree for the Menlosystems board based on i.MX53 M53 SoM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21 16:02:30 +08:00
Marek Vasut 6143613a84 ARM: dts: imx53: Rename M53 SoM touchscreen node
Rename the touchscreen node to match contemporary design.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21 16:02:13 +08:00
Vladimir Oltean c7861adbe3 ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY disconnect
Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus.
But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC
are pointing towards the same internal PCS. Therefore nobody is
controlling the internal PCS of eTSEC0.

Upon initial ndo_open, the SGMII link is ok by virtue of U-boot
initialization. But upon an ifdown/ifup sequence, the code path from
ndo_open -> init_phy -> gfar_configure_serdes does not get executed for
the PCS of eTSEC0 (and is executed twice for MAC eTSEC1). So the SGMII
link remains down for eTSEC0. On the LS1021A-TWR board, to signal this
failure condition, the PHY driver keeps printing
'803x_aneg_done: SGMII link is not ok'.

Also, it changes compatible of mdio0 to "fsl,etsec2-mdio" to match
mdio1 device.

Fixes: 055223d4d2 ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR")
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21 15:51:28 +08:00
Vladimir Zapolskiy d5a71e4646 ARM: dts: lpc32xx: use SPDX license identifier
Replace GPLv2+ header with the SPDX identifier.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:57:12 +03:00
Vladimir Zapolskiy cea8623867 ARM: dts: lpc32xx: add address and size cell values to SPI controller nodes
All 4 SPI controllers on NXP LPC32xx SoC support SPI slaves discerning them
by one cell address value, set it as default to avoid duplication in board
device tree files.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:57:04 +03:00
Vladimir Zapolskiy 4c546175db ARM: dts: lpc32xx: disable MAC controller by default
NXP LPC3220 and LPC3230 SoCs do NOT contain a MAC controller, so,
since for now there is just one dtsi file for all variants of
NXP LPC32xx SoCs, it is reasonable to disable the controller
by default and enable it in device tree files of particular boards.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:56:57 +03:00
Vladimir Zapolskiy 903fa2ab79 ARM: dts: lpc32xx: disable I2S controllers by default
The I2S controllers found on NXP LPC32xx SoCs are not yet in
use by any boards supported in upstream, disable the controllers
by default.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:56:48 +03:00
Vladimir Zapolskiy 37917ce5b4 ARM: dts: lpc32xx: change hexadecimal values to lower case
This is a non-functional change, all inconsistent hexadecimal values
found in the file are now fixed.

Taking a chance to interfere into some non-functional change I add
my copyright notice for work done during the last few years.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 23:56:40 +03:00
Vladimir Zapolskiy e861cfbed0 ARM: lpc32xx: use SPDX license identifier
Replace GPLv2+ header with the SPDX identifier.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 22:59:30 +03:00
Vladimir Zapolskiy bbf553c6bb ARM: lpc32xx: remove platform data of SSP0 and SSP1 controllers
Both controllers are described in lpc32xx.dtsi and there is no any
specific platform data added in the platform file.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 22:59:23 +03:00
Vladimir Zapolskiy a1e65c28f6 ARM: lpc32xx: remove redundant included headers
While the majority of platform data was moved to device tree description
the list of included header files remained untouched, the change cleans
it up to an irreducible and observable subset.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 22:59:16 +03:00
Alexandre Belloni a93fb4f407 ARM: lpc32xx: stop overwriting TEST_CLK_SEL
While the UDA1380 is described in some lpc3250 device trees, there is
currently no real user of that codec. Anyway, if the codec needs a clock,
it should take it explicitly.

lpc3250_machine_init is called for all the lpc32xx machines and some are
using test1_clk (for example to strobe an HW watchdog). Overwriting
TEST_CLK_SEL prevents booting those platforms.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19 22:12:28 +03:00
Linus Walleij dc8ef8cd3a ARM: ixp4xx: Convert to SPARSE_IRQ
This localizes the <mach/irqs.h> header to the mach-ixp4xx
directory, removes NR_IRQS and switches IXP4xx over to using
SPARSE_IRQ.

This is a prerequisite for DT support.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-19 20:37:44 +02:00
Linus Walleij 075df31aed ARM: ixp4xx: Pass IRQ resource to beeper
All IXP4xx devices except the beeper passes the IRQ as a
resource, augment the NSLU2 beeper to do the same.

This is a prerequisite for SPARSE_IRQ.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-19 20:37:40 +02:00
Linus Walleij 98ac0cc270 ARM: ixp4xx: Convert to MULTI_IRQ_HANDLER
This rewrites the IXP4xx to use MULTI_IRQ_HANDLER and
create an irqdomain for the irqchip in the platform. We
convert the timer to request the interrupt like any other
driver in the process.

We bump all IRQs to 16+offset to avoid using IRQ 0 and
set NR_IRQS to 512 (the default for most systems).
This conveniently fits with the first 16 IRQs being
pre-allocated when using SPARSE_IRQ.

This is a prerequisite for SPARSE_IRQ and DT boot.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-19 20:37:34 +02:00
David Howells 5dd50aaeb1
Make anon_inodes unconditional
Make the anon_inodes facility unconditional so that it can be used by core
VFS code and pidfd code.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
[christian@brauner.io: adapt commit message to mention pidfds]
Signed-off-by: Christian Brauner <christian@brauner.io>
2019-04-19 14:03:11 +02:00
Mathieu Desnoyers bff9504bfc rseq: Clean up comments by reflecting removal of event counter
The "event counter" was removed from rseq before it was merged upstream.
However, a few comments in the source code still refer to it. Adapt the
comments to match reality.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Ben Maurer <bmaurer@fb.com>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Chris Lameter <cl@linux.com>
Cc: Dave Watson <davejwatson@fb.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Joel Fernandes <joelaf@google.com>
Cc: Josh Triplett <josh@joshtriplett.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Michael Kerrisk <mtk.manpages@gmail.com>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Paul Turner <pjt@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-api@vger.kernel.org
Link: http://lkml.kernel.org/r/20190305194755.2602-2-mathieu.desnoyers@efficios.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-04-19 12:39:31 +02:00
Dave Martin 92e68b2b1b KVM: arm/arm64: Clean up vcpu finalization function parameter naming
Currently, the internal vcpu finalization functions use a different
name ("what") for the feature parameter than the name ("feature")
used in the documentation.

To avoid future confusion, this patch converts everything to use
the name "feature" consistently.

No functional change.

Suggested-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-18 17:14:02 +01:00
Dave Martin 0323e027df KVM: arm: Make vcpu finalization stubs into inline functions
The vcpu finalization stubs kvm_arm_vcpu_finalize() and
kvm_arm_vcpu_is_finalized() are currently #defines for ARM, which
limits the type-checking that the compiler can do at runtime.

The only reason for them to be #defines was to avoid reliance on
the definition of struct kvm_vcpu, which is not available here due
to circular #include problems.  However, because these are stubs
containing no code, they don't need the definition of struct
kvm_vcpu after all; only a declaration is needed (which is
available already).

So in the interests of cleanliness, this patch converts them to
inline functions.

No functional change.

Suggested-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-18 17:14:01 +01:00
Dave Martin a3be836df7 KVM: arm/arm64: Demote kvm_arm_init_arch_resources() to just set up SVE
The introduction of kvm_arm_init_arch_resources() looks like
premature factoring, since nothing else uses this hook yet and it
is not clear what will use it in the future.

For now, let's not pretend that this is a general thing:

This patch simply renames the function to kvm_arm_init_sve(),
retaining the arm stub version under the new name.

Suggested-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-18 17:14:01 +01:00
Chen-Yu Tsai 6e0c67e34f
ARM: dts: sun8i: a83t: Enable USB OTG controller on some boards
The Bananapi M3 and Cubietruck Plus both have USB OTG ports wired to the
SoC and PMIC in the same way, with the N_VBUSEN pin on the PMIC
controlling VBUS output, the PMIC's VBUS input for sensing VBUS, and
PH11 on the SoC for sensing the ID pin.

Enable OTG on both boards.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-18 17:49:43 +02:00
Quentin Schulz 6cb6cfd61e
ARM: dtsi: axp81x: add USB power supply node
The AXP813/818 has a VBUS power input. Add a device node for it, now
that we support it.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
[wens@csie.org: Add commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-18 17:49:43 +02:00
Eric Biggers 767f015ea0 crypto: arm/aes-neonbs - don't access already-freed walk.iv
If the user-provided IV needs to be aligned to the algorithm's
alignmask, then skcipher_walk_virt() copies the IV into a new aligned
buffer walk.iv.  But skcipher_walk_virt() can fail afterwards, and then
if the caller unconditionally accesses walk.iv, it's a use-after-free.

arm32 xts-aes-neonbs doesn't set an alignmask, so currently it isn't
affected by this despite unconditionally accessing walk.iv.  However
this is more subtle than desired, and it was actually broken prior to
the alignmask being removed by commit cc477bf645 ("crypto: arm/aes -
replace bit-sliced OpenSSL NEON code").  Thus, update xts-aes-neonbs to
start checking the return value of skcipher_walk_virt().

Fixes: e4e7f10bfc ("ARM: add support for bit sliced AES using NEON instructions")
Cc: <stable@vger.kernel.org> # v3.13+
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-04-18 22:14:58 +08:00
Dmitry Osipenko 1078946b4b ARM: tegra: Add ACTMON support on Tegra30
Add support for ACTMON on Tegra30. This is used to monitor activity from
different components. Based on the collected statistics, the rate at
which the external memory needs to be clocked can be derived.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-18 11:37:46 +02:00
Dmitry Osipenko a359de1b40 Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+"
Turned out that the actual bug was in the Memory Controller driver
that programmed shadowed registers without latching the new values
and then there was a bug on EMEM arbitration configuration calculation
that results in a wrong value being latched on resume from suspend.
The Memory Controller has been fixed properly now, hence the workaround
patch could be reverted safely.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-18 11:36:24 +02:00
Dmitry Osipenko 36841ba279 ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30
Tegra20/30 drivers do not handle the tick_broadcast_enter() error which
potentially could happen when CPU timer isn't permitted to be stopped.
Let's just move out the broadcasting to the CPUIDLE core by setting the
respective flag in the Tegra20/30 drivers. This patch doesn't fix any
problem because currently tick_broadcast_enter() could fail only on
ARM64, so consider this change as a minor cleanup.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-18 11:32:57 +02:00
Tudor Ambarus c60fed1dfd ARM: at91: sama5: make ov2640 as a module
OV2640 is a detachable camera that we use to test the
Image Sensor Interface. Make it as a module, it will reduce
the kernel image size.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
2019-04-18 10:55:40 +02:00
Miquel Raynal 72c5af0027 mtd: rawnand: Clarify Kconfig entry MTD_NAND
MTD_NAND is large and encloses much more than what the symbol is
actually used for: raw NAND. Clarify the symbol by naming it
MTD_RAW_NAND instead.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18 08:54:00 +02:00
Miquel Raynal 9bb94643b9 mtd: nand: Clarify Kconfig entry for software Hamming ECC entries
The software Hamming ECC correction implementation is referred as
MTD_NAND_ECC which is too generic. Rename it
MTD_NAND_ECC_SW_HAMMING. Also rename MTD_NAND_ECC_SMC which is an
SMC quirk in the Hamming implementation as
MTD_NAND_ECC_SW_HAMMING_SMC.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18 08:54:00 +02:00
Miquel Raynal 714c068228 mtd: nand: Clarify Kconfig entry for software BCH ECC algorithm
There is no point in having two distinct entries, merge them and
rename the symbol for more clarity: MTD_NAND_ECC_SW_BCH

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18 08:54:00 +02:00
Linus Walleij f4bdfcc29a ARM: dts: Ux500: Add MCDE and Samsung display
This adds and updates the device tree nodes for the MCDE
display controller and connects the Samsung display to
the TVK1281618 user interface board (UIB) so we get
nicely working graphics on this reference design.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-17 23:18:47 +02:00
Linus Walleij 61313fb2cc ARM: dts: ux500: Add Mali-400
This adds the Mali-400 block, also known as SGA500 or the
Smart Graphics Adapter, to the DBx500 DTS file. All
resources and bindings are already in place so this just
works.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-17 23:18:30 +02:00
Magnus Damm 0750e8344e ARM: dts: ape6evm: Reorder bootargs
Reorder bootargs parameters to make the APE6EVM board bootargs match other
boards from Renesas. No need to be special.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-17 17:47:37 +02:00
Magnus Damm ee8b7420fe ARM: dts: marzen: Add rw to bootargs and use ip=dhcp
Add rw as bootargs parameter and change from ip=on to ip=dhcp to make the
Marzen board bootargs match other boards from Renesas. No need to be special.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-17 17:47:22 +02:00
Magnus Damm 44861e5486 ARM: dts: bockw: Reorder bootargs
Reorder bootargs parameters to make the BockW board bootargs match other
boards from Renesas. No need to be special.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-17 17:47:04 +02:00
Magnus Damm 94b42a96da ARM: dts: kzm9d: Add rw parameter to bootargs
Add rw as bootargs parameter to make the KZM9D board bootargs match other
boards from Renesas. No need to be special.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-17 17:46:34 +02:00
Maxime Ripard 7aaee3d116
ARM: dts: sun8i: mapleboard: Remove cd-inverted
The cd-inverted property can also be expressed using the GPIO flags. Use
the active low GPIO flag to have the same semantic without the confusion.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17 16:57:48 +02:00
Maxime Ripard 66dc4e4bfc
ARM: dts: sun5i: Reorder pinctrl nodes
We try to keep the PIO nodes ordered alphabetically, but this doesn't
always work out. Let's fix it.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17 16:56:42 +02:00
Maxime Ripard 4b03e16d30
ARM: dts: sun6i: i7: Remove useless property
The I7 DTS uses an spdif-out property with an "okay" value. However, that
property isn't documented anywhere, and isn't used anywhere either.

Remove it.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17 16:56:40 +02:00
Maxime Ripard 15a48503cc
ARM: dts: sun4i: lime: Fix the USB PHY ID detect GPIO properties
While the USB PHY Device Tree mandates that the name of the ID detect pin
should be usb0_id_det-gpios, a significant number of device tree use
usb0_id_det-gpio instead.

This was functional because the GPIO framework falls back to the gpio
suffix that is legacy, but we should fix this. Commit 2c515b0d05
("ARM: sunxi: Fix the USB PHY ID detect GPIO properties") was supposed to
fix this, but one fell through the cracks.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17 16:56:39 +02:00
Maxime Ripard 147f3d5cc6
ARM: dts: sun4i: protab2: Remove stale pinctrl-names entry
Some nodes still have pinctrl-names entry, yet they don't have any pinctrl
group anymore. Drop them.

Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17 16:56:36 +02:00
Thierry Reding 4cb5d9eca1 firmware: Move Trusted Foundations support
Move the Trusted Foundations support out of arch/arm/firmware and into
drivers/firmware where most other firmware support implementations are
located.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:43:03 +02:00
Thierry Reding a6f3d883a6 ARM: Enable Trusted Foundations for multiplatform ARM v7
Some 32-bit Tegra devices supported by the multiplatform ARM v7 default
configuration ship with the Trusted Foundations firmware. Enable support
for it by default.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:36:34 +02:00
Thierry Reding 3a4fea460e ARM: tegra: Enable Trusted Foundations by default
Support for the Trusted Foundations firmware was recently moved outside
of arch/arm and now needs to be selected explicitly. Since some 32-bit
Tegra devices use this firmware, enable support for it in the default
configuration.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:35:44 +02:00
Thierry Reding 153f89ad37 ARM: tegra: Update default configuration for v5.1-rc1
Most of the changes here are just symbols that are now enabled by
default, have been removed, or which have been moved around and now
appear in a different spot.

The only notable change here is that BACKLIGHT_CLASS_DEVICE is now
built-in. This is to allow BACKLIGHT_PWM to be built-in as well.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:35:43 +02:00
Thierry Reding de36d54512 ARM: tegra: venice2: Move PLL power supplies to XUSB pad controller
The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:30:27 +02:00
Thierry Reding 965ae23289 ARM: tegra: nyan: Move PLL power supplies to XUSB pad controller
The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the XUSB controller to the XUSB pad controller to make
sure they are available when needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:30:26 +02:00
Thierry Reding cbfe6d036f ARM: tegra: jetson-tk1: Move PLL power supplies to XUSB pad controller
The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:30:26 +02:00
Thierry Reding 0c2f4ebbd7 ARM: tegra: apalis: Move PLL power supplies to XUSB pad controller
The XUSB pad controller is responsible for supplying power to the PLLs
used to drive the various USB, PCI and SATA pads. Move the PLL power
supplies from the PCIe and XUSB controllers to the XUSB pad controller
to make sure they are available when needed.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:30:26 +02:00
Thierry Reding 4a28f63449 ARM: tegra: Remove gratuitous parentheses in SPDX license identifier
Parentheses in the SPDX license identifier are only used to group sub-
expressions. If there's no need for such grouping, the parentheses can
be omitted.

Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:30:21 +02:00
Igor Opaniuk 8cb35d345c ARM: tegra: Convert to SPDX license tags for Tegra124 Apalis
Replace boiler plate licenses texts with the SPDX license identifiers in
Colibri/Apalis DTS files.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
[treding@nvidia.com: drop unneeded parentheses, keep license at X11]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17 16:29:47 +02:00
Maxime Ripard 0a3df8bb6d
ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCI
Neither the OHCI or EHCI bindings are using the phy-names property, so we
can just drop it.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17 09:58:00 +02:00
Maxime Ripard 3d109bdca9
ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCI
Neither the OHCI or EHCI bindings are using the phy-names property, so we
can just drop it.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17 09:57:30 +02:00
Martin Blumenstingl 09ee951617 ARM: dts: meson8b: odroid-c1: prepare support for the RTC
The Odroid-C1 has the 32.768 kHz oscillator (X3 in the schematics) which
is required for the RTC. A battery can be connected separately (to the
BT1 header) - then the "rtc" node can be enabled manually. By default
the RTC is disabled because the boards typically come without the RTC
battery.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16 11:58:00 -07:00
Martin Blumenstingl 6ffdc4738c ARM: dts: meson8b: ec100: enable the RTC
The RTC is always enabled on this board since the battery is already
connected in the factory.
According to the schematics the VCC_RTC regulator (which is either
powered by the internal 3.3V or a battery) is connected to the 0.9V
RTC_VDD input of the SoCs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16 11:57:50 -07:00
Martin Blumenstingl f6eb973db2 ARM: dts: meson: add support for the RTC
The 32-bit Meson SoCs have an RTC block in the AO (always on) area. The
RTC requires an external 32.768 kHz oscillator to work properly. Whether
or not this crystal exists depends on the board, so it has to be added
for each board.dts (instead of adding it somewhere in a generic .dtsi).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16 11:57:48 -07:00
Aaro Koskinen 11e600a8c7 ARM: OMAP1: ams-delta: fix early boot crash when LED support is disabled
When we boot with the LED support (CONFIG_NEW_LEDS) disabled,
gpio_led_register_device() will return a NULL pointer and we try
to dereference it. Fix by checking also for a NULL pointer.

Fixes: 19a2668a8a ("ARM: OMAP1: ams-delta: Provide GPIO lookup table for LED device")
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-16 07:43:19 -07:00
Tony Lindgren 35f8e2e29e ARM: multi_v7_defconfig: Update for moved options
These options have just moved around, let's update with make
savedefconfig to make patching the file easier.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Olof Johansson <olof@lixom.net>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-16 07:05:07 -07:00
Tony Lindgren 0d2cd68662 ARM: multi_v7_defconfig: Update for dropped options
These are mostly automatically selected with make multi_v7_defconfig,
except for SH_DMAE which is selected only by sound/soc/sh/Kconfig.

Then CONFIG_SND_SIMPLE_SCU_CARD no longer exists at all.

And CONFIG_SOC_CAMERA and CONFIG_SOC_CAMERA_PLATFORM are tagged
to depend on BROKEN, so we can drop them.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Olof Johansson <olof@lixom.net>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-16 07:05:07 -07:00
Christina Quast e5b258e53e ARM: dts: am335x: wega: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:28 -07:00
Christina Quast b1e0c487f3 ARM: dts: am335x: sl50: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:27 -07:00
Christina Quast aa7ed18373 ARM: dts: am335x: shc: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:27 -07:00
Christina Quast 631493a16a ARM: dts: am335x: sbc-t335: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:26 -07:00
Christina Quast c5ebf24a41 ARM: dts: am335x: sancloud-bbe: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:26 -07:00
Christina Quast a3328bf02d ARM: dts: am335x: phycore-som: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:25 -07:00
Christina Quast 891ffb8fcd ARM: dts: am335x: pepper: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:25 -07:00
Christina Quast 898c4a59bc ARM: dts: am335x: pdu001: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:24 -07:00
Christina Quast 781288d2bd ARM: dts: am335x: pcm-953: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:23 -07:00
Christina Quast 558fee9ab5 ARM: dts: am335x: osd335x-common: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:23 -07:00
Christina Quast 443fca762b ARM: dts: am335x: osd3358-sm-red: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:22 -07:00
Christina Quast affcce6f7c ARM: dts: am335x: nano: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:22 -07:00
Christina Quast c68a4ffd3d ARM: dts: am335x: moxa-uc-8100-me-t: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:21 -07:00
Christina Quast 4a424b0b16 ARM: dts: am335x: moxa-uc-2101: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:20 -07:00
Christina Quast 876144dd53 ARM: dts: am335x: moxa-uc-2100-common: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:20 -07:00
Christina Quast c422b10e88 ARM: dts: am335x: lxm: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:19 -07:00
Christina Quast 387fbf73eb ARM: dts: am335x: igep0033: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15 08:26:19 -07:00
Arnd Bergmann 39036cd272 arch: add pidfd and io_uring syscalls everywhere
Add the io_uring and pidfd_send_signal system calls to all architectures.

These system calls are designed to handle both native and compat tasks,
so all entries are the same across architectures, only arm-compat and
the generic tale still use an old format.

Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> (s390)
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-04-15 16:31:17 +02:00
Andreas Kemnade 8558c6e21c
ARM: dts: sun8i: h3: bluetooth for Banana Pi M2 Zero board
The Banana Pi M2 Zero board has an AP6212 BT+Wifi combo chip
with Broadcom internals attached to UART1 and some gpios.
This addition is in line with similar boards.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-15 11:00:19 +02:00
Pablo Greco 635e1e78a6
ARM: dts: sun8i: v40: bananapi-m2-berry: Sort device node dereferences.
The device node dereferences are out of order, sort them.

Signed-off-by: Pablo Greco <pgreco@centosproject.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-15 09:51:30 +02:00
YueHaibing 9ee8578d95 ARM: pxa: ssp: Fix "WARNING: invalid free of devm_ allocated data"
Since commit 1c459de1e6 ("ARM: pxa: ssp: use devm_ functions")
kfree, iounmap, clk_put etc are not needed anymore in remove path.

Fixes: 1c459de1e6 ("ARM: pxa: ssp: use devm_ functions")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
[ commit message spelling fix ]
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2019-04-14 21:54:50 +02:00
Thomas Gleixner 2a2bcfa0c9 arm/stacktrace: Remove the pointless ULONG_MAX marker
Terminating the last trace entry with ULONG_MAX is a completely pointless
exercise and none of the consumers can rely on it because it's
inconsistently implemented across architectures. In fact quite some of the
callers remove the entry and adjust stack_trace.nr_entries afterwards.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Alexander Potapenko <glider@google.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lkml.kernel.org/r/20190410103643.843075256@linutronix.de
2019-04-14 19:58:27 +02:00
Charles Keepax 7676e667c8 ARM: s3c64xx: Tidy up handling of regulator GPIO lookups
Rather than unconditionally registering the GPIO lookup table only do so
for devices that require it.

Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
[Fixed up to also handle wm5102 and wm5102 reva]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-04-14 12:53:03 +02:00
Douglas Anderson 356150e86d ARM: dts: rockchip: vdd_gpu off in suspend for rk3288-veyron
At some point long long ago the downstream GPU driver would crash if
we turned the GPU off during suspend.  For some context you can see:

https://chromium-review.googlesource.com/#/c/215780/5..6/arch/arm/boot/dts/rk3288-pinky-rev2.dts

At some point in time not too long after that got fixed.

It's unclear why the GPU is left enabled during suspend on the
mainline kernel.  Everything seems fine if I turn this off, so let's
do it.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-12 22:28:38 +02:00
Douglas Anderson ed27ae71bf ARM: dts: rockchip: vcc33_ccd off in suspend for rk3288-veyron-chromebook
As per my comments when the device tree for rk3288-veyron-chromebook
first landed:

> Technically I think vcc33_ccd can be off since we have
> 'needs-reset-on-resume' down in the EHCI port (this regulator is for
> the USB webcam that's connected to the EHCI port).
>
>  ...but leaving it on for now seems fine until we get suspend/resume
> more solid.

It's probably about time to do it right.

[1] https://lore.kernel.org/linux-arm-kernel/CAD=FV=U37Yx8Mqk75_x05zxonvdc3qRMhqp8TyTDPWGHqSuRqg@mail.gmail.com/

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-12 22:28:21 +02:00
Roger Quadros bcbb63b802 ARM: dts: dra7: Separate AM57 dtsi files
AM5 and DRA7 SoC families have different set of modules
in them so the SoC sepecific dtsi files need to be separated.

e.g. Some of the major differences between AM576 and DRA76

		DRA76x	AM576x

USB3		x
USB4		x
ATL		x
VCP		x
MLB		x
ISS		x
PRU-ICSS1		x
PRU-ICSS2		x

This patch only deals with disabling USB3, USB4 and ATL for
AM57 variants.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 09:57:07 -07:00
Christina Quast 33ef1394a9 ARM: dts: am335x: icev2: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:14 -07:00
Christina Quast 1f757e0616 ARM: dts: am335x: evmsk: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:13 -07:00
Christina Quast ef2791fd13 ARM: dts: am335x: evm: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:12 -07:00
Christina Quast 6c4f9ebf86 ARM: dts: am335x: cm-t335: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:12 -07:00
Christina Quast 125a6f3c58 ARM: dts: am335x: chilisom: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:11 -07:00
Christina Quast 4e5835effc ARM: dts: am335x: chiliboard: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:11 -07:00
Christina Quast e52a7204cd ARM: dts: am335x: bonegreen-common: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:10 -07:00
Christina Quast 9faf08c2e6 ARM: dts: am335x: boneblue: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:10 -07:00
Christina Quast ada077fa90 ARM: dts: am335x: bonegreen-wireless: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:09 -07:00
Christina Quast 0b119fafc8 ARM: dts: am335x: base0033: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:09 -07:00
Christina Quast 11ce1e0897 ARM: dts: am335x: baltos: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:08 -07:00
Christina Quast 8ce8c4b31a ARM: dts: am335x: baltos-leds: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:07 -07:00
Christina Quast f6385bd149 ARM: dts: am335x: baltos-ir5221: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:07 -07:00
Christina Quast a48d48e653 ARM: dts: am335x: baltos-ir3220: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:06 -07:00
Christina Quast 7229d544c8 ARM: dts: am335x: baltos-ir2110: Replaced register offsets with defines
The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-12 08:55:06 -07:00
Bartosz Golaszewski 274e4c3361 ARM: davinci: da830-evm: add a fixed regulator for ohci-da8xx
Instead of directly using the vbus GPIO we should model it as a fixed
regulator. Add all necessary fix-ups for the regulator to be registered
and configure the vbus GPIO as its enable pin.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-04-12 19:46:47 +05:30
Bartosz Golaszewski 1d272894ec ARM: davinci: omapl138-hawk: add a fixed regulator for ohci-da8xx
Instead of directly using the vbus GPIO we should model it as a fixed
regulator. Add all necessary fix-ups for the regulator to be registered
and configure the vbus GPIO as its enable pin.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-04-12 19:46:46 +05:30
Bartosz Golaszewski 3ea9ae57b4 ARM: davinci: add missing sentinels to GPIO lookup tables
Some GPIO lookup tables defined in davinci board files are missing
array sentinels. If an entry for given device cannot be found, this
will cause a kernel panic.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-04-12 19:43:54 +05:30
Biju Das 0725a5478e ARM: dts: iwg23s-sbc: Enable HS-USB
Enable HS-USB device for the iWave SBC based on RZ/G1C.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 14:26:09 +02:00
Biju Das 307ca5cf47 ARM: dts: r8a77470: Add HSUSB device nodes
Define the r8a77470 generic part of the HSUSB0/1 device nodes.

Currently the renesas_usbhs driver doesn't handle multiple phys and we
don't have a proper hardware to validate such driver changes.

So for hsusb1 it is assumed that usbphy0 will be enabled by either
channel0 host or device.

In future, if any boards support hsusb1, we will need to add multiple phy
support in the renesas_usbhs driver and override the board dts to enable
the same.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 14:24:35 +02:00
Biju Das 034484c4a3 ARM: dts: iwg23s-sbc: Enable USB USB2.0 Host
Enable USB2.0 host on the iwg23s sbc.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 14:23:15 +02:00
Biju Das ce5940798c ARM: dts: r8a77470: Add USB2.0 Host (EHCI/OHCI) device
Define the r8a77470 generic part of the USB2.0 Host Controller device
nodes (ehci[01]/ohci[01]).

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 14:21:55 +02:00
Biju Das e18cfb6e04 ARM: dts: iwg23s-sbc: Enable USB Phy[01]
Enable USB phy[01] on iWave iwg23s sbc based on RZ/G1C SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 14:19:35 +02:00
Biju Das 1a675db440 ARM: dts: r8a77470: Add USB PHY DT support
Define the r8a77470 generic part of the USB PHY device node.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 14:17:42 +02:00
Biju Das b266731b76 ARM: shmobile: Enable USB [EO]HCI HCD PLATFORM support in shmobile_defconfig
The USB [EO]HCI controller on RZ/G1C SoC doesn't have PCI bridge like
other R-Car Gen2 devices. So enable generic USB [EO]HCI HCD PLATFORM
support in shmobile_defconfig.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 14:16:10 +02:00
Biju Das 0cd4f4f102 ARM: shmobile: Enable PHY_RCAR_GEN3_USB2 in shmobile_defconfig
Enable PHY_RCAR_GEN3_USB2 in shmobile_defconfig so that boards
based on RZ/G1C SoC design can use the corresponding driver.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 14:14:36 +02:00
Cao Van Dong 1631b58c7e ARM: dts: r8a77470: Add VIN support
Add vin{0|1} nodes to dtsi for VIN support on the RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 14:06:25 +02:00
Cao Van Dong 3d59e55ef8 ARM: dts: r8a77470: Add PWM support
Add pwm{0|1|2|3|4|5|6} nodes to dtsi for PWM support on the
RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 13:59:09 +02:00
Cao Van Dong f408170d18 ARM: dts: r8a77470: Add HSCIF support
Add hscif{0|1|2} nodes to dtsi for HSCIF support on the
RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-12 13:53:07 +02:00
Douglas Anderson 8a5deb4e31 ARM: dts: rockchip: Add DDR retention/poweroff to rk3288-veyron hogs
Even though upstream Linux doesn't yet go into deep enough suspend to
get DDR into self refresh, there is no harm in setting these pins up.
They'll only actually do something if we go into a deeper suspend but
leaving them configed always is fine.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-12 13:14:29 +02:00
Douglas Anderson 2dd00d31d4 ARM: rockchip: Mark pm-init functions __init
The functions rk3288_config_bootdata() and rk3288_suspend_init() are
only called in the context of rockchip_suspend_init() which is already
marked __init.  We can mark them __init too.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-12 13:12:54 +02:00
Matthias Kaehlcke ac60c5e33d ARM: dts: rockchip: Add dynamic-power-coefficient for rk3288
The value was determined with the following method:

- take CPUs 1-3 offline
- for each OPP
  - set cpufreq min and max freq to OPP freq
  - start dhrystone benchmark
  - measure CPU power consumption during 10s
  - calculate Cx for OPPx
    - Cx = (Px - P1) / (Vx²fx - V1²f1)          [1]
      using the following units: mW / Ghz / V   [2]
- C = avg(C2, ..., Cn)

[1] see commit 4daa001a17 ("arm64: dts: juno: Add cpu
     dynamic-power-coefficient information")
[2] https://patchwork.kernel.org/patch/10493615/#22158551

FTR, these are the values for the different OPPs:

freq (kHz)   	mV		Px (mW)		Cx

126000		900		39
216000		900		66		370
312000		900		95		372
408000		900		122		363
600000		900		177		359
696000		950		230		363
816000		1000		297		361
1008000		1050		404		362
1200000		1100		528		362
1416000		1200		770		377
1512000		1300		984		385
1608000		1350		1156		394

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-12 12:06:09 +02:00
Heiko Stuebner 07f08d9cee ARM: dts: rockchip: bulk convert gpios to their constant counterparts
Rockchip SoCs use 2 different numbering schemes. Where the gpio-
controllers just count 0-31 for their 32 gpios, the underlying
iomux controller splits these into 4 separate entities A-D.

Device-schematics always use these iomux-values to identify pins,
so to make mapping schematics to devicetree easier Andy Yan introduced
named constants for the pins but so far we only used them on new
additions.

Using a sed-script created by Emil Renner Berthing bulk-convert
the remaining raw gpio numbers into their descriptive counterparts
and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x
mappings:

/rockchip,pins *=/bcheck
b # to end of script
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/<RK_GPIO\([0-9]\) /<\1 /g
s/<\([^ ][^ ]*  *\)0 /<\1RK_PA0 /g
s/<\([^ ][^ ]*  *\)1 /<\1RK_PA1 /g
s/<\([^ ][^ ]*  *\)2 /<\1RK_PA2 /g
s/<\([^ ][^ ]*  *\)3 /<\1RK_PA3 /g
s/<\([^ ][^ ]*  *\)4 /<\1RK_PA4 /g
s/<\([^ ][^ ]*  *\)5 /<\1RK_PA5 /g
s/<\([^ ][^ ]*  *\)6 /<\1RK_PA6 /g
s/<\([^ ][^ ]*  *\)7 /<\1RK_PA7 /g
s/<\([^ ][^ ]*  *\)8 /<\1RK_PB0 /g
s/<\([^ ][^ ]*  *\)9 /<\1RK_PB1 /g
s/<\([^ ][^ ]*  *\)10 /<\1RK_PB2 /g
s/<\([^ ][^ ]*  *\)11 /<\1RK_PB3 /g
s/<\([^ ][^ ]*  *\)12 /<\1RK_PB4 /g
s/<\([^ ][^ ]*  *\)13 /<\1RK_PB5 /g
s/<\([^ ][^ ]*  *\)14 /<\1RK_PB6 /g
s/<\([^ ][^ ]*  *\)15 /<\1RK_PB7 /g
s/<\([^ ][^ ]*  *\)16 /<\1RK_PC0 /g
s/<\([^ ][^ ]*  *\)17 /<\1RK_PC1 /g
s/<\([^ ][^ ]*  *\)18 /<\1RK_PC2 /g
s/<\([^ ][^ ]*  *\)19 /<\1RK_PC3 /g
s/<\([^ ][^ ]*  *\)20 /<\1RK_PC4 /g
s/<\([^ ][^ ]*  *\)21 /<\1RK_PC5 /g
s/<\([^ ][^ ]*  *\)22 /<\1RK_PC6 /g
s/<\([^ ][^ ]*  *\)23 /<\1RK_PC7 /g
s/<\([^ ][^ ]*  *\)24 /<\1RK_PD0 /g
s/<\([^ ][^ ]*  *\)25 /<\1RK_PD1 /g
s/<\([^ ][^ ]*  *\)26 /<\1RK_PD2 /g
s/<\([^ ][^ ]*  *\)27 /<\1RK_PD3 /g
s/<\([^ ][^ ]*  *\)28 /<\1RK_PD4 /g
s/<\([^ ][^ ]*  *\)29 /<\1RK_PD5 /g
s/<\([^ ][^ ]*  *\)30 /<\1RK_PD6 /g
s/<\([^ ][^ ]*  *\)31 /<\1RK_PD7 /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)0 /<\1RK_FUNC_GPIO /g
s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)RK_FUNC_\([1-9]\) /<\1\2 /g

Suggested-by: Emil Renner Berthing <esmil@mailme.dk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11 14:38:26 +02:00
Matthias Kaehlcke 280fa34975 ARM: dts: rockchip: Add BT_EN to the power sequence for veyron
Add GPIO D5 (BT_ENABLE_L) as reset-GPIO to the power sequence for the
Bluetooth/WiFi module. On devices with a Broadcom module the signal
needs to be asserted to use Bluetooth.

Note that BT_ENABLE_L is a misnomer in the schematics, the signal
actually is active-high.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11 13:37:47 +02:00
Matthias Kaehlcke 2f60eb2f03 ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron
Some veyron devices have a Bluetooth controller connected on UART0.
The UART needs to operate at a high speed, however setting the clock
rate at initialization has no practical effect. During initialization
user space adjusts the UART baudrate multiple times, which ends up
changing the SCLK rate. After a successful initiatalization the clk
is running at the desired speed (48MHz).

Remove the unnecessary clock rate configuration from the DT.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-04-11 13:35:55 +02:00
Yannick Fertré 3fca6a1ab9 ARM: dts: stm32: enable cec on stm32mp157a-dk1 board
Enable CEC (Consumer Electronics Control) device.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:07 +02:00
Yannick Fertré 5eaae04941 ARM: dts: stm32: add cec pins muxing on stm32mp157
Add a new pin muxing for cec.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:07 +02:00
Yannick Fertré 63834ff2d6 ARM: dts: stm32: add ltdc pins muxing on stm32mp157
Add ltdc pins muxing on stm32mp157.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:06 +02:00
Yannick Fertré f85c8acc7a ARM: dts: stm32: add I2C sleep pins muxing on stm32mp157
Add I2C sleep pins muxing for low power mode.

Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:06 +02:00
Yannick Fertré 81987fff52 ARM: dts: stm32: add power supply of otm8009a on stm32mp157c-dk2
This patch adds a new property (power-supply) to panel otm8009a (orisetech)
on stm32mp157c-dk2  & regulator v3v3.

Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:06 +02:00
Gabriel Fernandez 09666b76f3 ARM: dts: stm32: Enable STM32F769 clock driver
This patch enables clocks for STM32F769 boards.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:05 +02:00
Pascal Paillet b3e993a617 ARM: dts: stm32: add stpmic1 support on stm32mp157a dk1 board
This patch adds stpmic1 support on stm32mp157a dk1 board.
The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10
regulators, 3 power switches, a watchdog and an input for a power on key.
The DMAs are disabled because the PMIC generates a very few traffic and
DMA channels may lack for other usage.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:05 +02:00
Pascal Paillet 9c559b1565 ARM: dts: stm32: add stpmic1 support on stm32mp157c ed1 board
This patch adds stpmic1 support on stm32mp157c ed1 board.
The STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10
regulators, 3 power switches, a watchdog and an input for a power on key.
The DMAs are disabled because the PMIC generates a very few traffic and
DMA channels may lack for other usage.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:04 +02:00
Olivier Moysan 94d3d6f4dc ARM: dts: stm32: add spdfirx pins to stm32mp157c
This patch adds spdifrx support on stm32mp157c eval board.

Signed-off-by: Olivier Moysan <olivier.moysan@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:04 +02:00
Olivier Moysan 411435d390 ARM: dts: stm32: add spdifrx support on stm32mp157c
This patch adds support of STM32 SPDIFRX on
stm32mp157c.

Signed-off-by: Olivier Moysan <olivier.moysan@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:04 +02:00
Fabrice Gasnier 8d07b78c3e ARM: dts: stm32: Add romem and temperature calibration on stm32f429
Add & enable stm32 factory-programmed memory. Describe temperature sensor
calibration cells.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:03 +02:00
Fabrice Gasnier 3024c18543 ARM: dts: stm32: Add romem and temperature calibration on stm32mp157c
Add & enable stm32 factory-programmed memory. Describe temperature sensor
calibration cells. Non-volatile calibration data is made available by
stm32mp157c bootrom in bsec_dataX registers.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:03 +02:00
Fabrice Gasnier 0f57950695 ARM: dts: stm32: Add clock on stm32mp157c syscfg
STM32 syscfg needs a clock to access registers.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:02 +02:00
Fabien Dessenne 682d099514 ARM: dts: stm32: enable IPCC mailbox support on STM32MP157a-dk1
Enable STM32 IPCC mailbox driver for STM32MP157a-dk1 board.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:02 +02:00
Fabien Dessenne 679d9dac52 ARM: dts: stm32: enable IPCC mailbox support on STM32MP157c-ed1
Enable STM32 IPCC mailbox driver for STM32MP157c-ed1 board.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:02 +02:00
Fabien Dessenne eb2493172f ARM: dts: stm32: add IPCC mailbox support on STM32MP157c
Add configuration on DT for IPCC mailbox driver.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:01 +02:00
Ludovic Barre 8f6e0919b7 ARM: dts: stm32: add sdmmc1 support on stm32mp157a dk1 board
This patch adds sdmmc1 support on stm32mp157a dk1 board.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:01 +02:00
Ludovic Barre 379edbe434 ARM: dts: stm32: add sdmmc1 support on stm32mp157c ed1 board
This patch adds sdmmc1 support on stm32mp157c ed1 board.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:00 +02:00
Ludovic Barre 8d17cf7a8e ARM: dts: stm32: add sdmmc1 support on stm32mp157c
This patch adds support of sdmmc1 on stm32mp157c.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:00 +02:00
Ludovic Barre 30a8e03a1f ARM: dts: stm32: add sdmmc1 support on stm32h743i disco board
This patch adds sdmmc1 support on stm32h743i disco board.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:22:00 +02:00
Ludovic Barre 90f16fea40 ARM: dts: stm32: add sdmmc1 support on stm32h743i eval board
This patch adds sdmmc1 support on stm32h743i eval board.
This board has an external driver to control signal direction polarity.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:21:59 +02:00
Ludovic Barre 61c0f6b8b4 ARM: dts: stm32: add sdmmc1 support on stm32h743
This patch adds support of sdmmc1 on stm32h743.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-04-11 11:21:59 +02:00
Anson Huang 35dc29ef0f ARM: dts: imx6dl-sabreauto: update opp table for auto part
Update i.MX6DL automotive part's opp table according to i.MX6DL
automotive datasheet Rev.9, 11/2018, it adds 996MHz set-point
support as below:

LDO enabled(min value):
996MHz: VDDARM: 1.275V, VDDSOC: 1.175V;
792MHz: VDDARM: 1.150V, VDDSOC: 1.150V;
396MHz: VDDARM: 1.125V, VDDSOC: 1.150V;

Adding 25mV to cover board IR drop, for LDO enabled mode of 996MHz,
as the max value of LDO output can NOT exceed 1.3V, so 25mV is NOT
added for VDDARM.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 14:59:33 +08:00
Fabio Estevam 00e3ff8b98 ARM: dts: imx: Use generic node names for Zii dts
The devicetree specification recommends using generic node names.

Some Zii dts files already follow such recommendation, but some don't,
so use generic node names for consistency among the Zii dts files.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 13:51:09 +08:00
Fabio Estevam 7ee137a96a ARM: dts: imx: Switch Zii dts to SPDX identifier
Adopt the SPDX license identifier headers to ease license compliance
management.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 13:50:55 +08:00
Adam Ford 7aedca8750 ARM: dts: imx6q-logicpd: Reduce inrush current on USBH1
Some USB peripherals draw more power, and the sourcing regulator
take a little time to turn on.  This patch fixes an issue where
some devices occasionally do not get detected, because the power
isn't quite ready when communication starts, so we add a bit
of a delay.

Fixes: 1c207f911f ("ARM: dts: imx: Add support for Logic PD i.MX6QD EVM")
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 13:45:03 +08:00
Adam Ford dbb58e291c ARM: dts: imx6q-logicpd: Reduce inrush current on start
The main 3.3V regulator sources a series of additional regulators.
This patch adds a small delay, so when the 3.3V regulator comes
on it delays a bit before the subsequent regulators can come on.
This reduces the inrush current a bit on the external DC power
supply to help prevent a situation where the sourcing power supply
cannot source enough current and overloads and the kit fails to
start.

Fixes: 1c207f911f ("ARM: dts: imx: Add support for Logic PD i.MX6QD EVM")
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 13:44:44 +08:00
Adam Ford 6fd6d6f6a2 ARM: dts: imx6q-logicpd: Shutdown LCD regulator during suspend
The LCD power sequencer is very finicky.  The backlight cannot
be driven until after the sequencer is done.  Until now, the
regulators were marked with 'regulator-always-on' to make sure
it came up before the backlight.  This patch allows the LCD
regulators to power down and prevent the backlight from being
used again until the sequencer is ready.  This reduces
standby power consumption by ~100mW.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 13:44:12 +08:00
Adam Ford 45d9125040 ARM: dts: imx6q-logicpd: Enable Analog audio capture
The original submission had functional audio out and was based
on reviewing other boards using the same wm8962 codec. However,
the Logic PD board uses an analog microphone which was being
disabled for a digital mic.  This patch corrects that and
explicitly sets the gpio-cfg pins all to 0x0000 which allows the
analog microphone to capture audio.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 13:44:00 +08:00
Anson Huang 4b08ecc7c6 ARM: dts: imx6sll: add cooling-cells for cpu-freq cooling device
Add #cooling-cells for i.MX6SLL cpu-freq cooling device usage.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 13:08:55 +08:00
Jonathan Neuschäfer 891d940aef ARM: dts: imx50: Add Kobo Aura DTS
The Kobo Aura is an e-book reader released in 2013.

With the devicetree in its current state, the kernel will boot and run
for about ten seconds. To solve this, the embedded controller needs to
be told that the system should stay powered on. This will be done in a
later patchset.

- The IOMUXC mode bits for the SD interfaces were taken from the
  vendor's U-Boot fork.
- The bus width of the eMMC is 4 bits in the vendor kernel, but I
  achieved better performance with 8 bits.
- The SDIO clock frequency for the WiFi chip is 25MHz in the vendor
  kernel, but the WiFi chip (BCM43362) supports 50MHz, which works
  reliably on this board and gives slightly better performance.
- The I2C pins' IOMUXC settings come from the vendor's U-Boot fork.

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 11:06:01 +08:00
Fabio Estevam 0672d22a19 ARM: dts: imx: Fix the AR803X phy-mode
Commit 6d4cd041f0 ("net: phy: at803x: disable delay only for RGMII mode")
exposed an issue on imx DTS files using AR8031/AR8035 PHYs.

The end result is that the boards can no longer obtain an IP address
via UDHCP, for example.

Quoting Andrew Lunn:

"The problem here is, all the DTs were broken since day 0. However,
because the PHY driver was also broken, nobody noticed and it
worked. Now that the PHY driver has been fixed, all the bugs in the
DTs now become an issue"

To fix this problem, the phy-mode property needs to be "rgmii-id",  which
has the following meaning as per
Documentation/devicetree/bindings/net/ethernet.txt:

"RGMII with internal RX and TX delays provided by the PHY, the MAC should
not add the RX or TX delays in this case)"

Tested on imx6-sabresd, imx6sx-sdb and imx7d-pico boards with
successfully restored networking.

Based on the initial submission from Steve Twiss for the
imx6qdl-sabresd.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Tested-by: Soeren Moch <smoch@web.de>
Tested-by: Steve Twiss <stwiss.opensource@diasemi.com>
Tested-by: Adam Thomson <Adam.Thomson@diasemi.com>
Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com>
Tested-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:57:56 +08:00
Andrew F. Davis cadb32a9c1 ARM: dts: imx6qdl-var-dart: Use new CODEC reset pin name
The correct DT property for specifying a GPIO used for reset
is "reset-gpios", the driver now accepts this name, use it here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:41:55 +08:00
Andrew F. Davis c83bbdc227 ARM: dts: imx6qdl-gw5903: Use new CODEC reset pin name
The correct DT property for specifying a GPIO used for reset
is "reset-gpios", the driver now accepts this name, use it here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:41:52 +08:00
Andrew F. Davis 1268d8339c ARM: dts: mx6qdl-zii-rdu2: Use new CODEC reset pin name
The correct DT property for specifying a GPIO used for reset
is "reset-gpios", the driver now accepts this name, use it here.

Note the GPIO polarity in the driver was ignored before and always
assumed to be active low, when all the DTs are fixed we will start
respecting the specified polarity. Switch polarity in DT to the
currently assumed one, this way when the driver changes the
behavior will not change.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:40:28 +08:00
Andrey Smirnov b7b4fda263 ARM: dts: imx50: Specify IMX5_CLK_IPG as "ahb" clock to SDMA
Since 25aaa75df1 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX5_CLK_SDMA results in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA funtionality. Fix the code
to specify IMX5_CLK_AHB as "ahb" clock for SDMA, to avoid detecting
incorrect clock ratio.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Angus Ainslie (Purism) <angus@akkea.ca>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:27:36 +08:00
Andrey Smirnov 918bbde808 ARM: dts: imx51: Specify IMX5_CLK_IPG as "ahb" clock to SDMA
Since 25aaa75df1 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX5_CLK_SDMA results in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA funtionality. Fix the code
to specify IMX5_CLK_AHB as "ahb" clock for SDMA, to avoid detecting
incorrect clock ratio.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Angus Ainslie (Purism) <angus@akkea.ca>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:27:33 +08:00
Andrey Smirnov 28c168018e ARM: dts: imx53: Specify IMX5_CLK_IPG as "ahb" clock to SDMA
Since 25aaa75df1 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX5_CLK_SDMA results in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA funtionality. Fix the code
to specify IMX5_CLK_AHB as "ahb" clock for SDMA, to avoid detecting
incorrect clock ratio.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Angus Ainslie (Purism) <angus@akkea.ca>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:27:30 +08:00
Andrey Smirnov cc839d0f8c ARM: dts: imx6sx: Specify IMX6SX_CLK_IPG as "ahb" clock to SDMA
Since 25aaa75df1 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX6SL_CLK_SDMA results in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA funtionality. Fix the code
to specify IMX6SL_CLK_AHB as "ahb" clock for SDMA, to avoid detecting
incorrect clock ratio.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Angus Ainslie (Purism) <angus@akkea.ca>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:27:27 +08:00
Andrey Smirnov c5ed5daa65 ARM: dts: imx6sll: Specify IMX6SLL_CLK_IPG as "ipg" clock to SDMA
Since 25aaa75df1 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX6SLL_CLK_SDMA result in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA funtionality. Fix the code
to specify IMX6SLL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting
incorrect clock ratio.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Angus Ainslie (Purism) <angus@akkea.ca>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:27:25 +08:00
Andrey Smirnov 7b3132ecef ARM: dts: imx6ul: Specify IMX6UL_CLK_IPG as "ipg" clock to SDMA
Since 25aaa75df1 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX6UL_CLK_SDMA results in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA funtionality. Fix the code
to specify IMX6UL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting
incorrect clock ratio.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Angus Ainslie (Purism) <angus@akkea.ca>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:27:19 +08:00
Andrey Smirnov 412b032a1d ARM: dts: imx7d: Specify IMX7D_CLK_IPG as "ipg" clock to SDMA
Since 25aaa75df1 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX7D_CLK_SDMA results in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA funtionality. Fix the code
to specify IMX7D_CLK_IPG as "ipg" clock for SDMA, to avoid detecting
incorrect clock ratio.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Angus Ainslie (Purism) <angus@akkea.ca>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:27:16 +08:00
Andrey Smirnov 8979117765 ARM: dts: imx6sx: Specify IMX6SX_CLK_IPG as "ipg" clock to SDMA
Since 25aaa75df1 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX6SX_CLK_SDMA results in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA funtionality. Fix the code
to specify IMX6SX_CLK_IPG as "ipg" clock for SDMA, to avoid detecting
incorrect clock ratio.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Angus Ainslie (Purism) <angus@akkea.ca>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:27:14 +08:00
Andrey Smirnov b14c872eeb ARM: dts: imx6qdl: Specify IMX6QDL_CLK_IPG as "ipg" clock to SDMA
Since 25aaa75df1 SDMA driver uses clock rates of "ipg" and "ahb"
clock to determine if it needs to configure the IP block as operating
at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
clocks as IMX6QDL_CLK_SDMA results in driver incorrectly thinking that
ratio is 1:1 which results in broken SDMA funtionality(this at least
breaks RAVE SP serdev driver on RDU2). Fix the code to specify
IMX6QDL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect
clock ratio.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Angus Ainslie (Purism) <angus@akkea.ca>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:27:11 +08:00
Rui Miguel Silva e345fd4249 ARM: dts: imx7s-warp: add ov2680 sensor node
Warp7 comes with a Omnivision OV2680 sensor, add the node here to make
complete the camera data path for this system. Add the needed regulator
to the analog voltage supply, the port and endpoints in mipi_csi node
and the pinctrl for the reset gpio.

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:23:47 +08:00
Rui Miguel Silva 2cd37a97d1 ARM: dts: imx7s-warp: add csi and mipi_csi node
Add and enable csi and mipi_csi nodes.

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:23:34 +08:00
Rui Miguel Silva 6a2736fccf ARM: dts: imx7s: Add video mux, csi and mipi_csi
Add device tree nodes for csi, video multiplexer and mipi-csi.

Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-11 10:23:18 +08:00