Commit Graph

9 Commits

Author SHA1 Message Date
Xiang Chen ce60689e12 scsi: hisi_sas: add v3 code to send ATA frame
Add code to prepare ATA frame for v3 hw

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-06-19 21:31:26 -04:00
Xiang Chen fa913de23a scsi: hisi_sas: add v3 code to send SMP frame
Add code to prepare SMP frame.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-06-19 21:31:26 -04:00
Xiang Chen a2204723ac scsi: hisi_sas: add v3 code to send SSP frame
Add code to prepare SSP frame and deliver it to hardware.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-06-19 21:31:26 -04:00
Xiang Chen 60b4a5ee90 scsi: hisi_sas: add v3 cq interrupt handler
Add v3 cq interrupt handler slot_complete_v3_hw().

Note: The slot error handling needs to be further refined in the future
to examine all fields in the error record, and handle appropriately,
instead of current solution - just report SAS_OPEN_REJECT.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-06-19 21:31:26 -04:00
Xiang Chen 54edeee1e1 scsi: hisi_sas: add phy up/down/bcast and channel ISR
Add code to initialise interrupts and add some interrupt handlers.

Also add function hisi_sas_v3_destroy_irqs() to clean-up irqs upon
module unloading.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-06-19 21:31:26 -04:00
Xiang Chen 3975f6054e scsi: hisi_sas: add v3 hw PHY init
Add code to configure PHYs for v3 hw.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-06-19 21:31:26 -04:00
Xiang Chen c94d8ca2b1 scsi: hisi_sas: add v3 hw init
Add code to initialise v3 hardware.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-06-19 21:31:25 -04:00
John Garry e21fe3a526 scsi: hisi_sas: add initialisation for v3 pci-based controller
Add the code to initialise the controller which is based on pci device
in hisi_sas_v3_hw.c

The core controller routines are still in hisi_sas_main.c; some common
initialisation functions are also exported from hisi_sas_main.c

For pci-based controller, the device properties, like phy count and sas
address are read from the firmware, same as platform device-based
controller.

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-06-19 21:31:25 -04:00
John Garry 92f61e3bc2 scsi: hisi_sas: add skeleton v3 hw driver
Add skeleton driver for v3 hw in hisi_sas_v3_hw.c

File hisi_sas_v3_hw.c will serve 2 purposes:
- probing and initialisation of the controller based on pci device
- hw layer for v3-based controllers

The controller design is quite similar to v2 hw in hip07.

However key differences include:
-All v2 hw bugs are fixed (hopefully), so workarounds are not required
-support for device deregistration
-some interrupt modifications
-configurable max device support

Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2017-06-19 21:31:25 -04:00