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3 Commits

Author SHA1 Message Date
Pawel Moll 5f8f5a62a6 ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses 
... to enable use of LPAE, which extends physical address space
to 40 bits.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
 2012-07-13 11:48:28 +01:00
Pawel Moll e29b65dbc5 ARM: vexpress: Device Tree updates 
* Added extra regs for A15 VGIC
* Added A15 architected timer node
* Split A5 and A9 TWD nodes into two separate ones for timer
  and watchdog; interrupt definitions fixed on the way
* Fixed typo in A5 GIC compatible value

All the changes courtesy of Marc Zyngier.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
 2012-05-21 09:30:37 +01:00
Pawel Moll 059289b260 ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant) 
This patch adds Device Tree file for the CoreTile Express A15x2
(V2P-CA15) with Test Chip 1.

As the chip's GIC has 160 interrupt inputs and equivalent SMM
(FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
increased.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
 2012-02-24 09:18:21 +00:00