Commit Graph

184 Commits

Author SHA1 Message Date
Dave Airlie 91915260ea Merge tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Bit a bit -fixes pull request in the merge window than usual dua to two
feauture-y things:
- Display CRCs are now enabled on all platforms, including the odd DP case
  on gm45/vlv. Since this is a testing-only feature it should ever hurt,
  but I figured it'll help with regression-testing -fixes. So I left it
  in and didn't postpone it to 3.14.
- Display power well refactoring from Imre. Would have caused major pain
  conflict with the bdw stage 1 patches if I'd postpone this to -next.
  It's only an relatively small interface rework, so shouldn't cause pain.
  It's also been in my tree since almost 3 weeks already.

That accounts for about two thirds of the pull, otherwise just bugfixes:
- vlv backlight fix from Jesse/Jani
- vlv vblank timestamp fix from Jesse
- improved edp detection through vbt from Ville (fixes a vlv issue)
- eDP vdd fix from Paulo
- fixes for dvo lvds on i830M
- a few smaller things all over

Note: This contains a backmerge of v3.12. Since the -internal branch
always applied on top of -nightly I need that unified base to merge bdw
patches. So you'll get a conflict with radeon connector props when pulling
this (and nouveau/master will also conflict a bit when Ben doesn't
rebase). The backmerge itself only had conflicts in drm/i915.

There's also a tiny conflict between Jani's backlight fix and your sysfs
lifetime fix in drm-next.

* tag 'drm-intel-fixes-2013-11-07' of git://people.freedesktop.org/~danvet/drm-intel: (940 commits)
  drm/i915/vlv: use per-pipe backlight controls v2
  drm/i915: make backlight functions take a connector
  drm/i915: move opregion asle request handling to a work queue
  drm/i915/vlv: use PIPE_START_VBLANK interrupts on VLV
  drm/i915: Make intel_dp_is_edp() less specific
  drm/i915: Give names to the VBT child device type bits
  drm/i915/vlv: enable HDA display audio for Valleyview2
  drm/i915/dvo: call ->mode_set callback only when the port is running
  drm/i915: avoid unclaimed registers when capturing the error state
  drm/i915: Enable DP port CRC for the "auto" source on g4x/vlv
  drm/i915: scramble reset support for DP port CRC on vlv
  drm/i915: scramble reset support for DP port CRC on g4x
  drm/i916: add "auto" pipe CRC source
  ...

Conflicts:
	MAINTAINERS
	drivers/gpu/drm/i915/intel_panel.c
	drivers/gpu/drm/nouveau/core/subdev/mc/base.c
	drivers/gpu/drm/radeon/atombios_encoders.c
	drivers/gpu/drm/radeon/radeon_connectors.c
2013-11-08 16:34:39 +10:00
Christian König 24c164393d drm/radeon: drop CP page table updates & cleanup v2
The DMA ring seems to be stable now.

v2: remove pt_ring_index as well

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01 15:25:52 -04:00
Marek Olšák 1dac28eb72 drm/radeon: don't use PACKET2 on CIK
It is said to cause hangs.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01 15:25:51 -04:00
Alex Deucher 6ba81e538a drm/radeon: fix endian handling in rlc buffer setup
The buffers needs to be in little endian format.

Noticed-by: Sylvain BERTRAND <sylware@legeek.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01 15:25:48 -04:00
Alex Deucher c9dbd70552 drm/radeon: implement blit copy callback for CIK
Uses the CP ring rather than the DMA ring.  Useful
for debugging and benchmarking.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01 12:43:16 -04:00
Alex Deucher 6214bb7487 drm/radeon: add a connector property for dither
Allows you to enable dither in the display hardware
when the monitor supports lower a lower bpc than the
current framebuffer format.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01 12:43:13 -04:00
Alex Deucher 134b480f4b drm/radeon: Add support for programming the FMT blocks
The FMT blocks control how data is sent from the backend
of the display pipe to to monitor.  Proper set up of the
FMT blocks are required for 30bpp formats.  Additionally,
dithering can be enabled on for better display with 18 and
24bpp displays.  The exception is LVDS/eDP which atom
takes care of in the SelectCRTC_Source table.  For now
just enable truncation until we test dithering more.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-01 12:43:12 -04:00
Alex Deucher d30d71e85a drm/radeon: make missing smc ucode non-fatal (CI)
Prevent driver load problems if the smc is missing.

bug:
https://bugzilla.kernel.org/show_bug.cgi?id=63011

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-18 16:16:17 -04:00
Christian König 5510f124c6 drm/radeon: stop the leaks in cik_ib_test
Stop leaking IB memory and scratch register space when the test fails.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-18 16:16:16 -04:00
Alex Deucher fb2c7f4d2e drm/radeon: improve soft reset on CIK
Disable CG/PG before resetting.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-10-09 17:13:49 -04:00
Alex Deucher 13c5bfdad7 drm/radeon/cik: fix overflow in vram fetch
Missing ULL when calculating the amount of vram
leads to an overflow when the amount of vram is >= 4G.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-09-24 11:01:24 -04:00
Michel Dänzer a537314e0b drm/radeon/cik: Fix encoding of number of banks in tiling configuration info
There are multiple valid values, not just 0 or 1.  Required
to properly support 2D tiling in the userspace drivers.

Cc: stable@vger.kernel.org
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-20 17:32:58 -04:00
Michel Dänzer 328a50c7b0 drm/radeon/cik: Fix printing of client name on VM protection fault
The string is encoded from the MSB to the LSB of the register.

Cc: stable@vger.kernel.org
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-20 14:28:16 -04:00
Alex Deucher 2b19d17fbd drm/radeon: fix typo in PG flags
s/CG/PG/ in the GFX powergating flag name.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-11 11:44:31 -04:00
Alex Deucher 7c4622d541 drm/radeon/cik: update gpu_init for an additional berlin gpu
Sets the right paramters for the new pci id.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-09-11 11:44:30 -04:00
Alex Deucher 0a5b7b0bd9 drm/radeon: add spinlocks for indirect register accesss
This adds spinlocks to protect access to other
indirect register apertures.  These indirect spaces are
used pretty infrequently and we haven't had an reported
problems, but better safe than sorry.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-11 11:44:29 -04:00
Alex Deucher 4214faf621 drm/radeon/cik: properly handle internal cp ints
The internal cp interrupts need to be enabled and
disabled at specific times in order clockgating to
work properly.  This patch changes the handling
of the CP_INT_CNTL register to respect the current
state of the internal CP interrupts when making
changes to the other interrupts in CP_INT_CNTL.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-11 11:44:23 -04:00
Dave Airlie 9c725e5bcd Merge branch 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes:
This is the radeon drm-next request.  Big changes include:
- support for dpm on CIK parts
- support for ASPM on CIK parts
- support for berlin GPUs
- major ring handling cleanup
- remove the old 3D blit code for bo moves in favor of CP DMA or sDMA
- lots of bug fixes

[airlied: fix up a bunch of conflicts from drm_order removal]

* 'drm-next-3.12' of git://people.freedesktop.org/~agd5f/linux: (898 commits)
  drm/radeon/dpm: make sure dc performance level limits are valid (CI)
  drm/radeon/dpm: make sure dc performance level limits are valid (BTC-SI) (v2)
  drm/radeon: gcc fixes for extended dpm tables
  drm/radeon: gcc fixes for kb/kv dpm
  drm/radeon: gcc fixes for ci dpm
  drm/radeon: gcc fixes for si dpm
  drm/radeon: gcc fixes for ni dpm
  drm/radeon: gcc fixes for trinity dpm
  drm/radeon: gcc fixes for sumo dpm
  drm/radeonn: gcc fixes for rv7xx/eg/btc dpm
  drm/radeon: gcc fixes for rv6xx dpm
  drm/radeon: gcc fixes for radeon_atombios.c
  drm/radeon: enable UVD interrupts on CIK
  drm/radeon: fix init ordering for r600+
  drm/radeon/dpm: only need to reprogram uvd if uvd pg is enabled
  drm/radeon: check the return value of uvd_v1_0_start in uvd_v1_0_init
  drm/radeon: split out radeon_uvd_resume from uvd_v4_2_resume
  radeon kms: fix uninitialised hotplug work usage in r100_irq_process()
  drm/radeon/audio: set up the sads on DCE3.2 asics
  drm/radeon: fix handling of variable sized arrays for router objects
  ...

Conflicts:
	drivers/gpu/drm/i915/i915_dma.c
	drivers/gpu/drm/i915/i915_gem_dmabuf.c
	drivers/gpu/drm/i915/intel_pm.c
	drivers/gpu/drm/radeon/cik.c
	drivers/gpu/drm/radeon/ni.c
	drivers/gpu/drm/radeon/r600.c
2013-09-02 09:31:40 +10:00
Christian König 6a3808b823 drm/radeon: enable UVD interrupts on CIK
The same as on evergreen.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reported-by: FrankR Huang <FrankR.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-08-30 16:31:15 -04:00
Alex Deucher e5903d399a drm/radeon: fix init ordering for r600+
The vram scratch buffer needs to be initialized
before the mc is programmed otherwise we program
0 as the GPU address of the default GPU fault
page.  In most cases we put vram at zero anyway and
reserve a page for the legacy vga buffer so in practice
this shouldn't cause any problems, but better to make
it correct.

Was changed in:
6fab3febf6

Reported-by: FrankR Huang <FrankR.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-08-30 16:31:15 -04:00
Alex Deucher 2ce529dac7 drm/radeon: split out radeon_uvd_resume from uvd_v4_2_resume
For powergating, we just need to re-init the registers, there
is no need to restore the uvd BOs.  This just adds needless
work when powergating uvd for playback while the system is
on.  We only need to restore the uvd BOs on an actual resume
from suspend or when the driver loads.

This fixes multi-stream UVD playback on KB systems.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2013-08-30 16:31:12 -04:00
Alex Deucher b2e4c70a97 drm/radeon: fill in gpu_init for berlin GPU cores
This fills in the GPU specific details for berlin
GPU cores so that the driver will work with them.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-08-30 16:31:08 -04:00
Alex Deucher bc01a8c7a2 drm/radeon: update line buffer allocation for dce8
We need to allocate line buffer to each display when
setting up the watermarks.  Failure to do so can lead
to a blank screen.  This fixes blank screen problems
on dce8 asics.

Based on an initial fix from:
Jay Cornwall <jay.cornwall@amd.com>

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-08-30 16:31:01 -04:00
Alex Deucher a0f38609c9 drm/radeon/cik: properly set up the clearstate buffer for pg (v2)
The format of the clearstate buffer used for pg (powergating)
changed between NI and SI.  This formats it properly for what
the hardware expects on SI+.

v2: fix addresses

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:56 -04:00
Alex Deucher ddc76ff6c7 drm/radeon: fixes for gfx clockgating on CIK
Clockgating requires signalling between the CP and the
RLC to work properly.  Resetting the CP block in the
CP resume code messed up the internal coordination
between the blocks.  Removing the reset allows gfx
clockgating to work properly.  However, when gfx clock
gating is enabled, there is a strange interaction with
dpm which causes the chip to stay in the high performance
level all the time, so leave gfx clockgating disabled
for now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:55 -04:00
Alex Deucher 473359bc28 drm/radeon: restructure cg/pg on cik (v2)
- use new cg/pg flags for finer grained clock and
powergating control
- restructure the cg/pg code so it can be called from
other components such as dpm

v2: fix build breakage from rebase

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:54 -04:00
Alex Deucher b530602fd4 drm/radeon: add audio support for DCE6/8 GPUs (v12)
Similar to DCE4/5, but supports multiple audio pins
which can be assigned per afmt block.

v2: rework the driver to handle more than one audio
pin.
v3: try different dto reg
v4: properly program dto
v5 (ck): change dto programming order
v6: program speaker allocation block
v7: rebase
v8: rebase on Rafał's changes
v9: integrated Rafał's comments, update to latest
    drm_edid_to_speaker_allocation API
v10: add missing line break in error message
v11: add back audio enabled messages
v12: fix copy paste typo in r600_audio_enable

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
2013-08-30 16:30:45 -04:00
Christian König 2483b4ea98 drm/radeon: separate DMA code
Similar to separating the UVD code, just put the DMA
functions into separate files.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:42 -04:00
Christian König e409b12862 drm/radeon: separate UVD code v3
Our different hardware blocks are actually completely
separated, so it doesn't make much sense any more to
structure the code by pure chipset generations.

Start restructuring the code by separating our the UVD block.

v2: updated commit message
v3: rebased and restructurized start/stop functions for kv dpm.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:42 -04:00
Christian König 2e1e6dad6a drm/radeon: remove special handling for the DMA ring
Now that we have callbacks for [rw]ptr handling we can
remove the special handling for the DMA rings and use
the callbacks instead.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:41 -04:00
Christian König 02c9f7fa4e drm/radeon: rework UVD writeback & [rw]ptr handling
The hardware just doesn't support this correctly.
Disable it before we accidentally write anywhere we shouldn't.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:40 -04:00
Alex Deucher 77df508a98 drm/radeon/dpm: implement UVD powergating for KB/KV
Powergate the UVD block when not in use to save power.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:35 -04:00
Alex Deucher 5e884f606c drm/radeon: restructure UVD code to handle UVD PG (v2)
When we PG (powergate) UVD, we need to re-initialize it
before we can use it again.

v2: rebase on UVD stop fixes

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:34 -04:00
Alex Deucher cc8dbbb4f6 drm/radeon: add dpm support for CI dGPUs (v2)
This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching

Set radeon.dpm=1 to enable.

v2: remove unused radeon_atombios.c changes,
    make missing smc ucode non-fatal

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:29 -04:00
Alex Deucher 41a524abff drm/radeon/kms: add dpm support for KB/KV
This adds dpm support for KB/KV asics.  This includes:
- dynamic engine clock scaling
- dynamic voltage scaling
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:28 -04:00
Alex Deucher 286d9cc67a drm/radeon: add get_temperature() callbacks for CIK (v2)
This added support for the on-chip thermal sensors on
CIK asics.

v2: fix register offset.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:15 -04:00
Alex Deucher a412fce054 drm/radeon/cik: add rlc helpers for DPM
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:12 -04:00
Alex Deucher 22c775ce80 drm/radeon: implement clock and power gating for CIK (v3)
Only the APUs support power gating.

v2: disable cgcg for now
v3: workaround hw issue in mgcg

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:08 -04:00
Alex Deucher 1fd11777c2 drm/radeon: convert SI,CIK to use sumo_rlc functions
and remove duplicate si_rlc functions.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:08 -04:00
Alex Deucher 866d83de0c drm/radeon/cik: restructure rlc setup
Restructure rlc setup to handle clock and power
gating.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:06 -04:00
Alex Deucher 7235711a43 drm/radeon: add support for ASPM on CIK asics
Enables PCIE ASPM (Active State Power Management) on
CIK asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:05 -04:00
Alex Deucher 8a7cd27679 drm/radeon/cik: add support for pcie gen1/2/3 switching
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:04 -04:00
Alex Deucher 8c68e39388 drm/radeon: switch CIK to use radeon_ucode.h
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:04 -04:00
Alex Deucher 58ea2deab3 drm/radeon/kms: fix up dce8 display watermark calc for dpm
Calculate the low and high watermarks based on the low and high
clocks for the current power state.  The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:02 -04:00
Alex Deucher f61d5b4677 drm/radeon/cik: use a mutex to properly lock srbm instanced registers
We need proper locking in the driver when accessing instanced
registers on CIK.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:18 -04:00
Christian König 4ad9c1c774 drm/radeon: only save UVD bo when we have open handles
Otherwise just reinitialize from scratch on resume,
and so make it more likely to succeed.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:15 -04:00
Alex Deucher 6fab3febf6 drm/radeon: always program the MC on startup
For r6xx+ asics.  This mirrors the behavior of pre-r6xx
asics.  We need to program the MC even if something
else in startup() fails.  Failure to do so results in
an unusable GPU.

Based on a fix from: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-08-07 17:37:14 -04:00
Christian König 2858c00d28 drm/radeon: fix halting UVD
Removing the clock/power or resetting the VCPU can cause
hangs if that happens in the middle of a register write.

Stall the memory and register bus before putting the VCPU
into reset. Keep it in reset when unloading the module or
suspending.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:11 -04:00
Daniel Vetter b72a8925fd drm/radeon: s/drm_order/order_base_2/
Last driver and pretty obviously a major user of this little function.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
2013-07-23 20:14:24 +10:00
Christian König 9cc2e0e9f1 drm/radeon: never unpin UVD bo v3
Changing the UVD BOs offset on suspend/resume doesn't work because the VCPU
internally keeps pointers to it. Just keep it always pinned and save the
content manually.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=66425

v2: fix compiler warning
v3: fix CIK support

Note: a version of this patch needs to go to stable.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14 10:11:30 -04:00
Alex Deucher 3ec7d11b9a drm/radeon: add fault decode function for CIK
Helpful for debugging GPUVM errors as we can see what
hw block and page generated the fault in the log.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14 10:11:29 -04:00
Jerome Glisse 0a16893397 drm/radeon: use radeon device for request firmware
Avoid creating temporary platform device that will lead to issue
when several radeon gpu are in same computer. Instead directly use
the radeon device for requesting firmware.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14 10:11:27 -04:00
Alex Deucher b0fe3d39f6 drm/radeon: fix typo in cik_select_se_sh()
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 19:40:10 -04:00
Alex Deucher 39aee49028 drm/radeon: add cik tile mode array query
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:12 -04:00
Alex Deucher 0aafd3133f drm/radeon/cik: add support for golden register init
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:11 -04:00
Alex Deucher 2b0781a60e drm/radeon/cik: add support for compute interrupts
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:10 -04:00
Alex Deucher b07fdd3832 drm/radeon: fix up ring functions for compute rings
The compute rings use RELEASE_MEM rather then EOP
packets for writing fences and there is no SYNC_PFP_ME
packet on the compute rings.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:09 -04:00
Alex Deucher 2615b53ace drm/radeon/cik: switch to type3 nop packet for compute rings (v2)
Type 2 packets are deprecated on CIK MEC and we should use
type 3 nop packets.  Setting the count field to the max value
(0x3fff) indicates that only one dword should be skipped
like a type 2 packet.

v2: add comment to code

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27 10:49:09 -04:00
Alex Deucher 963e81f9e0 drm/radeon/cik: Add support for compute queues (v4)
On CIK, the compute rings work slightly differently than
on previous asics, however the basic concepts are the same.

The main differences:
- New MEC engines for compute queues
- Multiple queues per MEC:
  - CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues
  -    KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues
- Queues can be allocated and scheduled by another queue
- New doorbell aperture allows you to assign space in the aperture
  for the wptr which allows for userspace access to queues

v2: add wptr shadow, fix eop setup
v3: fix comment
v4: switch to new callback method

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27 10:49:08 -04:00
Alex Deucher 75efdee11b drm/radeon: implement simple doorbell page allocator
The doorbell aperture is a PCI BAR whose pages can be
mapped to compute resources for things like wptrs
for userspace queues.

This patch maps the BAR and sets up a simple allocator
to allocate pages from the BAR.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:07 -04:00
Alex Deucher b556b12e82 drm/radeon/cik: add srbm_select function
Allows us to select instanced registers based on:
- ME (micro engine
- Pipe
- Queue
- VMID

Switch MC setup to use this new function.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:51 -04:00
Christian König 87167bb16d drm/radeon: add UVD support for CIK (v3)
v2: agd5f: fix clock dividers setup for bonaire
v3: agd5f: rebase

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:50 -04:00
Alex Deucher 6e2c3c0ae7 drm/radeon/cik: add pcie_port indirect register accessors
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:48 -04:00
Alex Deucher 2c67912c43 drm/radeon: add get_xclk() callback for CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:48 -04:00
Alex Deucher cc066715e6 drm/radeon: update CIK soft reset
Update to the newer programming model.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:46 -04:00
Alex Deucher 44fa346f7a drm/radeon: add get_gpu_clock_counter() callback for cik
Used for GPU clock counter snapshots.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:45 -04:00
Alex Deucher cd84a27d18 drm/radeon/dce8: add support for display watermark setup
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:37 -04:00
Alex Deucher 7bf94a2c18 drm/radeon/cik: fill in startup/shutdown callbacks (v5)
v2: update to latest driver changes
v3: properly tear down vm on suspend
v4: fix up irq init ordering
v5: remove outdated comment

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2013-06-26 16:11:33 -04:00
Alex Deucher d0e092d969 drm/radeon/cik: add support for doing async VM pt updates (v5)
Async page table updates using the sDMA engine.  sDMA has a
special packet for updating entries for contiguous pages
that reduces overhead.

v2: add support for and use the CP for now.
v3: update for 2 level PTs
v4: rebase, fix DMA packet
v5: switch to using an IB

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:34 -04:00
Alex Deucher 605de6b97e drm/radeon: implement async vm_flush for the sDMA (v6)
Update the page table base address and flush the
VM TLB using the sDMA.

V2: update for 2 level PTs
V3: update vm flush
V4: update SH_MEM* regs
V5: switch back to old style VM TLB invalidate
V6: fix packet formatting

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:33 -04:00
Alex Deucher 21a93e130d drm/radeon/cik: add support for sDMA dma engines (v8)
CIK has new asynchronous DMA engines called sDMA
(system DMA).  Each engine supports 1 ring buffer
for kernel and gfx and 2 userspace queues for compute.

TODO: fill in the compute setup.

v2: update to the latest reset code
v3: remove ib_parse
v4: fix copy_dma()
v5: drop WIP compute sDMA queues
v6: rebase
v7: endian fixes for IB
v8: cleanup for release

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:33 -04:00
Alex Deucher 9d97c99b18 drm/radeon/cik: log and handle VM page fault interrupts
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:32 -04:00
Alex Deucher a59781bbe5 drm/radeon: add support for interrupts on CIK (v5)
Todo:
- handle interrupts for compute queues

v2: add documentation
v3: update to latest reset code
v4: update to latest illegal CP handling
v5: fix missing break in interrupt handler switch statement

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:31 -04:00
Alex Deucher f6796caee6 drm/radeon: Add support for RLC init on CIK (v4)
RLC handles the interrupt controller and other tasks
on the GPU.

v2: add documentation
v3: update programming sequence
v4: additional setup

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:31 -04:00
Alex Deucher f96ab48457 drm/radeon: implement async vm_flush for the CP (v7)
Update the page table base address and flush the
VM TLB using the CP.

v2: update for 2 level PTs
v3: use new packet for invalidate
v4: update SH_MEM* regs when flushing the VM
v5: add pfp sync, go back to old style vm TLB invalidate
v6: fix hdp flush packet count
v7: use old style HDP flush

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:30 -04:00
Alex Deucher fbc832c7f5 drm/radeon: add ring and IB tests for CIK (v3)
v2: add documenation
v3: update the latest ib changes

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:29 -04:00
Alex Deucher 2cae3bc3f3 drm/radeon: add IB and fence dispatch functions for CIK gfx (v7)
For gfx ring only.  Compute is still todo.

v2: add documentation
v3: update to latest reset changes, integrate emit update patch.
v4: fix count on wait_reg_mem for HDP flush
v5: use old hdp flush method for fence
v6: set valid bit for IB
v7: cleanup for release

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:29 -04:00
Alex Deucher 841cf442fd drm/radeon: Add CP init for CIK (v7)
Sets up the GFX ring and loads ucode for GFX and Compute.

Todo:
- handle compute queue setup.

v2: add documentation
v3: integrate with latest reset changes
v4: additional init fixes
v5: scratch reg write back no longer supported on CIK
v6: properly set CP_RB0_BASE_HI
v7: rebase

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:28 -04:00
Alex Deucher bc8273fe97 drm/radeon: add support mc ucode loading on CIK (v2)
Load the GDDR5 ucode and train the links.

v2: update ucode

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:27 -04:00
Alex Deucher 02c8132741 drm/radeon: add initial ucode loading for CIK (v5)
Currently the driver required 6 sets of ucode:
1. pfp - pre-fetch parser, part of the GFX CP
2. me - micro engine, part of the GFX CP
3. ce - constant engine, part of the GFX CP
4. rlc - interrupt, etc. controller
5. mc - memory controller (discrete cards only)
6. mec - compute engines, part of Compute CP

V2: add documentation
V3: update MC ucode
V4: rebase
V5: update mc ucode

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:27 -04:00
Alex Deucher a00024b03d drm/radeon/cik: stop page faults from hanging the system (v2)
Redirect invalid memory accesses to the default page
instead of locking up the memory controller.

v2: rebase on top of 2 level PTs

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:26 -04:00
Alex Deucher 1c49165d0a drm/radeon: add support for MC/VM setup on CIK (v6)
The vm callbacks are the same as the SI ones right now
(same regs and bits). We could share the SI variants, and
I may yet do that, but I figured I would add CIK specific
ones for now in case we need to change anything.

V2: add documentation, minor fixes.
V3: integrate vram offset fixes for APUs
V4: enable 2 level VM PTs
V5: index SH_MEM_* regs properly
V6: add ib_parse()

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:25 -04:00
Alex Deucher 6f2043ce15 drm/radeon: Add support for CIK GPU reset (v2)
v2: split soft reset into compute and gfx.  Still need
to make reset more fine grained, but this should be a
start.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:25 -04:00
Alex Deucher 8cc1a5328b drm/radeon: add gpu init support for CIK (v9)
v2: tiling fixes
v3: more tiling fixes
v4: more tiling fixes
v5: additional register init
v6: rebase
v7: fix gb_addr_config for KV/KB
v8: drop wip KV bits for now, add missing config reg
v9: fix cu count on Bonaire

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:24 -04:00