While the IRQ core doesn't currently support shared threaded interrupts
that's no reason for drivers not to do their bit and report IRQ_NONE when
they don't get an interrupt. This allows the core spurious/wedget interrupt
detection support to do its thing.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
There seem to be lots of regmap-using devices with very similar interrupt
controllers with a small bank of interrupt registers and mask registers
with an interrupt per bit. This won't cover everything but it's a good
start.
Each chip supplies a base for the status registers, a base for the mask
registers, an optional base for writing acknowledgements (which may be the
same as the status registers) and an array of bits within each of these
register banks which indicate the interrupt.
There is an assumption that the bit for each interrupt will be the same
in each of the register bank.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Mark Brown