c28c82e9db
drm/msm: sync generated headers
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We haven't sync'd for a while.. pull in updates to get definitions for
some fields in pkt7 payloads.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31 06:46:16 -07:00
2d75632253
drm/msm: update generated headers
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Resync generated headers to pull in a6xx registers.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-08-10 18:49:18 -04:00
52260ae4c4
drm/msm: update generated headers
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Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16 11:16:07 -04:00
a26ae754b0
drm/msm: update generated headers
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Pull in a5xx registers.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28 15:14:10 -05:00
a2272e48ee
drm/msm: update generated headers
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Pull in additional regs needed for a430, etc.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-03-03 11:55:27 -05:00
e9a2ce1349
drm/msm/hdmi: Update generated headers for HDMI 8996 PHY
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Adds HDMI 8996 PHY offsets. The offsets are divided into 3 parts:
- Core HDMI PHY registers
- HDMI PLL registers (part of QSERDES block)
- HDMI TX lane registers (part of QSERDES block)
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29 09:48:31 -05:00
568be320f7
drm/msm/hdmi: Update generated headers to split PHY/PLL offsets
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- Create separate domains for 8960 PHY and PLL
- Create separate domains for 8x60 PHY
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-02-29 09:48:31 -05:00
8217e97ab9
drm/msm: update generated headers
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Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22 15:39:44 -04:00
2d3584eb87
drm/msm: update generated headers
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Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-08-15 18:27:10 -04:00
af6cb4c1a4
drm/msm: update generated headers
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Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11 13:11:01 -04:00
8a264743b7
drm/msm: update generated headers
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Resync from rnndb database, to pull in register defines for:
* eDP
* HDMI/HDCP
* mdp4/mdp5 YUV support
* mdp5 hw cursor support
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-02-01 15:30:33 -05:00
bc00ae02e4
drm/msm: update generated headers
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Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16 14:22:42 -05:00
f9a1ca5c47
drm/msm: update generated headers
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In particular, pick up the definitions for a handful of LVDS related
registers.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-09-10 11:19:05 -04:00
89301471e6
drm/msm: update generated headers
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Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-08-04 11:55:28 -04:00
facb4f4e7f
drm/msm: resync generated headers
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resync to latest envytools db, add mdp5 registers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-01-09 14:38:59 -05:00
22ba8b6b23
drm/msm: resync generated headers
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resync to latest envytools db, fixes a typo: s/mpd4/mdp4/
Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: David Brown <davidb@codeaurora.org>
2013-11-01 12:39:44 -04:00
0cf6c71d70
drm/msm: add register definitions
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Generated from rnndb files in:
https://github.com/freedreno/envytools
Keep this split out as a separate commit to make it easier to review the
actual driver.
Signed-off-by: Rob Clark <robdclark@gmail.com>
2013-08-24 14:33:01 -04:00
Rob Clark