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2 Commits

Author SHA1 Message Date
Beniamino Galvani 550ab390d7 ARM: meson: DTS: enable L2 cache 
This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
 2014-11-18 16:36:14 +01:00
Beniamino Galvani aeff05a39a ARM: dts: add dtsi for Amlogic Meson8 SoCs 
This adds a dtsi for Amlogic Meson8 SoCs. It differs from the Meson6
dtsi for the number of Cortex-A9 cores (4 vs 2) and for the frequency
of clk81.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
 2014-11-18 16:36:06 +01:00