Commit Graph

11 Commits

Author SHA1 Message Date
Tony Lindgren b357787e74 Several OMAP2+ DSS-related clock fixes for v3.13 from Tomi Valkeinen.
Basic test logs at:
 
    http://www.pwsan.com/omap/testlogs/clock_fixes_v3.13/20131024090906/
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Merge tag 'for-v3.13/clock-fixes-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into xxx-dt

Several OMAP2+ DSS-related clock fixes for v3.13 from Tomi Valkeinen.

Basic test logs at:

   http://www.pwsan.com/omap/testlogs/clock_fixes_v3.13/20131024090906/
2013-11-14 10:38:43 -08:00
Tomi Valkeinen 4ff7e3b65c ARM: OMAP3: fix dpll4_m3_ck and dpll4_m4_ck dividers
dpll4_m3_ck and dpll4_m4_ck have divider bit fields which are 6 bits
wide. However, only values from 1 to 32 are allowed. This means we have
to add a divider tables and list the dividers explicitly.

I believe the same issue is there for other dpll4_mx_ck clocks, but as
I'm not familiar with them, I didn't touch them.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-24 09:07:23 -06:00
Tomi Valkeinen 262c2c9d06 ARM: OMAP3: use CLK_SET_RATE_PARENT for dss clocks
Set CLK_SET_RATE_PARENT flag for dss1_alwon_fck_3430es2,
dss1_alwon_fck_3430es1 and dpll4_m4x2_ck so that the DSS's fclk can be
configured without the need to get the parent's parent of the fclk.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-10-24 09:07:13 -06:00
Pali Rohár d2065e2b5b RX-51: Add support for OMAP3 ROM Random Number Generator
Adding this driver as platform device and only for RX-51 until somebody test if
it working also on other OMAP3 HS devices and until there will be generic ARM
way to deal with SMC calls.

Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
[tony@atomide.com: folded in the clock alias change]
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-10-08 12:02:12 -07:00
Roger Quadros 1919f0f7db ARM: OMAP3: clock data: get rid of unused USB host clock aliases and dummies
We don't need multiple aliases for the OMAP USB host clocks and neither
the dummy clocks so remove them.

CC: Paul Walmsley <paul@pwsan.com>
CC: Rajendra Nayak <rnayak@ti.com>
CC: Benoit Cousson <b-cousson@ti.com>
CC: Mike Turquette <mturquette@linaro.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
[paul@pwsan.com: updated against v3.10-rc4]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-06-09 01:05:34 -06:00
Mark A. Greer 14ae5564eb ARM: OMAP3xxx: hwmod: Convert AES crypto device data to hwmod
Convert the device data for the OMAP3 AES crypto IP
from explicit platform_data to hwmod.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
[paul@pwsan.com: fixed lines causing sparse warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-03-30 15:51:48 -06:00
Mark A. Greer 26f88e6ebf ARM: OMAP3xxx: hwmod: Convert SHAM crypto device data to hwmod
Convert the device data for the OMAP3 SHAM2 (SHA1/MD5) crypto IP
from explicit platform_data to hwmod.

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
[paul@pwsan.com: updated to use per-SoC registration lists for GP-only hwmods;
 fixed lines causing sparse warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-03-30 15:51:12 -06:00
J Keerthy 78e52e026d ARM: OMAP2+: clock data: Remove CK_* flags
The patch removes all the CK_* which were used to identify the family of
processors for which the individual clocks belonged to. Instead now separate
lists are created based on the family of processors.

Boot Tested on: OMAP4430, OMAP4460, Beagle-board, AM33X boards, OMAP2 boards.

Signed-off-by: J Keerthy <j-keerthy@ti.com>
Tested-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Tested-by: Jon Hunter <jon-hunter@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: changed omap_clock_register_links() to omap_clocks_register();
 updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-03-18 09:57:39 -06:00
Laurent Pinchart 7b2e127759 ARM: OMAP3: clock: Back-propagate rate change from cam_mclk to dpll4_m5
The cam_mclk clock is generated through the following clocks chain:

dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk

As dpll4_m5 and dpll4_m5x2 do not driver any clock other than cam_mclk,
back-propagate the cam_clk rate changes up to dpll4_m5.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Sakari Ailus <sakari.ailus@iki.fi>
Tested-by: Sakari Ailus <sakari.ailus@iki.fi>
2013-01-23 00:44:03 +01:00
Jon Hunter cfef4b2723 ARM: OMAP3: clock data: Add missing enable/disable for EMU clock
The ETM/ETB drivers for OMAP3, enable the emu_src_ck clock in order
to access the ETM/ETB hardware. The emu_src_ck should enable the EMU
clock domain so that the ETM/ETB hardware is accessible. However,
currently when enabling the emu_src_ck the EMU clock domain is not
being enabled and so the ETM/ETB drivers are failing. Add enable/disable
clock functions to enable the EMU clock domain when enabling the
emu_src_ck.

Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2013-01-02 12:07:16 -07:00
Rajendra Nayak 99e7938def ARM: OMAP3: clock: Add 3xxx data using common struct clk
The patch is the output from a python script which converts
from the old OMAP clk format to COMMON clk format using a
JSON parser in between which was developed by Paul Walmsley.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: AM3517/05: dropped bogus hsotgusb "ick" and "fck"
 clkdev aliases; added hsotgusb_fck alias; added emac_ick and emac_fck
 aliases; replace omap2_init_clksel_parent() with
 omap2_clksel_find_parent_index(); reflow macros and parent name
 lists; add clkdm_name argument to DEFINE_STRUCT_CLK_HW_OMAP macros]
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-11-12 19:18:49 -07:00