Add initial pinctrl driver to support pin configuration with
pinctrl framework for SM8150
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
[vkoul: modify to use upstream tile support
use upstream code style
order the functions and squash functions]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-4-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Introduce the irq_enable callback which will be same as irq_unmask
except that it will also clear the status bit before unmask.
This will help in clearing any erroneous interrupts that would
have got latched when the interrupt is not in use.
There may be devices like UART which can use the same gpio line
for data rx as well as a wakeup gpio when in suspend. The data that
was flowing on the line may latch the interrupt and when we enable
the interrupt before going to suspend, this would trigger the
unexpected interrupt. This change helps clearing the interrupt
so that these unexpected interrupts gets cleared.
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
Link: https://lore.kernel.org/r/1561472086-23360-1-git-send-email-neeraju@codeaurora.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Clang warns when CONFIG_ACPI is unset:
drivers/pinctrl/qcom/pinctrl-sdm845.c:1320:5: warning: 'CONFIG_ACPI' is
not defined, evaluates to 0 [-Wundef]
#if CONFIG_ACPI
^
1 warning generated.
Use ifdef instead of if to resolve this.
Fixes: a229105d7a ("pinctrl: qcom: sdm845: Provide ACPI support")
Link: https://github.com/ClangBuiltLinux/linux/issues/569
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch provides basic support for booting with ACPI instead
of the currently supported Device Tree. When doing so there are a
couple of differences which we need to taken into consideration.
Firstly, the SDM850 ACPI tables omit information pertaining to the
4 reserved GPIOs on the platform. If Linux attempts to touch/
initialise any of these lines, the firmware will restart the
platform.
Secondly, when booting with ACPI, it is expected that the firmware
will set-up things like; Regulators, Clocks, Pin Functions, etc in
their ideal configuration. Thus, the possible Pin Functions
available to this platform are not advertised when providing the
higher GPIOD/Pinctrl APIs with pin information.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When booting MSM based platforms with Device Tree or some ACPI
implementations, it is possible to provide a list of reserved pins
via the 'gpio-reserved-ranges' and 'gpios' properties respectively.
However some ACPI tables are not populated with this information,
thus it has to come from a knowledgable device driver instead.
Here we provide the MSM common driver with additional support to
parse this informtion and correctly populate the widely used
'valid_mask'.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The ufs_reset pin is expected to be wired to the reset pin of the
primary UFS memory but is pretty much just a general purpose output pinr
Reorder the pins and expose it as gpio 150, so that the UFS driver can
toggle it.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 and
only version 2 as published by the free software foundation this
program is distributed in the hope that it will be useful but
without any warranty without even the implied warranty of
merchantability or fitness for a particular purpose see the gnu
general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 294 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
No core changes.
New drivers:
- NXP (ex Freescale) i.MX 8QM driver.
- NXP (ex Freescale) i.MX 8MM driver.
- AT91 SAM9X60 subdriver.
Improvements:
- Support for external interrups (EINT) on Mediatek virtual GPIOs.
- Make BCM2835 pin config fully generic.
- Lots of Renesas SH-PFC incremental improvements.
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Merge tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is a calm cycle, not much happened this time around: not even
much incremental development. Some three new drivers, that is all.
No core changes.
New drivers:
- NXP (ex Freescale) i.MX 8QM driver.
- NXP (ex Freescale) i.MX 8MM driver.
- AT91 SAM9X60 subdriver.
Improvements:
- Support for external interrups (EINT) on Mediatek virtual GPIOs.
- Make BCM2835 pin config fully generic.
- Lots of Renesas SH-PFC incremental improvements"
* tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (70 commits)
pinctrl: imx: fix scu link errors
dt-bindings: pinctrl: Document the i.MX50 IOMUXC binding
pinctrl: qcom: spmi-gpio: Reorder debug print
pinctrl: nomadik: fix possible object reference leak
pinctrl: stm32: return error upon hwspinlock failure
pinctrl: stm32: fix memory leak issue
pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions
pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions
pinctrl: sh-pfc: Validate fixed-size field widths at build time
pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups
pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group
pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group
pinctrl: sh-pfc: emev2: Add missing pinmux functions
pinctrl: sunxi: Support I/O bias voltage setting on A80
pinctrl: ingenic: Add LCD pins for the JZ4725B SoC
pinctrl: samsung: Remove legacy API for handling external wakeup interrupts mask
pinctrl: bcm2835: Direct GPIO config changes to generic pinctrl
pinctrl: bcm2835: declare pin config as generic
pinctrl: qcom: qcs404: Drop unused UFS_RESET macro
dt-bindings: add documentation for slew rate
...
Core changes:
- The big change this time around is the irqchip handling in
the qualcomm pin controllers, closely coupled with the
gpiochip. This rework, in a classic fall-between-the-chairs
fashion has been sidestepped for too long. The Qualcomm
IRQchips using the SPMI and SSBI transport mechanisms have
been rewritten to use hierarchical irqchip. This creates
the base from which I intend to gradually pull support for
hierarchical irqchips into the gpiolib irqchip helpers to
cut down on duplicate code. We have too many hacks in the
kernel because people have been working around the missing
hierarchical irqchip for years, and once it was there,
noone understood it for a while. We are now slowly adapting
to using it. This is why this pull requests include changes
to MFD, SPMI, IRQchip core and some ARM Device Trees
pertaining to the Qualcomm chip family. Since Qualcomm have
so many chips and such large deployments it is paramount
that this platform gets this right, and now it (hopefully)
does.
- Core support for pull-up and pull-down configuration, also
from the device tree. When a simple GPIO chip support a
"off or on" pull-up or pull-down resistor, we provide a
way to set this up using machine descriptors or device tree.
If more elaborate control of pull up/down (such as
resistance shunt setting) is required, drivers should be
phased over to use pin control. We do not yet provide a
userspace ABI for this pull up-down setting but I suspect
the makers are going to ask for it soon enough. PCA953x
is the first user of this new API.
- The GPIO mockup driver has been revamped after some
discussion improving the IRQ simulator in the process.
The idea is to make it possible to use the mockup for
both testing and virtual prototyping, e.g. when you do
not yet have a GPIO expander to play with but really
want to get something to develop code around before
hardware is available. It's neat. The blackbox testing
usecase is currently making its way into kernelci.
- ACPI GPIO core preserves non direction flags when updating
flags.
- A new device core helper for devm_platform_ioremap_resource()
is funneled through the GPIO tree with Greg's ACK.
New drivers:
- TQ-Systems QTMX86 GPIO controllers (using port-mapped
I/O)
- Gateworks PLD GPIO driver (vaccumed up from OpenWrt)
- AMD G-Series PCH (Platform Controller Hub) GPIO driver.
- Fintek F81804 & F81966 subvariants.
- PCA953x now supports NXP PCAL6416.
Driver improvements:
- IRQ support on the Nintendo Wii (Hollywood) GPIO.
- get_direction() support for the MVEBU driver.
- Set the right output level on SAMA5D2.
- Drop the unused irq trigger setting on the Spreadtrum
driver.
- Wakeup support for PCA953x.
- A slew of cleanups in the various Intel drivers.
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Merge tag 'gpio-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v5.1 cycle:
Core changes:
- The big change this time around is the irqchip handling in the
qualcomm pin controllers, closely coupled with the gpiochip. This
rework, in a classic fall-between-the-chairs fashion has been
sidestepped for too long.
The Qualcomm IRQchips using the SPMI and SSBI transport mechanisms
have been rewritten to use hierarchical irqchip. This creates the
base from which I intend to gradually pull support for hierarchical
irqchips into the gpiolib irqchip helpers to cut down on duplicate
code.
We have too many hacks in the kernel because people have been
working around the missing hierarchical irqchip for years, and once
it was there, noone understood it for a while. We are now slowly
adapting to using it.
This is why this pull requests include changes to MFD, SPMI,
IRQchip core and some ARM Device Trees pertaining to the Qualcomm
chip family. Since Qualcomm have so many chips and such large
deployments it is paramount that this platform gets this right, and
now it (hopefully) does.
- Core support for pull-up and pull-down configuration, also from the
device tree. When a simple GPIO chip supports an "off or on" pull-up
or pull-down resistor, we provide a way to set this up using
machine descriptors or device tree.
If more elaborate control of pull up/down (such as resistance shunt
setting) is required, drivers should be phased over to use pin
control. We do not yet provide a userspace ABI for this pull
up-down setting but I suspect the makers are going to ask for it
soon enough. PCA953x is the first user of this new API.
- The GPIO mockup driver has been revamped after some discussion
improving the IRQ simulator in the process.
The idea is to make it possible to use the mockup for both testing
and virtual prototyping, e.g. when you do not yet have a GPIO
expander to play with but really want to get something to develop
code around before hardware is available. It's neat. The blackbox
testing usecase is currently making its way into kernelci.
- ACPI GPIO core preserves non direction flags when updating flags.
- A new device core helper for devm_platform_ioremap_resource() is
funneled through the GPIO tree with Greg's ACK.
New drivers:
- TQ-Systems QTMX86 GPIO controllers (using port-mapped I/O)
- Gateworks PLD GPIO driver (vaccumed up from OpenWrt)
- AMD G-Series PCH (Platform Controller Hub) GPIO driver.
- Fintek F81804 & F81966 subvariants.
- PCA953x now supports NXP PCAL6416.
Driver improvements:
- IRQ support on the Nintendo Wii (Hollywood) GPIO.
- get_direction() support for the MVEBU driver.
- Set the right output level on SAMA5D2.
- Drop the unused irq trigger setting on the Spreadtrum driver.
- Wakeup support for PCA953x.
- A slew of cleanups in the various Intel drivers"
* tag 'gpio-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (110 commits)
gpio: gpio-omap: fix level interrupt idling
gpio: amd-fch: Set proper output level for direction_output
x86: apuv2: remove unused variable
gpio: pca953x: Use PCA_LATCH_INT
platform/x86: fix PCENGINES_APU2 Kconfig warning
gpio: pca953x: Fix dereference of irq data in shutdown
gpio: amd-fch: Fix type error found by sparse
gpio: amd-fch: Drop const from resource
gpio: mxc: add check to return defer probe if clock tree NOT ready
gpio: ftgpio: Register per-instance irqchip
gpio: ixp4xx: Add DT bindings
x86: pcengines apuv2 gpio/leds/keys platform driver
gpio: AMD G-Series PCH gpio driver
drivers: depend on HAS_IOMEM for devm_platform_ioremap_resource()
gpio: tqmx86: Set proper output level for direction_output
gpio: sprd: Change to use SoC compatible string
gpio: sprd: Use SoC compatible string instead of wildcard string
gpio: of: Handle both enable-gpio{,s}
gpio: of: Restrict enable-gpio quirk to regulator-gpio
gpio: davinci: use devm_platform_ioremap_resource()
...
It's reasonable to expect that people turn to the "gpio" debugfs file to
first and foremost learn about the direction and value of a gpio, and
second to that about it's pinconf. So reorder the value so each line
reads:
gpioN: direction value ...
This also makes it consistent with the TLMM pinctrl driver's output in
the same dump.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
SSBI GPIOs are numbered 1..ngpio, so the boundary check in
pm8xxx_domain_translate() is off by one. This patch corrects that check.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
ssbi-gpio did not have any irqchip support so consumers of this in
device tree would need to call gpio[d]_to_irq() in order to get the
proper IRQ on the underlying PMIC. IRQ chips in device tree should
be usable from the start without the consumer having to make an
additional call to get the proper IRQ on the parent. This patch adds
hierarchical IRQ chip support to the ssbi-gpio code to correct this
issue.
The constant PM8XXX_GPIO_PHYSICAL_OFFSET is introduced to replace the
hardcoded '1' that previously existed in two places in this driver to
improve code readability.
This change was tested on an APQ8060 DragonBoard.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The probing of this driver calls platform_irq_count, which will
setup all of the IRQs that are configured in device tree. In
preparation for converting this driver to be a hierarchical IRQ
chip, hardcode the IRQ count based on the hardware type so that all
the IRQs are not configured immediately and are configured on an
as-needed basis later in the boot process. This change will also
allow for the removal of the interrupts property later in this
patch series once the hierarchical IRQ chip support is in.
This patch also removes the generic qcom,ssbi-gpio OF match since we
don't know the number of pins. All of the existing upstream bindings
already include the more-specific binding.
This change was tested on an APQ8060 DragonBoard.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
GPIOs on the SPMI PMIC are numbered 1..ngpio, so the boundary check in
pmic_gpio_domain_translate() is off by one, correct this.
Fixes: ca69e2d165 ("qcom: spmi-gpio: add support for hierarchical IRQ chip")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SDC controls live in the south tile, not the north one. Correct this
so that we program the right registers.
Cc: stable@vger.kernel.org
Fixes: 22eb8301db ("pinctrl: qcom: Add qcs404 pinctrl driver")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The UFS_RESET macro serves no purpose on QCS404, remove it.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Select IRQ_DOMAIN_HIERARCHY for spmi-gpio in Kconfig since this driver
is now setup as a hierarchical IRQ chip.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
spmi-gpio did not have any irqchip support so consumers of this in
device tree would need to call gpio[d]_to_irq() in order to get the
proper IRQ on the underlying PMIC. IRQ chips in device tree should
be usable from the start without the consumer having to make an
additional call to get the proper IRQ on the parent. This patch adds
hierarchical IRQ chip support to the spmi-gpio code to correct this
issue.
Driver was tested using the volume buttons (via gpio-keys) on the LG
Nexus 5 (hammerhead) phone with the following two configurations.
volume-up {
interrupts-extended = <&pm8941_gpios 2 IRQ_TYPE_EDGE_BOTH>;
...
};
volume-up {
gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>;
...
};
Both configurations now show that spmi-gpio is the IRQ domain and that
the IRQ is setup in a hierarchy.
$ grep volume_up /proc/interrupts
72: 6 0 spmi-gpio 1 Edge volume_up
$ cat /sys/kernel/debug/irq/irqs/72
handler: handle_edge_irq
device: (null)
status: 0x00000403
_IRQ_NOPROBE
istate: 0x00000000
ddepth: 0
wdepth: 0
dstate: 0x02400203
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
IRQD_ACTIVATED
IRQD_IRQ_STARTED
node: 0
affinity: 0-3
effectiv:
domain: :soc:spmi@fc4cf000:pm8941@0:gpios@c000
hwirq: 0x1
chip: spmi-gpio
flags: 0x4
IRQCHIP_MASK_ON_SUSPEND
parent:
domain: :soc:spmi@fc4cf000
hwirq: 0xc100057
chip: pmic_arb
flags: 0x4
IRQCHIP_MASK_ON_SUSPEND
Signed-off-by: Brian Masney <masneyb@onstation.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The probing of this driver calls platform_irq_count, which will
setup all of the IRQs that are configured in device tree. In
preparation for converting this driver to be a hierarchical IRQ
chip, hardcode the IRQ count based on the hardware type so that all
the IRQs are not configured immediately and are configured on an
as-needed basis later in the boot process. This change will also
allow for the removal of the interrupts property later in this
patch series once the hierarchical IRQ chip support is in.
This patch also removes the generic qcom,spmi-gpio OF match since we
don't know the number of pins. All of the existing upstream bindings
already include the more-specific binding.
The pm8941 code was tested on a LG Nexus 5 (hammerhead) phone.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support for qcom,pm8005-gpio, qcom,pm8998-gpio, and
qcom,pmi8998-gpio. These three variants are already in use in some
arm64 dtsi files. Those boards work since the generic binding
qcom,spmi-gpio is also specified.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
No core changes this time.
New drivers:
- NXP (ex Freescale) i.MX 8 QXP SoC driver.
- Mediatek MT6797 SoC driver.
- Mediatek MT7629 SoC driver.
- Actions Semiconductor S700 SoC driver.
- Renesas RZ/A2 SoC driver.
- Allwinner sunxi suniv F1C100 SoC driver.
- Qualcomm PMS405 PMIC driver.
- Microsemi Ocelot Jaguar2 SoC driver.
Improvements:
- Some RT improvements (using raw spinlocks where appropriate).
- A lot of new pin sets on the Renesas PFC pin controllers.
- GPIO hogs now work on the Qualcomm SPMI/SSBI pin controller GPIO
chips, and Xway.
- Major modernization of the Intel pin control drivers.
- STM32 pin control driver will now synchronize usage of pins
with another CPU using a hardware spinlock.
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Merge tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"We have no core changes but lots of incremental development in drivers
all over the place: Renesas, NXP, Mediatek and Actions Semiconductor
keep churning out new SoCs.
I have some subtree maintainers for Renesas and Intel helping out to
keep down the load, it's been working smoothly (Samsung also have a
subtree but it was not used this cycle.)
New drivers:
- NXP (ex Freescale) i.MX 8 QXP SoC driver.
- Mediatek MT6797 SoC driver.
- Mediatek MT7629 SoC driver.
- Actions Semiconductor S700 SoC driver.
- Renesas RZ/A2 SoC driver.
- Allwinner sunxi suniv F1C100 SoC driver.
- Qualcomm PMS405 PMIC driver.
- Microsemi Ocelot Jaguar2 SoC driver.
Improvements:
- Some RT improvements (using raw spinlocks where appropriate).
- A lot of new pin sets on the Renesas PFC pin controllers.
- GPIO hogs now work on the Qualcomm SPMI/SSBI pin controller GPIO
chips, and Xway.
- Major modernization of the Intel pin control drivers.
- STM32 pin control driver will now synchronize usage of pins with
another CPU using a hardware spinlock"
* tag 'pinctrl-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (145 commits)
dt-bindings: arm: fsl-scu: add imx8qm pinctrl support
pinctrl: freescale: Break dependency on SOC_IMX8MQ for i.MX8MQ
pinctrl: imx-scu: Depend on IMX_SCU
pinctrl: ocelot: Add dependency on HAS_IOMEM
pinctrl: ocelot: add MSCC Jaguar2 support
pinctrl: bcm: ns: support updated DT binding as syscon subnode
dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon
MAINTAINERS: merge at91 pinctrl entries
pinctrl: imx8qxp: break the dependency on SOC_IMX8QXP
pinctrl: uniphier: constify uniphier_pinctrl_socdata
pinctrl: mediatek: improve Kconfig dependencies
pinctrl: msm: mark PM functions as __maybe_unused
dt-bindings: pinctrl: sunxi: Add supply properties
pinctrl: meson: meson8b: add the missing GPIO_GROUPs for BOOT and CARD
pinctrl: meson: meson8: add the missing GPIO_GROUPs for BOOT and CARD
pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
pinctrl: meson: meson8: rename the "gpio" function to "gpio_periphs"
pinctrl: meson: meson8b: fix the GPIO function for the GPIOAO pins
pinctrl: meson: meson8: fix the GPIO function for the GPIOAO pins
pinctrl: sh-pfc: Make pinmux_cfg_reg.var_field_width[] variable-length
...
Without CONFIG_PM_SLEEP, we get annoying warnings about unused functions:
drivers/pinctrl/qcom/pinctrl-msm.c:1082:12: error: 'msm_pinctrl_resume' defined but not used [-Werror=unused-function]
static int msm_pinctrl_resume(struct device *dev)
^~~~~~~~~~~~~~~~~~
drivers/pinctrl/qcom/pinctrl-msm.c:1075:12: error: 'msm_pinctrl_suspend' defined but not used [-Werror=unused-function]
static int msm_pinctrl_suspend(struct device *dev)
Mark them as __maybe_unused to shut up the warning and silently drop
the functions without having to add ugly #ifdefs.
Fixes: 977d057ad3 ("pinctrl: msm: Add sleep pinctrl state transitions")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This was missed when tiles support was added in a revison and
causes the driver to fail to load.
Fixes: 9cf0c526bc ("pinctrl: qcom: Add sdm660 pinctrl driver")
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add PM suspend callbacks to the msm core driver that select the
sleep and default pinctrl states. Then wire those callbacks up
in the sdm845 driver, for those boards that may have GPIO hogs
that need to change state during suspend.
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When attempting to setup up a gpio hog, device probing will repeatedly
fail with -EPROBE_DEFERED errors. It is caused by a circular dependency
between the gpio and pinctrl frameworks. If the gpio-ranges property is
present in device tree, then the gpio framework will handle the gpio pin
registration and eliminate the circular dependency.
See Christian Lamparter's commit a86caa9ba5 ("pinctrl: msm: fix
gpio-hog related boot issues") for a detailed commit message that
explains the issue in much more detail. The code comment in this commit
came from Christian's commit.
I did not test this change against any hardware supported by this
particular driver, however I was able to validate this same fix works
for pinctrl-spmi-gpio.c using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When attempting to setup up a gpio hog, device probing would repeatedly
fail with -EPROBE_DEFERED errors. It was caused by a circular dependency
between the gpio and pinctrl frameworks. If the gpio-ranges property is
present in device tree, then the gpio framework will handle the gpio pin
registration and eliminate the circular dependency.
See Christian Lamparter's commit a86caa9ba5 ("pinctrl: msm: fix
gpio-hog related boot issues") for a detailed commit message that
explains the issue in much more detail. The code comment in this commit
came from Christian's commit.
Signed-off-by: Brian Masney <masneyb@onstation.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- A patch series from Hans Verkuil to make it possible to
enable/disable IRQs on a GPIO line at runtime and drive GPIO
lines as output without having to put/get them from scratch.
The irqchip callbacks have been improved so that they can
use only the fastpatch callbacks to enable/disable irqs
like any normal irqchip, especially the gpiod_lock_as_irq()
has been improved to be callable in fastpath context.
A bunch of rework had to be done to achieve this but it is
a big win since I never liked to restrict this to slowpath.
The only call requireing slowpath was try_module_get() and
this is kept at the .request_resources() slowpath callback.
In the GPIO CEC driver this is a big win sine a single
line is used for both outgoing and incoming traffic, and
this needs to use IRQs for incoming traffic while actively
driving the line for outgoing traffic.
- Janusz Krzysztofik improved the GPIO array API to pass a
"cookie" (struct gpio_array) and a bitmap for setting or
getting multiple GPIO lines at once. This improvement
orginated in a specific need to speed up an OMAP1 driver and
has led to a much better API and real performance gains
when the state of the array can be used to bypass a lot
of checks and code when we want things to go really fast.
The previous code would minimize the number of calls
down to the driver callbacks assuming the CPU speed was
orders of magnitude faster than the I/O latency, but this
assumption was wrong on several platforms: what we needed
to do was to profile and improve the speed on the hot
path of the array functions and this change is now
completed.
- Clean out the painful and hard to grasp BNF experiments
from the device tree bindings. Future approaches are looking
into using JSON schema for this purpose. (Rob Herring
is floating a patch series.)
New drivers:
- The RCAR driver now supports r8a774a1 (RZ/G2M).
- Synopsys GPIO via CREGs driver.
Major improvements:
- Modernization of the EP93xx driver to use irqdomain and
other contemporary concepts.
- The ingenic driver has been merged into the Ingenic pin
control driver and removed from the GPIO subsystem.
- Debounce support in the ftgpio010 driver.
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Merge tag 'gpio-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.20 series:
Core changes:
- A patch series from Hans Verkuil to make it possible to
enable/disable IRQs on a GPIO line at runtime and drive GPIO lines
as output without having to put/get them from scratch.
The irqchip callbacks have been improved so that they can use only
the fastpatch callbacks to enable/disable irqs like any normal
irqchip, especially the gpiod_lock_as_irq() has been improved to be
callable in fastpath context.
A bunch of rework had to be done to achieve this but it is a big
win since I never liked to restrict this to slowpath. The only call
requireing slowpath was try_module_get() and this is kept at the
.request_resources() slowpath callback. In the GPIO CEC driver this
is a big win sine a single line is used for both outgoing and
incoming traffic, and this needs to use IRQs for incoming traffic
while actively driving the line for outgoing traffic.
- Janusz Krzysztofik improved the GPIO array API to pass a "cookie"
(struct gpio_array) and a bitmap for setting or getting multiple
GPIO lines at once.
This improvement orginated in a specific need to speed up an OMAP1
driver and has led to a much better API and real performance gains
when the state of the array can be used to bypass a lot of checks
and code when we want things to go really fast.
The previous code would minimize the number of calls down to the
driver callbacks assuming the CPU speed was orders of magnitude
faster than the I/O latency, but this assumption was wrong on
several platforms: what we needed to do was to profile and improve
the speed on the hot path of the array functions and this change is
now completed.
- Clean out the painful and hard to grasp BNF experiments from the
device tree bindings. Future approaches are looking into using JSON
schema for this purpose. (Rob Herring is floating a patch series.)
New drivers:
- The RCAR driver now supports r8a774a1 (RZ/G2M).
- Synopsys GPIO via CREGs driver.
Major improvements:
- Modernization of the EP93xx driver to use irqdomain and other
contemporary concepts.
- The ingenic driver has been merged into the Ingenic pin control
driver and removed from the GPIO subsystem.
- Debounce support in the ftgpio010 driver"
* tag 'gpio-v4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (116 commits)
gpio: Clarify kerneldoc on gpiochip_set_chained_irqchip()
gpio: Remove unused 'irqchip' argument to gpiochip_set_cascaded_irqchip()
gpio: Drop parent irq assignment during cascade setup
mmc: pwrseq_simple: Fix incorrect handling of GPIO bitmap
gpio: fix SNPS_CREG kconfig dependency warning
gpiolib: Initialize gdev field before is used
gpio: fix kernel-doc after devres.c file rename
gpio: fix doc string for devm_gpiochip_add_data() to not talk about irq_chip
gpio: syscon: Fix possible NULL ptr usage
gpiolib: Show correct direction from the beginning
pinctrl: msm: Use init_valid_mask exported function
gpiolib: Add init_valid_mask exported function
GPIO: add single-register GPIO via CREG driver
dt-bindings: Document the Synopsys GPIO via CREG bindings
gpio: mockup: use device properties instead of platform_data
gpio: Slightly more helpful debugfs
gpio: omap: Remove set but not used variable 'dev'
gpio: omap: drop omap_gpio_list
Accept partial 'gpio-line-names' property.
gpio: omap: get rid of the conditional PM runtime calls
...
The current code produces XPU violation if get_direction is called just
after the initialization.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Timur Tabi <timur@kernel.org>
Tested-by: Jeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The 'tiles' array is initialized to a constant pointers to constant
strings, but the declaration is only half as constant:
drivers/pinctrl/qcom/pinctrl-qcs404.c:1660:11: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
drivers/pinctrl/qcom/pinctrl-sdm660.c:1417:11: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
Let's make it more constant.
Fixes: 22eb8301db ("pinctrl: qcom: Add qcs404 pinctrl driver")
Fixes: a46d5e9819 ("pinctrl: qcom: Support dispersed tiles")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This code needs to select function #0, which is the first int in the
array of functions, not the number 0 which may or may not be the
function for "GPIO mode" per the enum mapping. We were getting lucky on
SDM845, where this was tested, because the function 0 matched the enum
value for "GPIO mode". On other platforms, e.g. MSM8996, the gpio enum
value is the last one in the list so this code doesn't work and we see a
warning at boot. Fix it by grabbing the first element out of the array
of functions.
Cc: Doug Anderson <dianders@chromium.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Niklas Cassel <niklas.cassel@linaro.org>
Reported-by: Niklas Cassel <niklas.cassel@linaro.org>
Fixes: 1de7ddb3a1 ("pinctrl: msm: Mux out gpio function with gpio_request()")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Merge tag 'v4.19-rc6' into devel
This is the 4.19-rc6 release
I needed to merge this in because of extensive conflicts in
the MSM and Intel pin control drivers. I know how to resolve
them, so let's do it like this.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add initial pinctrl driver to support pin configuration with
pinctrl framework for qcs404.
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
[bjorn: Reworked tile handling and did some minor rework]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On some new platforms the tiles have been placed too far apart to be
covered in a single ioremap. Turn "regs" into an array of base addresses
and make the pingroup carry the information about which tile the pin
resides in.
For existing platforms we map the first entry regs and the existing
pingroups will all use tile 0, meaning that there's no functional
change.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In preparation for the support for dispersed tiles move all readl and
writel calls to helper functions. This will allow us to isolate the
added complexity of another indirection.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'ret' should be returned while pmic_mpp_write_mode_ctl fails.
Fixes: 0e948042c4 ("pinctrl: qcom: spmi-mpp: Implement support for sink mode")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These drivers are GPIO drivers, and the do not need to use the
legacy header in <linux/gpio.h>, go directly for
<linux/gpio/driver.h> instead.
Replace any use of GPIOF_* with 0/1, these flags are for
consumers, not drivers.
Get rid of a few gpio_to_irq() users that was littering
around the place, use local callbacks or avoid using it at
all.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It looks like we parse the drive strength setting here, but never
actually write it into the hardware to update it. Parse the setting and
then write it at the end of the pinconf setting function so that it
actually sticks in the hardware.
Fixes: 0e948042c4 ("pinctrl: qcom: spmi-mpp: Implement support for sink mode")
Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If you look at "pinconf-groups" in debugfs for ssbi-mpp you'll notice
it looks like nonsense.
The problem is fairly well described in commit 1cf86bc212 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c82895 ("pinctrl: msm: Fix msm_config_group_get() to be
compliant"), but it was pointed out that ssbi-mpp has the same
problem. Let's fix it there too.
NOTE: in case it's helpful to someone reading this, the way to tell
whether to do the -EINVAL or not is to look at the PCONFDUMP for a
given attribute. If the last element (has_arg) is false then you need
to do the -EINVAL trick.
ALSO NOTE: it seems unlikely that the values returned when we try to
get PIN_CONFIG_BIAS_PULL_UP will actually be printed since "has_arg"
is false for that one, but I guess it's still fine to return different
values so I kept doing that. It seems like another driver (ssbi-gpio)
uses a custom attribute (PM8XXX_QCOM_PULL_UP_STRENGTH) for something
similar so maybe a future change should do that here too.
Fixes: cfb24f6ebd ("pinctrl: Qualcomm SPMI PMIC MPP pin controller driver")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If you look at "pinconf-groups" in debugfs for ssbi-gpio you'll notice
it looks like nonsense.
The problem is fairly well described in commit 1cf86bc212 ("pinctrl:
qcom: spmi-gpio: Fix pmic_gpio_config_get() to be compliant") and
commit 05e0c82895 ("pinctrl: msm: Fix msm_config_group_get() to be
compliant"), but it was pointed out that ssbi-gpio has the same
problem. Let's fix it there too.
Fixes: b4c45fe974 ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When requesting a gpio as an interrupt, we should make sure to mux the
pin as the GPIO function and configure it to be an input so that various
functions or output signals don't affect the interrupt state of the pin.
So far, we've relied on pinmux configurations in DT to handle this, but
let's explicitly configure this in the code so that DT implementers
don't have to get this part right.
Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We rely on devices to use pinmuxing configurations in DT to select the
GPIO function (function 0) if they're going to use the gpio in GPIO
mode. Let's simplify things for driver authors by implementing
gpio_request_enable() for this pinctrl driver to mux out the GPIO
function when the gpio is use from gpiolib.
Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The interrupt controller hardware in this pin controller has two status
enable bits. The first "normal" status enable bit enables or disables
the summary interrupt line being raised when a gpio interrupt triggers
and the "raw" status enable bit allows or prevents the hardware from
latching an interrupt into the status register for a gpio interrupt.
Currently we just toggle the "normal" status enable bit in the mask and
unmask ops so that the summary irq interrupt going to the CPU's
interrupt controller doesn't trigger for the masked gpio interrupt.
For a level triggered interrupt, the flow would be as follows: the pin
controller sees the interrupt, latches the status into the status
register, raises the summary irq to the CPU, summary irq handler runs
and calls handle_level_irq(), handle_level_irq() masks and acks the gpio
interrupt, the interrupt handler runs, and finally unmask the interrupt.
When the interrupt handler completes, we expect that the interrupt line
level will go back to the deasserted state so the genirq code can unmask
the interrupt without it triggering again.
If we only mask the interrupt by clearing the "normal" status enable bit
then we'll ack the interrupt but it will continue to show up as pending
in the status register because the raw status bit is enabled, the
hardware hasn't deasserted the line, and thus the asserted state latches
into the status register again. When the hardware deasserts the
interrupt the pin controller still thinks there is a pending unserviced
level interrupt because it latched it earlier. This behavior causes
software to see an extra interrupt for level type interrupts each time
the interrupt is handled.
Let's fix this by clearing the raw status enable bit for level type
interrupts so that the hardware stops latching the status of the
interrupt after we ack it. We don't do this for edge type interrupts
because it seems that toggling the raw status enable bit for edge type
interrupts causes spurious edge interrupts.
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If you do this on an sdm845 board:
grep "" /sys/kernel/debug/pinctrl/*spmi:pmic*/pinconf-groups
...it looks like nonsense. For every pin you see listed:
input bias disabled, input bias high impedance, input bias pull down, input bias pull up, ...
That's because pmic_gpio_config_get() isn't complying with the rules
that pinconf_generic_dump_one() expects. Specifically for boolean
parameters (anything with a "struct pin_config_item" where has_arg is
false) the function expects that the function should return its value
not through the "config" parameter but should return "0" if the value
is set and "-EINVAL" if the value isn't set.
Let's fix this.
From a quick sample of other pinctrl drivers, it appears to be
tradition to also return 1 through the config parameter for these
boolean parameters when they exist. I'm not one to knock tradition,
so I'll follow tradition and return 1 in these cases. While I'm at
it, I'll also continue searching for four leaf clovers, kocking on
wood three times, and trying not to break mirrors.
NOTE: This also fixes an apparent typo for reading
PIN_CONFIG_BIAS_DISABLE where the old driver was accidentally
using "=" instead of "==" and thus was setting some internal
state when you tried to query PIN_CONFIG_BIAS_DISABLE. Oops.
Fixes: eadff30244 ("pinctrl: Qualcomm SPMI PMIC GPIO pin controller driver")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If you do this on an sdm845 board:
cat /sys/kernel/debug/pinctrl/3400000.pinctrl/pinconf-groups
...it looks like nonsense. For every pin you see listed:
input bias bus hold, input bias disabled, input bias pull down, input bias pull up
That's because msm_config_group_get() isn't complying with the rules
that pinconf_generic_dump_one() expects. Specifically for boolean
parameters (anything with a "struct pin_config_item" where has_arg is
false) the function expects that the function should return its value
not through the "config" parameter but should return "0" if the value
is set and "-EINVAL" if the value isn't set.
Let's fix this.
From a quick sample of other pinctrl drivers, it appears to be
tradition to also return 1 through the config parameter for these
boolean parameters when they exist. I'm not one to knock tradition,
so I'll follow tradition and return 1 in these cases. While I'm at
it, I'll also continue searching for four leaf clovers, kocking on
wood three times, and trying not to break mirrors.
Fixes: f365be0925 ("pinctrl: Add Qualcomm TLMM driver")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sven Eckelmann reported an issue with the current IPQ4019 pinctrl.
Setting up any gpio-hog in the device-tree for his device would
"kill the bootup completely":
| [ 0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
| [ 0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe
| [ 1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517
| [ 1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register
| [ 1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip
| [ 1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe
| [ 1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri
This was also verified on a RT-AC58U (IPQ4018) which would
no longer boot, if a gpio-hog was specified. (Tried forcing
the USB LED PIN (GPIO0) to high.).
The problem is that Pinctrl+GPIO registration is currently
peformed in the following order in pinctrl-msm.c:
1. pinctrl_register()
2. gpiochip_add()
3. gpiochip_add_pin_range()
The actual error code -517 == -EPROBE_DEFER is coming from
pinctrl_get_device_gpio_range(), which is called through:
gpiochip_add
of_gpiochip_add
of_gpiochip_scan_gpios
gpiod_hog
gpiochip_request_own_desc
__gpiod_request
chip->request
gpiochip_generic_request
pinctrl_gpio_request
pinctrl_get_device_gpio_range
pinctrl_get_device_gpio_range() is unable to find any valid
pin ranges, since nothing has been added to the pinctrldev_list yet.
so the range can't be found, and the operation fails with -EPROBE_DEFER.
This patch fixes the issue by adding the "gpio-ranges" property to
the pinctrl device node of all upstream Qcom SoC. The pin ranges are
then added by the gpio core.
In order to remain compatible with older, existing DTs (and ACPI)
a check for the "gpio-ranges" property has been added to
msm_gpio_init(). This prevents the driver of adding the same entry
to the pinctrldev_list twice.
Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019]
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
I was debugging some gpio issues and I thought that the output of gpio
debugfs was telling me the high or low level of the gpios with a '1' or
a '0'. We saw a line like this though:
gpio93 : in 4 2mA pull down
and I started to think that there may be a gas leak in the building
because '4' doesn't mean high or low, and other pins said '0' or '1'. It
turns out, '4' is the function selection for the pinmux of the gpio and
not the value on the pin. Reading code helps decipher what debugfs is
actually saying.
Add support to read the input or output pin depending on how the pin is
configured so we can easily see the high or low value of the pin in
debugfs. Now the output looks like
gpio93 : in low func4 2mA pull down
which clearly shows that the pin is an input, low, with function 4 and a
2mA drive strength plus a pull down.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
DebugFS strings about pin pull status for no_keeper SoC are wrong
Fix this by adding a different string array for no_keeper SoC
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM. To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios". This property is an array of
specific GPIOs that are accessible. When an older kernel boots on
newer (restricted) firmware, it will fail to probe.
To implement the sparse GPIO map, we register all of the GPIOs, but
fill in the data only for available GPIOs. This ensures that the driver
cannot accidentally access an unavailable GPIO.
The pinctrl-msm driver also scans the "gpios" property to determine
which pins are available, and ensure that only those can be registered.
Support for QCOM8001 is removed as there is no longer any firmware that
implements it.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Two data structures are declared as static globals but are intended to
be per-TLMM. Move them into the msm_pinctrl structure and initialize
them at runtime.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
New drivers:
- Nintendo Wii GameCube GPIO, known as "Hollywood"
- Raspberry Pi mailbox service GPIO expander
- Spreadtrum main SC9860 SoC and IEC GPIO controllers.
Improvements:
- Implemented .get_multiple() callback for most of the
high-performance industrial GPIO cards for the ISA bus.
- ISA GPIO drivers now select the ISA_BUS_API instead of
depending on it. This is merged with the same pattern
for all the ISA drivers and some other Kconfig cleanups
related to this.
Cleanup:
- Delete the TZ1090 GPIO drivers following the deletion of
this SoC from the ARM tree.
- Move the documentation over to driver-api to conform with
the rest of the kernel documentation build.
- Continue to make the GPIO drivers include only
<linux/gpio/driver.h> and not the too broad <linux/gpio.h>
that we want to get rid of.
- Managed to remove VLA allocation from two drivers pending
more fixes in this area for the next merge window.
- Misc janitorial fixes.
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Merge tag 'gpio-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.17 kernel cycle:
New drivers:
- Nintendo Wii GameCube GPIO, known as "Hollywood"
- Raspberry Pi mailbox service GPIO expander
- Spreadtrum main SC9860 SoC and IEC GPIO controllers.
Improvements:
- Implemented .get_multiple() callback for most of the
high-performance industrial GPIO cards for the ISA bus.
- ISA GPIO drivers now select the ISA_BUS_API instead of depending on
it. This is merged with the same pattern for all the ISA drivers
and some other Kconfig cleanups related to this.
Cleanup:
- Delete the TZ1090 GPIO drivers following the deletion of this SoC
from the ARM tree.
- Move the documentation over to driver-api to conform with the rest
of the kernel documentation build.
- Continue to make the GPIO drivers include only
<linux/gpio/driver.h> and not the too broad <linux/gpio.h> that we
want to get rid of.
- Managed to remove VLA allocation from two drivers pending more
fixes in this area for the next merge window.
- Misc janitorial fixes"
* tag 'gpio-v4.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (77 commits)
gpio: Add Spreadtrum PMIC EIC driver support
gpio: Add Spreadtrum EIC driver support
dt-bindings: gpio: Add Spreadtrum EIC controller documentation
gpio: ath79: Fix potential NULL dereference in ath79_gpio_probe()
pinctrl: qcom: Don't allow protected pins to be requested
gpiolib: Support 'gpio-reserved-ranges' property
gpiolib: Change bitmap allocation to kmalloc_array
gpiolib: Extract mask allocation into subroutine
dt-bindings: gpio: Add a gpio-reserved-ranges property
gpio: mockup: fix a potential crash when creating debugfs entries
gpio: pca953x: add compatibility for pcal6524 and pcal9555a
gpio: dwapb: Add support for a bus clock
gpio: Remove VLA from xra1403 driver
gpio: Remove VLA from MAX3191X driver
gpio: ws16c48: Implement get_multiple callback
gpio: gpio-mm: Implement get_multiple callback
gpio: 104-idi-48: Implement get_multiple callback
gpio: 104-dio-48e: Implement get_multiple callback
gpio: pcie-idio-24: Implement get_multiple/set_multiple callbacks
gpio: pci-idio-16: Implement get_multiple callback
...
Some qcom platforms make some GPIOs or pins unavailable for use
by non-secure operating systems, and thus reading or writing the
registers for those pins will cause access control issues and
reset the device. With a DT/ACPI property to describe the set of
pins that are available for use, parse the available pins and set
the irq valid bits for gpiolib to know what to consider 'valid'.
This should avoid any issues with gpiolib. Furthermore, implement
the pinmux_ops::request function so that pinmux can also make
sure to not use pins that are unavailable.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Tested-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
platform_driver does not need to set the owner field, as this will
be populated by the driver core.
Generated by scripts/coccinelle/api/platform_no_drv_owner.cocci.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The base of the TLMM gpiochip should not be statically defined as 0, fix
this to not artificially restrict the existence of multiple pinctrl-msm
devices.
Fixes: f365be0925 ("pinctrl: Add Qualcomm TLMM driver")
Reported-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds the pinctrl definitions for the TLMM of SDM845.
Signed-off-by: Kyle Yan <kyan@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
kernel cycle:
Core:
- The pin control Kconfig entry PINCTRL is now turned into
a menuconfig option. This obviously has the implication of
making the subsystem menu visible in menuconfig. This is
happening because of two things:
- Intel have started to deploy and depend on pin controllers
in a way that is affecting users directly. This happens
on the highly integrated laptop chipsets named after
geographical places: baytrail, broxton, cannonlake,
cedarfork, cherryview, denverton, geminilake, lewisburg,
merrifield, sunrisepoint... It started a while back and
now it is ever more evident that this is crucial
infrastructure for x86 laptops and not an embedded
obscurity anymore. Users need to be aware.
- Pin control expanders on I2C and SPI that are
arch-agnostic. Currently Semtech SX150X and Microchip
MCP28x08 but more are expected. Users will have to be
able to configure these in directly for their set-up.
- Just go and select GPIOLIB now that we made sure that
GPIOLIB is a very vanilla subsystem. Do not depend on
it, if we need it, select it.
- Exposing the pin control subsystem in menuconfig uncovered
a bunch of obscure bugs that are now hopefully fixed,
all more or less pertaining to Blackfin.
- Unified namespace for cross-calls between pin control and
GPIO.
- New support for clock skew/delay generic DT bindings
and generic pin config options for this.
- Minor documentation improvements.
Various:
- The Renesas SH-PFC pin controller has evolved a lot. It seems
Renesas are churning out new SoCs by the minute.
- A bunch of non-critical fixes for the Rockchip driver.
- Improve the use of library functions instead of open coding.
- Support the MCP28018 variant in the MCP28x08 driver.
- Static constifying.
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Merge tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.15 kernel cycle:
Core:
- The pin control Kconfig entry PINCTRL is now turned into a
menuconfig option. This obviously has the implication of making the
subsystem menu visible in menuconfig. This is happening because of
two things:
(a) Intel have started to deploy and depend on pin controllers in
a way that is affecting users directly. This happens on the
highly integrated laptop chipsets named after geographical
places: baytrail, broxton, cannonlake, cedarfork, cherryview,
denverton, geminilake, lewisburg, merrifield, sunrisepoint...
It started a while back and now it is ever more evident that
this is crucial infrastructure for x86 laptops and not an
embedded obscurity anymore. Users need to be aware.
(b) Pin control expanders on I2C and SPI that are arch-agnostic.
Currently Semtech SX150X and Microchip MCP28x08 but more are
expected. Users will have to be able to configure these in
directly for their set-up.
- Just go and select GPIOLIB now that we made sure that GPIOLIB is a
very vanilla subsystem. Do not depend on it, if we need it, select
it.
- Exposing the pin control subsystem in menuconfig uncovered a bunch
of obscure bugs that are now hopefully fixed, all more or less
pertaining to Blackfin.
- Unified namespace for cross-calls between pin control and GPIO.
- New support for clock skew/delay generic DT bindings and generic
pin config options for this.
- Minor documentation improvements.
Various:
- The Renesas SH-PFC pin controller has evolved a lot. It seems
Renesas are churning out new SoCs by the minute.
- A bunch of non-critical fixes for the Rockchip driver.
- Improve the use of library functions instead of open coding.
- Support the MCP28018 variant in the MCP28x08 driver.
- Static constifying"
* tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (91 commits)
pinctrl: gemini: Fix missing pad descriptions
pinctrl: Add some depends on HAS_IOMEM
pinctrl: samsung/s3c24xx: add CONFIG_OF dependency
pinctrl: gemini: Fix GMAC groups
pinctrl: qcom: spmi-gpio: Add pmi8994 gpio support
pinctrl: ti-iodelay: remove redundant unused variable dev
pinctrl: max77620: Use common error handling code in max77620_pinconf_set()
pinctrl: gemini: Implement clock skew/delay config
pinctrl: gemini: Use generic DT parser
pinctrl: Add skew-delay pin config and bindings
pinctrl: armada-37xx: Add edge both type gpio irq support
pinctrl: uniphier: remove eMMC hardware reset pin-mux
pinctrl: rockchip: Add iomux-route switching support for rk3288
pinctrl: intel: Add Intel Cedar Fork PCH pin controller support
pinctrl: intel: Make offset to interrupt status register configurable
pinctrl: sunxi: Enforce the strict mode by default
pinctrl: sunxi: Disable strict mode for old pinctrl drivers
pinctrl: sunxi: Introduce the strict flag
pinctrl: sh-pfc: Save/restore registers for PSCI system suspend
pinctrl: sh-pfc: r8a7796: Use generic IOCTRL register description
...
CORE:
- Fix the semantics of raw GPIO to actually be raw. No
inversion semantics as before, but also no open draining,
and allow the raw operations to affect lines used for
interrupts as the caller supposedly knows what they are
doing if they are getting the big hammer.
- Rewrote the __inner_function() notation calls to names that
make more sense. I just find this kind of code disturbing.
- Drop the .irq_base() field from the gpiochip since now all
IRQs are mapped dynamically. This is nice.
- Support for .get_multiple() in the core driver API. This
allows us to read several GPIO lines with a single
register read. This has high value for some usecases: it
can be used to create oscilloscopes and signal analyzers
and other things that rely on reading several lines at
exactly the same instant. Also a generally nice
optimization. This uses the new assign_bit() macro from
the bitops lib that was ACKed by Andrew Morton and
is implemented for two drivers, one of them being the
generic MMIO driver so everyone using that will be able
to benefit from this.
- Do not allow requests of Open Drain and Open Source
setting of a GPIO line simultaneously. If the hardware
actually supports enabling both at the same time the
electrical result would be disastrous.
- A new interrupt chip core helper. This will be helpful
to deal with "banked" GPIOs, which means GPIO controllers
with several logical blocks of GPIO inside them. This
is several gpiochips per device in the device model, in
contrast to the case when there is a 1-to-1 relationship
between a device and a gpiochip.
NEW DRIVERS:
- Maxim MAX3191x industrial serializer, a very interesting
piece of professional I/O hardware.
- Uniphier GPIO driver. This is the GPIO block from the
recent Socionext (ex Fujitsu and Panasonic) platform.
- Tegra 186 driver. This is based on the new banked GPIO
infrastructure.
OTHER IMPROVEMENTS:
- Some documentation improvements.
- Wakeup support for the DesignWare DWAPB GPIO controller.
- Reset line support on the DesignWare DWAPB GPIO controller.
- Several non-critical bug fixes and improvements for the
Broadcom BRCMSTB driver.
- Misc non-critical bug fixes like exotic errorpaths, removal
of dead code etc.
- Explicit comments on fall-through switch() statements.
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-----END PGP SIGNATURE-----
Merge tag 'gpio-v4.15-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.15 kernel cycle:
Core:
- Fix the semantics of raw GPIO to actually be raw. No inversion
semantics as before, but also no open draining, and allow the raw
operations to affect lines used for interrupts as the caller
supposedly knows what they are doing if they are getting the big
hammer.
- Rewrote the __inner_function() notation calls to names that make
more sense. I just find this kind of code disturbing.
- Drop the .irq_base() field from the gpiochip since now all IRQs are
mapped dynamically. This is nice.
- Support for .get_multiple() in the core driver API. This allows us
to read several GPIO lines with a single register read. This has
high value for some usecases: it can be used to create
oscilloscopes and signal analyzers and other things that rely on
reading several lines at exactly the same instant. Also a generally
nice optimization. This uses the new assign_bit() macro from the
bitops lib that was ACKed by Andrew Morton and is implemented for
two drivers, one of them being the generic MMIO driver so everyone
using that will be able to benefit from this.
- Do not allow requests of Open Drain and Open Source setting of a
GPIO line simultaneously. If the hardware actually supports
enabling both at the same time the electrical result would be
disastrous.
- A new interrupt chip core helper. This will be helpful to deal with
"banked" GPIOs, which means GPIO controllers with several logical
blocks of GPIO inside them. This is several gpiochips per device in
the device model, in contrast to the case when there is a 1-to-1
relationship between a device and a gpiochip.
New drivers:
- Maxim MAX3191x industrial serializer, a very interesting piece of
professional I/O hardware.
- Uniphier GPIO driver. This is the GPIO block from the recent
Socionext (ex Fujitsu and Panasonic) platform.
- Tegra 186 driver. This is based on the new banked GPIO
infrastructure.
Other improvements:
- Some documentation improvements.
- Wakeup support for the DesignWare DWAPB GPIO controller.
- Reset line support on the DesignWare DWAPB GPIO controller.
- Several non-critical bug fixes and improvements for the Broadcom
BRCMSTB driver.
- Misc non-critical bug fixes like exotic errorpaths, removal of dead
code etc.
- Explicit comments on fall-through switch() statements"
* tag 'gpio-v4.15-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (65 commits)
gpio: tegra186: Remove tegra186_gpio_lock_class
gpio: rcar: Add r8a77995 (R-Car D3) support
pinctrl: bcm2835: Fix some merge fallout
gpio: Fix undefined lock_dep_class
gpio: Automatically add lockdep keys
gpio: Introduce struct gpio_irq_chip.first
gpio: Disambiguate struct gpio_irq_chip.nested
gpio: Add Tegra186 support
gpio: Export gpiochip_irq_{map,unmap}()
gpio: Implement tighter IRQ chip integration
gpio: Move lock_key into struct gpio_irq_chip
gpio: Move irq_valid_mask into struct gpio_irq_chip
gpio: Move irq_nested into struct gpio_irq_chip
gpio: Move irq_chained_parent to struct gpio_irq_chip
gpio: Move irq_default_type to struct gpio_irq_chip
gpio: Move irq_handler to struct gpio_irq_chip
gpio: Move irqdomain into struct gpio_irq_chip
gpio: Move irqchip into struct gpio_irq_chip
gpio: Introduce struct gpio_irq_chip
pinctrl: armada-37xx: remove unused variable
...
In order to consolidate the multiple ways to associate an IRQ chip with
a GPIO chip, move more fields into the new struct gpio_irq_chip.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Update the binding and driver for pmi8994-gpios
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is
configured. Update is_enabled flag in config_set() so that it can
reflect GPIO status correctly. Also modify EN_CTL register based on
is_enabled flag in config_set() to configure the GPIO properly.
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Power source selection in DIG_VIN_CTL is indexed from 0, in the range
check it shouldn't be equal to the total number of power sources.
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add property "qcom,dtest-buffer" to specify which dtest rail to feed
when the pin is configured as a digital input.
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add support
for LV and MV subtypes.
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This structure is only used to copy into another structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
15136 5112 0 20248 4f18 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.o
after:
bss dec hex filename
14849 5024 0 19873 4da1 drivers/pinctrl/qcom/pinctrl-ssbi-mpp.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This structure is only used to copy into other structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
13129 2808 192 16129 3f01 drivers/pinctrl/qcom/pinctrl-msm.o
after:
text data bss dec hex filename
12839 2720 192 15751 3d87 drivers/pinctrl/qcom/pinctrl-msm.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This structure is only used to copy into other structure, so declare
it as const.
This issue was detected using Coccinelle and the following semantic patch:
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct gpio_chip i@p = { ... };
@ok@
identifier r.i;
expression e;
position p;
@@
e = i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct gpio_chip e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct gpio_chip i = { ... };
In the following log you can see a significant difference in the code size
and data segment, hence in the dec segment. This log is the output
of the size command, before and after the code change:
before:
text data bss dec hex filename
17061 6992 0 24053 5df5 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o
after:
text data bss dec hex filename
16777 6904 0 23681 5c81 drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
GPIO_PULL bits configurations in TLMM_GPIO_CFG register
differs for IPQ40xx from rest of the other qcom SoCs.
As it does not support the keeper state and therefore can't
support bias-bus-hold property.
This patch adds a pull_no_keeper setting which configures the
msm_gpio_pull bits for ipq40xx. This is required to fix the
proper configurations of gpio-pull bits for nand pins mux.
IPQ40xx SoC:
2'b10: Internal pull up enable.
2'b11: Unsupport
For other SoC's:
2'b10: Keeper
2'b11: Pull-Up
Note: Due to pull_no_keeper length, all kerneldoc entries
in the msm_pinctrl_soc_data struct had to be realigned.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds multiple pinctrl functions and mappings
for SDIO, NAND, I2S, WIFI, PCIE, LEDs, etc... that have
been missing from the current minimal version.
This patch has been updated from the original version
that was posted by Ram Chandra Jangir on the LEDE-DEV ML:
<https://patchwork.ozlabs.org/patch/752962/>. A short
summary of the changes are documented in the device-tree
patch of this series:
"dt-bindings: pinctrl: add most other IPQ4019 pin functions and groups"
Cc: John Crispin <john@phrozen.org>
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- Add bi-directional and output-enable pin configurations to
the generic bindings and generic pin controlling core.
New drivers or subdrivers:
- Armada 37xx SoC pin controller and GPIO support.
- Axis ARTPEC-6 SoC pin controller support.
- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.
- Rockchip RK3328 support.
- Renesas R-Car H3 ES2.0 support.
- STM32F469 support in the STM32 driver.
- Aspeed G4 and G5 pin controller support.
Improvements:
- A whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.
- Switch meson driver to get the GPIO ranges from the device
tree.
- Input schmitt trigger support on the Rockchip driver.
- Enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.
- Name the Qualcomm QDF2xxx GPIO lines.
- Support GMMR GPIO regions on the Intel Cherryview. This
fixes a serialization problem on these platforms.
- Pad retention support for the Samsung Exynos 5433.
- Handle suspend-to-ram in the AT91-pio4 driver.
- Pin configuration support in the Aspeed driver.
Cleanups:
- The final name of Rockchip RK1108 was RV1108 so rename the
driver and variables to stay consistent.
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Merge tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.12 cycle.
The extra week before the merge window actually resulted in some of
the type of fixes that usually arrive after the merge window already
starting to trickle in from eager developers using -next, I'm
impressed.
I have recruited a Samsung subsubsystem maintainer (Krzysztof) to deal
with the onset of Samsung patches. It works great.
Apart from that it is a boring round, just incremental updates and
fixes all over the place, no serious core changes or anything exciting
like that. The most pleasing to see is Julia Cartwrights work to audit
the irqchip-providing drivers for realtime locking compliance. It's
one of those "I should really get around to looking into that" things
that have been on my TODO list since forever.
Summary:
Core changes:
- add bi-directional and output-enable pin configurations to the
generic bindings and generic pin controlling core.
New drivers or subdrivers:
- Armada 37xx SoC pin controller and GPIO support.
- Axis ARTPEC-6 SoC pin controller support.
- AllWinner A64 R_PIO controller support, and opening up the
AllWinner sunxi driver for ARM64 use.
- Rockchip RK3328 support.
- Renesas R-Car H3 ES2.0 support.
- STM32F469 support in the STM32 driver.
- Aspeed G4 and G5 pin controller support.
Improvements:
- a whole slew of realtime improvements to drivers implementing
irqchips: BCM, AMD, SiRF, sunxi, rockchip.
- switch meson driver to get the GPIO ranges from the device tree.
- input schmitt trigger support on the Rockchip driver.
- enable the sunxi (AllWinner) driver to also be used on ARM64
silicon.
- name the Qualcomm QDF2xxx GPIO lines.
- support GMMR GPIO regions on the Intel Cherryview. This fixes a
serialization problem on these platforms.
- pad retention support for the Samsung Exynos 5433.
- handle suspend-to-ram in the AT91-pio4 driver.
- pin configuration support in the Aspeed driver.
Cleanups:
- the final name of Rockchip RK1108 was RV1108 so rename the driver
and variables to stay consistent"
* tag 'pinctrl-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
pinctrl: mediatek: Add missing pinctrl bindings for mt7623
pinctrl: artpec6: Fix return value check in artpec6_pmx_probe()
pinctrl: artpec6: Remove .owner field for driver
pinctrl: tegra: xusb: Silence sparse warnings
ARM: at91/at91-pinctrl documentation: fix spelling mistake: "contoller" -> "controller"
pinctrl: make artpec6 explicitly non-modular
pinctrl: aspeed: g5: Add pinconf support
pinctrl: aspeed: g4: Add pinconf support
pinctrl: aspeed: Add core pinconf support
pinctrl: aspeed: Document pinconf in devicetree bindings
pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrl
pinctrl: stm32: Add STM32F469 MCU support
Documentation: dt: Remove ngpios from stm32-pinctrl binding
pinctrl: stm32: replace device_initcall() with arch_initcall()
pinctrl: stm32: add possibility to use gpio-ranges to declare bank range
pinctrl: armada-37xx: Add gpio support
pinctrl: armada-37xx: Add pin controller support for Armada 37xx
pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllers
pinctrl: core: Make pinctrl_init_controller() static
pinctrl: generic: Add bi-directional and output-enable
...
This patch adds the missing PINGROUP for GPIO70-99.
This fixes a crash that happens in pinctrl-msm, if any
of the GPIO70-99 are accessed.
Fixes: 5303f7827f ("pinctrl: qcom: ipq4019: set ngpios to correct value")
Signed-off-by: Christian Lamparter <chunkeey@googlemail.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Clearing the status bit on irq_unmask will discard any pending interrupt
that did arrive after the irq_ack, i.e. while the IRQ handler function
was executing.
Fixes: f365be0925 ("pinctrl: Add Qualcomm TLMM driver")
Cc: stable@vger.kernel.org
Cc: Stephen Boyd <sboyd@codeaurora.org>
Reported-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The sysfs and debugfs entries for pin control drivers work better when
the individual pins are given real names, even if they are all just
"gpio0", "gpio1", etc.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The get_direction callback function allows gpiolib to know the current
direction (input vs output) for a given GPIO.
This is particularly useful on ACPI systems, where the GPIOs are
configured only by firmware (typically UEFI), so the only way to
know the initial values to query the hardware directly. Without
this function, gpiolib thinks that all GPIOs are configured for
input.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The MSM pinctrl driver currently implements an irq_chip for handling
GPIO interrupts; due to how irq_chip handling is done, it's necessary
for the irq_chip methods to be invoked from hardirq context, even on a
a real-time kernel. Because the spinlock_t type becomes a "sleeping"
spinlock w/ RT kernels, it is not suitable to be used with irq_chips.
A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw
spinlock.
On real-time kernels, this fixes an OOPs which looks like the following,
as reported by Brian Wrenn:
kernel BUG at kernel/locking/rtmutex.c:1014!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
Modules linked in: spidev_irq(O) smsc75xx wcn36xx [last unloaded: spidev]
CPU: 0 PID: 1163 Comm: irq/144-mmc0 Tainted: G W O 4.4.9-linaro-lt-qcom #1
PC is at rt_spin_lock_slowlock+0x80/0x2d8
LR is at rt_spin_lock_slowlock+0x68/0x2d8
[..]
Call trace:
rt_spin_lock_slowlock
rt_spin_lock
msm_gpio_irq_ack
handle_edge_irq
generic_handle_irq
msm_gpio_irq_handler
generic_handle_irq
__handle_domain_irq
gic_handle_irq
Reported-by: Brian Wrenn <dcbrianw@gmail.com>
Tested-by: Brian Wrenn <dcbrianw@gmail.com>
Signed-off-by: Julia Cartwright <julia@ni.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These four pins are for SDC4, not SDC1. They are grouped for
SDC4 later in the file so this must be a typo.
Reviewed-by: Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Initial pinctrl driver for QCOM msm8994 platforms.
In order to continue the initial board support for QCOM msm8994/msm8992
presented in patches from Jeremy McNicoll <jeremymc@redhat.com>, let's put
a proper pinctrl driver in place.
Currently, the DT for these platforms uses the msm8x74 pinctrl driver to
enable basic UART. Beyond the first few pins the rest are different enough
to justify it's own driver.
Note: This driver is also used by QCOM's msm8992 platform as it's TLM block
is the same.
- Initial formatting and style was taken from the msm8x74 pinctrl driver
added by Björn Andersson <bjorn.andersson@linaro.org>
- Data was then adjusted per QCOM MSM8994v2 documentation for Top Level
Multiplexing
- Bindings documentation was based on qcom,msm8996-pinctrl.txt by
Joonwoo Park <joonwoop@codeaurora.org> and then modified for msm8994
content
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Tested-by: Jeremy McNicoll <jeremymc@redhat.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The following commit introduced a regression by not properly masking the
calculated value.
Fixes: 47a01ee9a6 ("pinctrl: qcom: Clear all function selection bits")
Signed-off-by: John Crispin <john@phrozen.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The drivers don't really need to know which PMIC they're for, so
make a generic binding for them. This alleviates us from updating
the drivers every time a new PMIC comes out. It's still
recommended that we update the binding with new PMIC models and
always specify the specific model for the MPPs and gpios before
the generic compatible string in devicetree, but this at least
cuts down on adding more and more compatible strings to the
drivers until we actually need them.
Cc: <devicetree@vger.kernel.org>
Acked-by: "Ivan T. Ivanov" <iivanov.xz@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
After some digging around I found documentation (!) of the APQ8060
EBI2 pin groups. It turns out I first need to split the group in
two: ebi2cs and ebi2 proper. The chip select pins are kind of
orthogonal to the other EBI2 pins since CS1B and CS2B can be muxed
over address bits 7 and 6 (don't know why, but they can). This
is good to fix up before we add users.
Also found what the "holes" in the assignment all the way up to
gpio158 was actually for.
All mux documentation comes from "Snapdragon(TM) S3 APQ8060-based
DragonBoard(TM) GPIO User Guide Rev. E August 10, 2012", published
by Bsquare Corporation.
As the documentation seems a bit hard to come by I put some comments
in the group definitions so that it is clear to all readers what
is going on here and what the lines are used for.
Cc: Björn Andersson <bjorn.andersson@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support to mux in the second external bus interface as
follows:
- CS1 and CS2 on GPIO39 and GPIO40 as func 2
- ADDR_7 thru ADDR_0 on GPIO123 thru GPIO130 as func 1
- CS4, CS3 and CS0 on GPIO132, GPIO133, GPIO134 as func 1
- DATA_15 thru DATA_0 on GPIO135 thru GPIO150 as func 1
- OE on GPIO151 as func 1
- ADV on GPIO153 as func 1
- WE on GPIO157 as func 1
This external bus is used on the APQ8060 Dragonboard to connect
an external SMSC9211 ethernet adapter, but there are many other
usecases for the EBI2.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The msm8974 pinctrl variant has a couple USB HSIC "glue"
registers that let us mux between the pinctrl register settings
or the HSIC core settings for the HSIC pins (gpio 144 and gpio
145). Support this method of operation by adding hsic_data and
hsic_strobe pins that can select between hsic_ctl and gpio
functions. This allows us to toggle the hsic pin configuration
over to the HSIC core at runtime.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The function selection bitfield is not always 3 bits wide.
Sometimes it is 4 bits wide. Let's use the npins struct member to
determine how many bits wide the function selection bitfield is
so we clear the correct amount of bits in the register while
remuxing the pins.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In order to support the Qualcomm MDM9615 SoC, add support for the TLMM
using the Qualcomm pinctrl generic driver.
Note: the pinctrl is partial, need Documentation to complete all the groups.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The PM8058 is found in connection to the APQ8060 on the APQ8060
Dragonboard. Works the same as all others, just add the compatible
string for this variant.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Core changes:
- Add the devm_pinctrl_register() API and switch all applicable drivers
to use it, saving lots of lines of code all over the place.
New drivers:
- New driver for the Broadcom NS2 SoC.
- New subdriver for the PXA25x SoCs.
- New subdriver for the AMLogic Meson GXBB SoC.
Driver improvements:
- The Intel Baytrail driver now properly supports pin control.
- The Nomadik, Rockchip, Broadcom BCM2835 supports the .get_direction() callback in
the GPIO portions.
- Continued development and stabilization of several SH-PFC
SoC subdrivers: r8a7795, r8a7790, r8a7794 etc.
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Merge tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This kernel cycle was quite calm when it comes to pin control and
there is really just one major change, and that is the introduction of
devm_pinctrl_register() managed resources.
Apart from that linear development, details below.
Core changes:
- Add the devm_pinctrl_register() API and switch all applicable
drivers to use it, saving lots of lines of code all over the place.
New drivers:
- driver for the Broadcom NS2 SoC
- subdriver for the PXA25x SoCs
- subdriver for the AMLogic Meson GXBB SoC
Driver improvements:
- the Intel Baytrail driver now properly supports pin control
- Nomadik, Rockchip, Broadcom BCM2835 support the .get_direction()
callback in the GPIO portions
- continued development and stabilization of several SH-PFC SoC
subdrivers: r8a7795, r8a7790, r8a7794 etc"
* tag 'pinctrl-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (85 commits)
Revert "pinctrl: tegra: avoid parked_reg and parked_bank"
pinctrl: meson: Fix eth_tx_en bit index
pinctrl: tegra: avoid parked_reg and parked_bank
pinctrl: tegra: Correctly check the supported configuration
pinctrl: amlogic: Add support for Amlogic Meson GXBB SoC
pinctrl: rockchip: fix pull setting error for rk3399
pinctrl: stm32: Implement .pin_config_dbg_show()
pinctrl: nomadik: hide nmk_gpio_get_mode when unused
pinctrl: ns2: rename pinctrl_utils_dt_free_map
pinctrl: at91: Merge clk_prepare and clk_enable into clk_prepare_enable
pinctrl: at91: Make at91_gpio_template const
pinctrl: baytrail: fix some error handling in debugfs
pinctrl: ns2: add pinmux driver support for Broadcom NS2 SoC
pinctrl: sirf/atlas7: trivial fix of spelling mistake on flagged
pinctrl: sh-pfc: Kill unused variable in sh_pfc_remove()
pinctrl: nomadik: implement .get_direction()
pinctrl: nomadik: use BIT() with offsets consequently
pinctrl: exynos5440: Use off-stack memory for pinctrl_gpio_range
pinctrl: zynq: Use devm_pinctrl_register() for pinctrl registration
pinctrl: u300: Use devm_pinctrl_register() for pinctrl registration
...
Use devm_pinctrl_register() for pin control registration and clean
the error path.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use devm_pinctrl_register() for pin control registration and clean
the error path.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use devm_pinctrl_register() for pin control registration and clean
the error path.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: "Björn Andersson" <bjorn.andersson@sonymobile.com>
Cc: "Ivan T. Ivanov" <ivan.ivanov@linaro.org>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Prasad Sodagudi