Commit Graph

23 Commits

Author SHA1 Message Date
Gabor Juhos dfc3a7b66c ath9k: fix few register offsets for AR9330
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-06-22 16:09:56 -04:00
Gabor Juhos 0c453732a7 ath9k: set NF limits for AR9330
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-06-22 16:09:54 -04:00
Sujith Manoharan 5b68138e56 ath9k: Drag the driver to the year 2011
The Times They Are a-Changin'.

Signed-off-by: Sujith Manoharan <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-05-19 13:54:05 -04:00
Mohammed Shafi Shajakhan c6ba9feb4f ath9k_hw: define registers/macros to support Antenna diversity
define few registers and macros to configure/enable Antenna diversity
parameters in AR9485

Cc: Gabriel Tseng <Gabriel.Tseng@Atheros.com>
Cc: Senthilkumar Balasubramanian <Senthilkumar.Balasubramanian@Atheros.com>
Signed-off-by: Mohammed Shafi Shajakhan <mshajakhan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-05-16 14:10:44 -04:00
Rajkumar Manoharan 3782c69d6e ath9k_hw: Fix Tx IQ Calibration hang issue in AR9003 chips
On AR9003 chips, doing three IQ calibrations will possibly cause chip
in stuck state. In noisy environment, chip could receive
a packet during the middle of three calibrations and it causes
the conflict of HW access and the eventual failure. It also
causes IQ calibration outliers which results in poor Tx EVM.

The IQ Cal procedure is after resetting the chip, run IQ cal 3 times
per each cal cycle and find the two closest readings and average of two.
The advantage of running Tx IQ cal more than once is that we can compare
calibration results for the same gain setting over multiple iterations.
Most of the cases the IQ failures were observed after first pass.

For the AR9485 and later chips, Tx IQ Calibration is performed along
with AGC cal. But for pre-AR9485 chips, Tx IQ cal HW has to be separated
from the rest of calibration HW to avoid chip hang. After all
calibrations are done in HW, we can start SW post-processing.
By doing this way, we minimize the SW difference among all chips.

The order of calibration (run IQ cal before other calibration) is also
needed to avoid chip hang for chips before AR9485. This issue was
originally observed with AR9382.

During the issue kernel log was filled with following message
ath: timeout (100000 us) on reg 0xa640: 0x00000001 & 0x00000001 != 0x00000000
ath: timeout (100000 us) on reg 0xa2c4: 0x00158dd9 & 0x00000001 != 0x00000000
ath: Unable to reset channel (2412 MHz), reset status -5
ath: Unable to set channel

Signed-off-by: Rajkumar Manoharan <rmanoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-04-26 15:50:27 -04:00
Vasanthakumar Thiagarajan 66953d4385 ath9k_hw: Fix register offset AR_PHY_65NM_CH0_THERM for AR9340
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-04-25 14:50:10 -04:00
Felix Fietkau 4a4fdf2e0b ath9k_hw: replace magic values in register writes with proper defines
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2011-01-21 16:21:43 -05:00
Felix Fietkau 1bf3866182 ath9k_hw: fix PA predistortion training power selection
The EEPROM contains scale factors for the tx power, which define
the range of allowable difference between target power and training
power. If the difference is too big, PA predistortion cannot be used.
For 2.4 GHz there is only one scale factor, for 5 GHz there are
three, depending on the specific frequency range.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-12-13 15:23:33 -05:00
Vasanthakumar Thiagarajan 11441fb8b7 ath9k_hw: Setup paprd only for supported chains
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-12-07 16:54:23 -05:00
Vasanthakumar Thiagarajan 7090ad1416 ath9k_hw: Program appropriate register for temperature compensation cal for AR9485
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-12-07 16:54:22 -05:00
Vasanthakumar Thiagarajan 858b7e36e8 ath9k_hw: Add IQ cal changes for AR9485
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-12-07 16:54:14 -05:00
Vasanthakumar Thiagarajan 31faff815b ath9k_hw: Define IQcal correction coefficient registers using index
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-12-07 16:35:00 -05:00
Vasanthakumar Thiagarajan dd040f76ce ath9k_hw: Read and configure turnning caps to regulate freq accuracy
Right now it is done for only AR9485, will be done for ar9003 also
after proper testing.

Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-12-07 16:34:58 -05:00
Vasanthakumar Thiagarajan ab09b5b4be ath9k_hw: Configure internal regulator for AR9485
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-12-07 16:34:58 -05:00
Vasanthakumar Thiagarajan 47e84dfb41 ath9k_hw: Read and configure antenna diversity control for AR9485
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-12-07 16:34:57 -05:00
Vasanthakumar Thiagarajan 9936e65fae ath9k_hw: Configure xpa bias level for AR9485
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-12-07 16:34:56 -05:00
Felix Fietkau ab33449895 ath9k_hw: add register definitions related to PA predistortion
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-06-14 15:39:32 -04:00
Luis R. Rodriguez 7ca710d58e ath9k_hw: add register definitions for the new ANI
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-06-14 15:39:29 -04:00
Luis R. Rodriguez aea702b70a ath9k_hw: add support for the AR9003 baseband watchdog
The baseband watchdog will monitor blocks of the baseband
through timers and will issue an interrupt when things are
detected to be stalled. It is only available on the AR9003
family.

Cc: Sam Ng <sam.ng@atheros.com>
Cc: Paul Shaw <paul.shaw@atheros.com>
Cc: Don Breslin <don.breslin@atheros.com>
Cc: Cliff Holden <cliff.holden@atheros.com
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-06-02 16:13:00 -04:00
Luis R. Rodriguez 1547da37db ath9k_hw: add OFDM spur mitigation for AR9003
We add this now as OFDM spur mitigation required accessing
the EEPROM for the AR9003 devices.

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-04-16 15:43:38 -04:00
Luis R. Rodriguez 400b738678 ath9k_hw: abstract the AR_PHY_AGC_CONTROL register access
This is so we can share routines which access this register
on calib.c

Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-04-16 15:43:34 -04:00
Luis R. Rodriguez cffb5e49a1 ath9k_hw: add helpers for processing the AR9003 INI
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-04-16 15:43:24 -04:00
Felix Fietkau da6f1d7f5f ath9k_hw: Add AR9003 PHY register definitions
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
2010-04-16 15:43:23 -04:00