2 Commits

Author	SHA1	Message	Date
Masahiro Yamada	f2032f24c0	ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ... This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings document says that the bits[15:8] of the 3rd cell of the interrupts property represents PPI interrupt CPU mask. Because the timer interrupts are wired to all of the 4 cores, bits[15:8] should be set to 0xf. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>	2015-08-20 18:28:39 -07:00
Masahiro Yamada	a5e921b477	ARM: dts: uniphier: add ProXstream2 and PH1-LD6b SoC/board support ... Initial version of DTSI for ProXstream2 and PH1-LD6b and DTS for PH1-LD6b reference board. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [olof: sort Makefile entries] Signed-off-by: Olof Johansson <olof@lixom.net>	2015-08-11 15:09:32 +02:00