Commit Graph

90 Commits

Author SHA1 Message Date
Ralf Baechle beab375a48 [MIPS] Treat CPUs with AR bit as physically indexed.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:54 +01:00
Chris Dearman 73f403527b [MIPS] Fix handling of 0 length I & D caches.
Don't ask.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:53 +01:00
Chris Dearman 9318c51acd [MIPS] MIPS32/MIPS64 secondary cache management
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:52 +01:00
Sergei Shtylyov 9370b35175 [MIPS] Save write-only Config.OD from being clobbered
Save the Config.OD bit from being clobbered by coherency_setup(). This
bit, when set, fixes various errata in the early steppings of Au1x00
SOCs.  Unfortunately, the bit was write-only on the most early of them.
In addition, also restore the bit after a wakeup from sleep.
    
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-06 00:15:13 +01:00
Kumba 44d921b246 [MIPS] Treat R14000 like R10000.
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:35 +01:00
Ralf Baechle 7f3f1d01a9 [MIPS] Fix deadlock on MP with cache aliases.
A proper fix would involve introducing the notion of shared caches but
at this stage of 2.6.17 that's going to be too intrusive and not needed
for current hardware; aside I think some discussion will be needed.

So for now on the affected SMP configurations which happen to suffer from
cache aliases we make use of the fact that a single cache will be shared
by all processors.  This solves the deadlock issue and will improve
performance by getting rid of the smp_call_function overhead.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:33 +01:00
Nigel Stephens 98a41de99a [MIPS] Add missing 34K processor IDs
The 34K is very much like a 24K on steroids.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:30 +01:00
Atsushi Nemoto 3c68da798a [MIPS] Use __ffs() instead of ffs() for waybit calculation.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:30 +02:00
Ralf Baechle 7e3bfc7cfc [MIPS] Handle IDE PIO cache aliases on SMP.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:29 +02:00
Atsushi Nemoto 67a3f6de93 [MIPS] Fix tx49_blast_icache32_page_indexed.
Fix the cache index value in tx49_blast_icache32_page_indexed().
This is a damage by de62893bc0 commit.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:21 +02:00
Atsushi Nemoto de862b488e [MIPS] TX49XX has prefetch.
The TX49XX has the prefetch instruction.  It supports only Pref_Load
(hint 0).  Actually changes in this patch except for Kconfig are not
have any effects, I added these changes to prevent misuse of unsupported
hints.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21 13:27:47 +00:00
Atsushi Nemoto de62893bc0 [MIPS] local_r4k_flush_cache_page fix
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly.  Make
blast_?cache_page_indexed() masks its index value correctly.  Also,
use physical address for physically indexed pcache/scache.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18 16:59:27 +00:00
Ralf Baechle 4debe4f963 [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.
When a CPU has no scache, the scache flushing functions currently
aren't getting initialized and the NULL pointer is eventually called
as a function.  Initialize the scache flushing functions as a noop
when there's no scache.
    
Initial patch by me and most of the debugging done by Martin Michlmayr.
    
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-28 17:04:19 +00:00
Atsushi Nemoto 41700e7399 [MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
Add blast_xxx_range(), protected_blast_xxx_range() etc. for common
use.  They are built by __BUILD_BLAST_CACHE_RANGE().
Use protected_cache_op() macro for various protected_ routines.
Output code should be logically same.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 19:13:24 +00:00
Atsushi Nemoto d4264f1839 [MIPS] Remove wrong __user tags.
This fixes sparse warnings 'dereference of noderef expression'.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:25 +00:00
Ralf Baechle e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:06 +00:00
Ralf Baechle 6ec25809c1 Rename page argument of flush_cache_page to something more descriptive.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:42 +01:00
Ralf Baechle 02cf211968 Cleanup the mess in cpu_cache_init.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:32 +01:00
Thiemo Seufer 10a3dabddd Add/Fix missing bit of R4600 hit cacheop workaround.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:18 +01:00
Thiemo Seufer 02fe2c9ce3 Minor code cleanup.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:17 +01:00
Thiemo Seufer d8748a3abf More .set push/pop.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:16 +01:00
Thiemo Seufer 330cfe016b Let r4600 PRID detection match only legacy CPUs, cleanups.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:15 +01:00
Ralf Baechle 1d40cfcd34 Avoid SMP cacheflushes. This is a minor optimization of startup but
will also avoid smp_call_function from doing stupid things when called
from a CPU that is not yet marked online.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:54 +01:00
Ralf Baechle e01402b115 More AP / SP bits for the 34K, the Malta bits and things. Still wants
a little polishing.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:53 +01:00
Ralf Baechle ec74e361f1 Mark a few variables __read_mostly.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:46 +01:00
Ralf Baechle cc61c1fede MIPS R2 instruction hazard handling.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:46 +01:00
Thiemo Seufer ba5187dbb4 Better interface to run uncached cache setup code.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:11 +01:00
Ralf Baechle fe00f943e0 Sparseify MIPS.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:50 +01:00
Pete Popov e3ad1c23ba Base Au1200 2.6 support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:47 +01:00
Thiemo Seufer 26a51b270f Use intermediate variable.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:38 +01:00
Ralf Baechle 79acf83e50 Moves a test which determines if we actually need to perform a
cacheflush to the right place.  That's a bug which is harmless on UP
but a severe bug on SMP.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:31 +01:00
Ralf Baechle c6e8b58771 Update MIPS to use the 4-level pagetable code thereby getting rid of
the compacrapability headers.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:31 +01:00
Ralf Baechle 505403b6a0 25Kf is also physically indexed.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:29 +01:00
Ralf Baechle a95970f323 20Kc and SB1 don't suffer from aliases.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:28 +01:00
Ralf Baechle ae6aafe309 Move missplaced code line to the right place.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:26 +01:00
Ralf Baechle d1e344e500 Use hardware mechanism to deal with cache aliases in the 24K.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:25 +01:00
Ralf Baechle 28ecca4786 Remove old wrong bits of cache code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:25 +01:00
Ralf Baechle 42a3b4f25a [PATCH] mips: nuke trailing whitespace
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-05 00:06:07 -07:00
Ralf Baechle 875d43e72b [PATCH] mips: clean up 32/64-bit configuration
Start cleaning 32-bit vs. 64-bit configuration.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-05 00:06:06 -07:00
Linus Torvalds 1da177e4c3 Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!
2005-04-16 15:20:36 -07:00