This patch replaces the "cs-gpio" from "controller-data" node
as was specified in the old binding and uses the standard
"cs-gpios" property expected by the SPI core as is defined now
in the spi-s3c64xx driver DT binding.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
The Keystone 2 has MDIO HW block which are compatible
to Davinci SoCs:
See "Gigabit Ethernet (GbE) Switch Subsystem"
See http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf
Hence, add corresponding DT entry for Keystone 2.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tegra DSI support has been fixed to support continuous clock behavior that
the panel used on SHIELD requires, so finally add its device tree node
since it is functional.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The property for enabling external rail control on the AS3722 is
ams,ext-control, not ams,external-control. Since the external rail
control property was previously being ignored, LP1 suspend on these
boards wasn't actually turning the CPU rail off at all.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Assign lanes to the XUSB pads as used on the Jetson TK1.
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The device tree node in the SoC file contains only the resources (such
as registers, resets, ...) but none of the lane assignment information
since that's board specific and belongs in the board file.
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Input had been disabled by mistake on these pins, leading to issues with
SDIO devices like the Wifi module not being probed or random errors
occuring on the SD card.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The pinmux subsystem complained that the nvidia,low-power-mode property
is not supported by the sdio1, sdio3 and gma drive groups. In addition
gma also does not support nvidia,drive-type. Remove these properties so
the pinmux configuration can properly be applied.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This migration is required for continued PCIe operation after commit
d3c7e24b84fc "PCI: tegra: Implement accurate power supply scheme".
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
[swarren: added commit subject and shortened hash]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable the RGB output and add the panel definition to the Medcom Wide
DTS. Also add a label to the backlight defintion to reference it in
the panel definition.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Currently the Tamonten DTS define a fixed regulator for the 5V supply.
However this regulator is in fact on the base board. Fix this by
properly defining the regulators found on the base boards.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds the device tree to support Toradex Apalis T30, a
computer on module which can be used on different carrier boards.
The module consists of a Tegra 3 SoC, two PMICs, 1 or 2 GB of DDR3L
RAM, eMMC, an LM95245 temperature sensor chip, an i210 resp. i211
gigabit Ethernet controller, an STMPE811 ADC/touch controller as well
as two MCP2515 CAN controllers. Furthermore, there is an SGTL5000 audio
codec which is not yet supported. Anything that is not self contained
on the module is disabled by default.
The device tree for the Evaluation Board includes the modules device
tree and enables the supported peripherals of the carrier board (the
Evaluation Board supports almost all of them).
While at it also add the device tree binding documentation for Apalis
T30.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
[swarren: fixed some node sort orders]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The eMMC is soldered to the board, reflect this in the DT.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Turn on the HDA controller in Venice2, it is used for HDMI audio.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add a device node for the HDA controller found on Tegra124.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This adds the EC i2c tunnel (and devices under it) to the
tegra124-venice2 device tree.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add efuse and apbmisc bindings for Tegra20, Tegra30, Tegra114 and
Tegra124.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order to support dynamic frequency scaling:
* the cpuclk Device Tree node needs to be updated to describe a
second set of registers describing the PMU DFS registers.
* the clock-latency property of the CPUs must be filled, otherwise
the ondemand and conservative cpufreq governors refuse to work. The
latency is high because the cost of a frequency transition is quite
high on those CPUs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The CA9 MPcore SoC Control block is a set of registers that allows to
configure certain internal aspects of the core blocks of the SoC
(Cortex-A9, L2 cache controller, etc.). In most cases, the default
values are fine so they aren't many reasons to touch those registers,
but there is one exception: to support cpuidle on Armada 38x, we need
to modify the value of the CA9 MPcore Reset Control register.
Therefore, this commit adds a new Device Tree binding for this
hardware block, and uses this new binding for the Armada 38x Device
Tree file.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Display domain is removed due to instability issues. Explaining
the problem below:
exynos_init_late triggers the pm_genpd_poweroff_unused which powers
off the unused power domains. This call hits before the trigger to
deferred probes.
DRM DP Panel defers the probe due to supply get failure. By the time,
deferred probe is scheduled again, Display Power Domain is powered
off by pm_genpd_poweroff_unused.
FIMD and DP drivers are accessing registers during Probe and Bind
callbacks. If display domain is enabled/disabled around register
accesses, display domain gets unstable and we are getting Power Domain
Disable fail notification. Increasing the Timeout also didn't help.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add MAX98090 audio codec, I2S interface and the sound complex
nodes to enable audio on Odroid-X2/U3 boards.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
TFLASH (SDHCI2 controller) uses internal card detect line, but it looks
that the driver fails to operate it properly. Use GPIO interrupt on
SD_CDn line for detecting SD card state.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support for simple GPIO-based button availabled on
Exynos4 based Odroid boards. All supported boards have POWER button,
which has been defined in exynos4412-odroid-common.dtsi. X/X2 boards
also have additional user-configurable button which has been mapped to
KEY_HOME. All defined keys have been marked as possible wakeup source.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
On Odroid U2/U3 BUCK8 is used for providing power to also to P3V3
source, which is also connected to LAN9730 chip's nRESET signal. To
reset lan chip on system reboot, the BUCK8 output should not be used in
'always on' mode. This change has no impact on X/X2 boards.
Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch moves some parts of exynos4412-odroidx.dts to common
exynos4412-odroid-common.dtsi file and adds support for Odroid X2 and
U2/U3 boards. X2 is same as X, but it has faster SoC module (1.7GHz
instead of 1.4GHz), while U2/U3 differs from X2 by different way of
routing signals to host USB hub. It also lacks some hw modules not yet
supported by those dts files (i.e. LCD & touch panel).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Last megabyte of RAM is used by secure firmware and should not be accessed
by Linux kernel, so correct available memory size in DTS file.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds basic support for USB modules (host and device) on
OdroidX board.
Signed-off-by: Kamil Debski <k.debski@samsung.com>
[removed incorrect port@2 node]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support for common hardware modules available on all
Exynos4412-based Odroid boards, which already have complete support in
mainline kernel. This includes secure firmware calls, watchdog, g2d and
fimc (mem2mem) multimedia accelerators.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds port sub-nodes to exynos4 ehci and ohci modules, which
are required by recently merged new exynos4 usb2 phy support.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake. If we don't set it to anything then
the TPM will be reset. U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything. It will get pulled back high again during a
normal warm reset when it will default back to an input.
To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake. If we don't set it to anything then
the TPM will be reset. U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything. It will get pulled back high again during a
normal warm reset when it will default back to an input.
To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
DRA7xx has 13 system mailboxes, and is present on both the
DRA72x and DRA74x family of SoCs. Add the DT nodes for all
these 13 mailboxes. Except for mailbox 1, all other mailboxes
do not have interrupts mapped into the MPU GIC by default.
All the mailboxes have been disabled and the interrupts
property information is left out intentionally for now,
because of the dependencies against the crossbar driver.
These mailboxes can be enabled when a usecase arises
and the crossbar driver dependencies are met.
NOTE: The mailbox 1 has different number of mailbox fifos
and IP interrupts compared to the remaining 12 mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The mailbox DT node for AM4372 is enabled and is corrected to
remove some properties that have crept in by mistake.
Fixes: 9e3269b (ARM: dts: AM4372: Add L2, EDMA, mailbox, MMC and SHAM nodes)
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The mailbox DT node data has been added for AM33xx device.
The mailbox IP in AM33xx is similar to the version found in
OMAP4+ devices.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The mailbox DT node data has been added for OMAP44xx
devices.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The number of mailbox fifos and users (IP interrupts) are added
to the Mailbox DT nodes on OMAP2420, OMAP2430, OMAP3, and OMAP5
family of SoCs through the DT properties "ti,mbox-num-fifos" and
"ti,mbox-num-users" properties. This data represents the same data
that used to be represented in hwmod attribute data through the
.num_fifos and .num_users fields previously.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The board uses twl6040 codec connected via McPDM link. McBSP1 and McBSP2 can
be used for FM/BT.
At the same time move the pinctrl handling to the correct place - under the
corresponding nodes.
Audio connectors on the board:
Headset in/out
Stereo Line out
Stereo Line in.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The board uses twl6040 as audio codec. Move the corresponding pinctrl as
well under the node.
twl6040 needs 32k clock from palams.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
26.3.3 PCIe Shared PHY Subsystem Integration in vE of DRA7xx ES1.0
describes the PCIe PHY subsystem-related components integrated in the device.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Added missing clocks used by second instance of PCIe PHY.
The documention for this nodes can be found @ ../bindings/clock/ti/gate.txt.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There are two instances of PCIe PHY in DRA7xx. So renamed
optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to
optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk
respectively. This is needed for adding the clocks for second PCIe PHY
instance.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Figure 26-22. DPLL_PCIE_REF Functional Block Diagram in vE of DRA7xx ES1.0 TRM
shows the signal name for the output of post divider (M2) is CLKOUTLDO.
Figure 26-21. PCIe PHY Clock Generator Overview shows CLKOUTLDO is used as
input to apll mux.
So the actual output of dpll is dpll_pcie_ref_m2ldo_ck which is also the input
of apll.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add divider table to optfclk_pciephy_div clock. The 8th bit of
CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1
based on if the divider value is 0x2 or 0x1.
Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the
block diagram of Clock Generator Subsystem of PCIe PHY module. The divider
value if '1' should be programmed in order to get the correct
PCIE_PHY_DIV_GCLK frequency (2.5GHz).
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With sun8i PRCM support available, we can add the PRCM clock and
reset controller nodes to the DTSI. Also update R_UART's clock
phandle and add it's reset control phandle.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
add #reset-cells to socfpga.dtsi. This was missing from the
latest updates and caused the socfpga reset controller to fail
to load like so:
ffd05000.rstmgr: /soc/rstmgr@ffd05000 missing #reset-cells property
probe of ffd05000.rstmgr failed with error -22
Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx
SoCs.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with
ahci/sata pins. By default evaluation board of both controller works in ahci
mode. Because of this, these nodes are marked "disabled" by default.
In order to use pcie controller on evaluation boards do necessary modifications
on board and enable (By replacing "disabled" with "okay") pcie and miphy from
respective 'evb' dtsi file.
Phy specific initialization was previously done from spear1340.c, which isn't
required anymore as we have separate drivers for it. Remove it.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
SPEAr SOCs have some miscellaneous registers which are used to configure
peripheral.
This patch adds dt node and binding information for this block.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: devicetree@vger.kernel.org
[viresh: fixed logs/cclist]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Now that all boards have been converted to DT and all the support code
lives in mach-mvebu, we can remove mach-kirkwood.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1405028192-9623-2-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds DT support for the LaCie NAS d2 Network v2 (d2net_v2).
Most of the hardware characteristics are shared with the 2Big and 5Big
Network v2 boards.
- CPU: Marvell 88F6281 1200Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- 2 SATA ports: internal and eSATA
- Gigabit ethernet: PHY Marvell 88E1116R
- Flash memory: SPI NOR 512KB (Macronix MX25L4005A)
- i2c EEPROM: 512 bytes (24C04 type)
- 2 USB2 ports: host and host/device
- 1 push button
- 1 power switch
- 1 SATA LED (bi-color, blue and red)
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1404830545-15581-3-git-send-email-simon.guinot@sequanux.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The d2 Network v2 board (d2net_v2) shares a lot of hardware
characteristics with the 2Big and 5Big Network v2 boards. This patch
prepares the kirkwood-netxbig.dtsi file in order to allow to include it
from the d2net_v2 DTS file. The DT nodes only relevant for the 2Big and
5Big Network v2 boards are moved into their respective DTS files.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1404830545-15581-2-git-send-email-simon.guinot@sequanux.org
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Consistently use tabs for indentation
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Merge tag 'renesas-r8a7779-multiplatform3-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Third Round of Renesas ARM Based SoC r8a7779-multiplatform Updates
for v3.17" from Simon Horman:
- Consistently use tabs for indentation
* tag 'renesas-r8a7779-multiplatform3-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: marzen: Consistently use tabs for indentation
Signed-off-by: Olof Johansson <olof@lixom.net>
some constification from static code analysis.
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Merge tag 'ux500-core-for-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/cleanup
Merge "Ux500 core changes for v3.17 take 1" from Linus Walleij:
Some minor cleanups to the Ux500 core. DT-only probe path and
some constification from static code analysis.
* tag 'ux500-core-for-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: remove pointless cache setup complexity
ARM: ux500: storage class should be before const qualifier
ARM: ux500: Staticize ab8505_regulators
ARM: ux500: Staticize local symbols in cpu-db8500.c
ARM: ux500: Staticise ux500_soc_attr
+ Linux 3.16-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add regulators to STMPE expanders
- Add proper DMA channels for all SD/MMC blocks
- Add sensors to the device tree
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Merge tag 'ux500-devicetree-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
Merge "Ux500 devicetree changes for v3.17" from Linus Walleij:
Ux500 device tree patches for v3.17:
- Add regulators to STMPE expanders
- Add proper DMA channels for all SD/MMC blocks
- Add sensors to the device tree
* tag 'ux500-devicetree-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: add misc sensors to the device trees
ARM: ux500: add some DB8500 DMA channel info
ARM: ux500: add VCC and VIO regulators to STMPE IC
+ Linux 3.16-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
- update the parent for Auudss clock because kernel will be hang
during late boot if the parent clock is disabled in bootloader.
- enable clk handing in power domain because while power domain
on/off, its regarding clock source will be reset and it causes
a problem so need to handle it.
- add mux clocks to be used by power domain for exynos5420-mfc
during power domain on/off and property in device tree also.
- register cpuidle only for exynos4210 and exynos5250 because a
system failure will be happened on other exynos SoCs.
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Merge tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Merge "Samsung fixes-3 for 3.16" from Kukjin Kim:
Samsung fixes-3 for v3.16
- update the parent for Auudss clock because kernel will be hang
during late boot if the parent clock is disabled in bootloader.
- enable clk handing in power domain because while power domain
on/off, its regarding clock source will be reset and it causes
a problem so need to handle it.
- add mux clocks to be used by power domain for exynos5420-mfc
during power domain on/off and property in device tree also.
- register cpuidle only for exynos4210 and exynos5250 because a
system failure will be happened on other exynos SoCs.
* tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250
ARM: dts: Add clock property for mfc_pd in exynos5420
clk: exynos5420: Add IDs for clocks used in PD mfc
ARM: EXYNOS: Add support for clock handling in power domain
ARM: dts: Update the parent for Audss clocks in Exynos5420
Signed-off-by: Olof Johansson <olof@lixom.net>
* Extend hardware coverage
- Add DVC support for sound nodes on r8a7791 and r8a7790
- Enable internal PCI on r8a7790/lager
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Merge tag 'renesas-dt2-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Merge "Second Round of Renesas ARM Based SoC DT Updates for v3.17" from Simon
Horman:
- Extend hardware coverage
* Add DVC support for sound nodes on r8a7791 and r8a7790
* Enable internal PCI on r8a7790/lager
* tag 'renesas-dt2-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791: add DVC support for sound node on DTSI
ARM: shmobile: r8a7790: add DVC support for sound node on DTSI
ARM: shmobile: lager: enable internal PCI
ARM: shmobile: r8a7790: add internal PCI bridge nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
Add clocks for usb device, or else switch to CCF, the gadget
won't work.
Reported-by: Jiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: Jiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This describes all of the SCIF hardware of the sh73a0.
Each node is disabled and may be enabled as necessary
by board DTS files.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This describes all of the SCIF hardware of the r8a7740.
Each node is disabled and may be enabled as necessary
by board DTS files.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This describes all of the SCIF hardware of the r8a73a4.
Each node is disabled and may be enabled as necessary
by board DTS files.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Initialise SCIF device using DT when booting bockw
using DT reference.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This describes all of the SCIF hardware of the r8a7778.
Each node is disabled and may be enabled as necessary
by board DTS files.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Pads for PB0-PB3, PC0-PC4, PE26-PE31 and PF24-PF31 does not exist on
the i.MX27 SOC. There is no reason to define them, the presence of
such definitions in the DTS files is a bug.
This patch removes these nonexistent pad definitions.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On Lager board, i2c and iic cores can be interchanged since they can be
muxed to the same wires. Commit e489c2a9bc
("ARM: shmobile: lager: enable i2c devices") activated the i2c cores,
yet the iic cores should be default since they have the more interesting
features for generic use cases, i.e. SMBUS_QUICK and DMA (yet to be
supported).
Reported-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
I2C bus for VDD MPU regulator is IIC3, not I2C3.
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Reviewed-by: Wolfram Sang <wsa@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Adding the optional clock property for the mfc_pd for
handling the re-parenting while pd on/off.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
restart handling and phy regulators and SATA interconnect data.
Also few build fixes related to the DSP driver in staging, and trivial
stuff like removal of broken and soon to be unused platform data init
for HDMI audio that would be good to get into the -rc series if not
too late.
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Merge tag 'omap-for-v3.16/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge "omap fixes against v3.16-rc4" from Tony Lindgren:
Fixes for omaps for the -rc series. It's mostly fixes for clock rates,
restart handling and phy regulators and SATA interconnect data.
Also few build fixes related to the DSP driver in staging, and trivial
stuff like removal of broken and soon to be unused platform data init
for HDMI audio that would be good to get into the -rc series if not
too late.
* tag 'omap-for-v3.16/fixes-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Remove non working OMAP HDMI audio initialization
ARM: dts: Fix TI CPSW Phy mode selection on IGEP COM AQUILA.
ARM: dts: am335x-evmsk: Enable the McASP FIFO for audio
ARM: dts: am335x-evm: Enable the McASP FIFO for audio
ARM: OMAP2+: Make GPMC skip disabled devices
ARM: OMAP2+: create dsp device only on OMAP3 SoCs
ARM: dts: dra7-evm: Make VDDA_1V8_PHY supply always on
ARM: DRA7/AM43XX: fix header definition for omap44xx_restart
ARM: OMAP2+: clock/dpll: fix _dpll_test_fint arithmetics overflow
ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
ARM: DRA7: hwmod: Fixup SATA hwmod
ARM: OMAP3: PRM/CM: Add back macros used by TI DSP/Bridge driver
ARM: dts: dra7xx-clocks: Fix the l3 and l4 clock rates
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds alias entries for UART nodes of all SoCs using
samsung-uart compatible UART controllers, so that the dependency on
probe order is removed and deterministic device naming is assured.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add new properties to all of the Tegra PHYs that are now required
according to the binding.
In order to stay compatible with old device trees, the USB drivers
will still function without these reset properties but with the old,
potentially buggy behaviour.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Define at91sam9263ek main and slow crystals frequencies.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define the at91sam9263 clocks in the SoC dtsi file.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define at91sam9m10g45ek main and slow crystals frequencies.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define the at91sam9g45 clocks in the SoC dtsi file.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define Somfy Animeo IP main and slow crystals frequencies.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define AK signal CDU slow crystal frequency
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define Calao TNY-A9260 and TNY-A9G20 main and slow crystals frequencies.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define Calao USB-A9260, USB-A9G20 and USB-A9G20-LPW main and slow crystals
frequencies.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define Acme Systems srl Fox G20 main and slow crystals frequencies.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define at91sam9g20ek main and slow crystals frequencies.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define the at91sam9g20 clocks that differ from at91sam9260 in the SoC dtsi file.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define the at91sam9260 clocks in the SoC dtsi file.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define at91rm9200ek main and slow crystals frequencies.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Define Acme Systems Aria G25 board main and slow crystals frequencies.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add the "atmel,nand-has-dma" property to NAND node
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
As the at91sam9n12ek has switch to CCF, so add clock for wm8904
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviwed-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
As the sama5d3xek board has switch to CCF, so add clock for wm8904
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviwed-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Having clocks grouped in a subnode is common practice, so move the crystals
under a clocks node for the sama5d3 SoC and sama5d3 based boards.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Having clocks grouped in a subnode is common practice, so move the crystals and
the ADC clock under a clocks node for the at91sam9x5 SoC and at91sam9x5 based
boards.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Having clocks grouped in a subnode is common practice, so move the crystals
under a clocks node for the at91sam9rl SoC and at91sam9rl based boards.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Having clocks grouped in a subnode is common practice, so move the crystals
under a clocks node for the at91sam9n12 SoC and at91sam9n12 based boards.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Having clocks grouped in a subnode is common practice, so move the crystals
under a clocks node for the at91sam9261 SoC and at91sam9261 based boards.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The ldousb_reg regulator provides power to the USB1 and USB2
High Speed PHYs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add TPS65218 device tree nodes. i2c clock frequency setting
also added as part of tps65218 nodes addition. As i2c clock
enabling is required.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add TPS65218 device tree nodes. i2c clock frequency setting
also added as part of tps65218 nodes addition. As i2c clock
enabling is required.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There is a IRQ crossbar device in the soc, which
maps the irq requests from the peripherals to the
mpu interrupt controller's inputs. The Peripheral irq
requests are connected to only one crossbar
input and the output of the crossbar is connected to only one
controller's input line. The crossbar device is used to map
a peripheral input to a free mpu's interrupt controller line.
Here, adding a new crossbar device node and replacing all the peripheral
interrupt numbers with its fixed crossbar input lines.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There is a IRQ crossbar device in the soc, which maps the
irq requests from the peripherals to the mpu interrupt
controller's inputs. The gic provides the support for such
IPs in the form of routable-irqs. So adding the property
here to gic node.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Benoit Cousson <bcousson@baylibre.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As early printk is not supported when devices are initialised
using DT, so remove it from the command line.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
As early printk is not supported when devices are initialised
using DT, so remove it from the command line.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to
them.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
[horms+renesas@verge.net.au: minor witespace changes]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to
them.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
[horms+renesas@verge.net.au: minor witespace changes]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add ABB device nodes for OMAP5 family of devices. Data is based on
final production OMAP543x Technical Reference Manual revision Z (April 2013).
Final production Data Manual for OMAP5432 SWPS050F(APRIL 2014).
[nm@ti.com: co-developer and updates to latest documentation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrii.Tseglytskyi <andrii.tseglytskyi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- L2CC latency properties for BG2Q
- DW i2c nodes for BG2Q and corresponding dev board
- SMP related nodes for BG2 and BG2Q
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Merge tag 'berlin-dt-3.17-1' of git://git.infradead.org/users/hesselba/linux-berlin into next/dt
Merge "Berlin DT changes for v3.17" from Sebastian Hesselbarth:
- L2CC latency properties for BG2Q
- DW i2c nodes for BG2Q and corresponding dev board
- SMP related nodes for BG2 and BG2Q
* tag 'berlin-dt-3.17-1' of git://git.infradead.org/users/hesselba/linux-berlin:
ARM: dts: berlin: add SMP related nodes and properties for BG2Q
ARM: dts: berlin: add SMP related nodes and properties for BG2
Documentation: bindings: add the marvell,berlin-smp CPU enable method
Documentation: bindings: add the Berlin CPU control doc
ARM: dts: berlin: enable i2c0 and i2c2
ARM: dts: berlin: add I2C nodes for BG2Q
ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles
Signed-off-by: Olof Johansson <olof@lixom.net>
- Remove <mach/memory.h> from the Integrator, paving the
road for multiplatform.
- Push the CLCD helper code down into the framebuffer subsystem,
removing the last hook in plat-versatile for the Integrator,
also paving the road for multiplatform.
Patches tested on Integrator/AP, Integrator/CP and Versatile AB
(all real hardware).
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Merge tag 'versatile-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/cleanup
Merge "First pull request of Versatile family clean-ups for v3.17" from Linus
Walleij:
- Remove <mach/memory.h> from the Integrator, paving the
road for multiplatform.
- Push the CLCD helper code down into the framebuffer subsystem,
removing the last hook in plat-versatile for the Integrator,
also paving the road for multiplatform.
Patches tested on Integrator/AP, Integrator/CP and Versatile AB
(all real hardware).
* tag 'versatile-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
video: move Versatile CLCD helpers
ARM: integrator: get rid of <mach/memory.h>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge tag 'versatile-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next/soc
Merge "DT IRQ and clock support for Versatile platforms" from Rob Herring.
This branch moves IRQ and clock support over to DT for the versatile
platforms.
* tag 'versatile-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
clk: versatile: add versatile OSC support
dts: versatile: add clock tree
ARM: timer-sp: allow getting timer1 clock from DT to fallback to legacy clock
dt/bindings: add compatible string for versatile osc clock
dt/bindings: arm-boards: add binding for Versatile core module
dts: versatile: add pl180 compatible strings
ARM: versatile: remove init_irq hook for DT boot
ARM: integrator: convert to use irqchip_init
irqchip: versatile-fpga: add support for arm,versatile-sic
irqchip: versatile-fpga: Add IRQCHIP_DECLARE support
dts: versatile: add missing irq controller properties
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
- fix the check for SMP configuration with using CONFIG_SMP
not just SMP
- fix the number of pwm-cells for exynos4 pwm
- fix ftrace for exynos_mct
- register exynos_mct for stable udely
- fix secondary boot addr for secure mode for exynos SoCs
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Merge tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Merge "Samsung fixes-2 for v3.16" from Kukjin Kim:
- fix the check for SMP configuration with using CONFIG_SMP
not just SMP
- fix the number of pwm-cells for exynos4 pwm
- fix ftrace for exynos_mct
- register exynos_mct for stable udely
- fix secondary boot addr for secure mode for exynos SoCs
* tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Update secondary boot addr for secure mode
clocksource: exynos_mct: Register the timer for stable udelay
clocksource: exynos_mct: Fix ftrace
ARM: dts: fix pwm-cells in pwm node for exynos4
ARM: EXYNOS: Fix the check for non-smp configuration
Signed-off-by: Olof Johansson <olof@lixom.net>
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.
The problem surfaced when the bootloader in Peach-pit board set
the EPLL clock as the parent of AUDSS mux. While booting the kernel,
we used to get a system hang during late boot if CLK_MAU_EPLL was
disabled.
Signed-off-by: Tushar Behera <tushar.b@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Reported-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add sound-card name property to Snow/Peach-Pit/Peach-Pi boards.
Signed-off-by: Tushar Behera <tushar.b@samsung.com>
Acked-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
It's 1.6 GHz for the Cortex-A15.
Avoids warnings like "/cpus/cpu@0 missing clock-frequency property".
Signed-off-by: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Tarek Dakhran <t.dakhran@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
As this board use external clock for RMII interface we should specify 'rmii'
phy mode and 'rmii-clock-ext' to make ethernet working.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The use of FIFO in McASP can reduce the risk of audio under/overrun and
lowers the load on the memories since the DMA will operate in bursts.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The use of FIFO in McASP can reduce the risk of audio under/overrun and
lowers the load on the memories since the DMA will operate in bursts.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
After clarification from the hardware team it was found that
this 1.8V PHY supply can't be switched OFF when SoC is Active.
Since the PHY IPs don't contain isolation logic built in the design to
allow the power rail to be switched off, there is a very high risk
of IP reliability and additional leakage paths which can result in
additional power consumption.
The only scenario where this rail can be switched off is part of Power on
reset sequencing, but it needs to be kept always-on during operation.
This patch is required for proper functionality of USB, SATA
and PCIe on DRA7-evm.
CC: Rajendra Nayak <rnayak@ti.com>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds the STMicroelectonics MEMS sensor devices to the Ux500
family device trees:
- Accelerometer
- Magnetometer
- Gyroscope
- Pressure (barometer)
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Denis CIOCCA <denis.ciocca@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds some missing DMA channel information to the disabled
MMC/SD/SDIO blocks number 3 and 5, and notes that the assignment
of MSP channels vary with ASIC variant.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a VCC and VIO regulator supplies to the the STMPE expander
found on the STUIB UIB variants.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The A23 has the same MMIO reset controllers matching the clocks gates,
just like in the A31. This patch adds the reset controller nodes and
the reset control phandles for the peripherals needing them to the
DTSI.
Unlike the sun6i DTSI, this patch uses sun6i-a31-clock-reset for
ahb1_rst. sun6i-a31-ahb-reset is for early init, and requires some
additions to the machine code. It is used to support the hstimer.
However the hstimer on sun8i only has 1 timer, which is somewhat
useless. Support for it will probably not be added. Hence the
decision to use sun6i-a31-clock-reset here to avoid the changes to
sun8i machine code.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Use shmobile_init_delay on r8a7790, r7s72100 and EMEV2 SoCs
* Remove unused redundant callbacks on EMEV2 SoC
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Merge tag 'renesas-soc-cleanup-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup
Merge "Renesas ARM Based SoC Cleanup for v3.17" from Simon Horman:
- Use shmobile_init_delay on r8a7790, r7s72100 and EMEV2 SoCs
- Remove unused redundant callbacks on EMEV2 SoC
* tag 'renesas-soc-cleanup-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Remove unused r8a7790_init_early()
ARM: shmobile: Use r8a7790 DT CPU Frequency for Lager
ARM: shmobile: Use r8a7790 DT CPU Frequency in common case
ARM: shmobile: Use shmobile_init_delay() on r7s72100
ARM: shmobile: Use shmobile_init_delay() on Genmai boards
ARM: shmobile: Update r7s72100 DTS to include CPU frequency
ARM: shmobile: Get rid of redundant EMEV2 mach callbacks
ARM: shmobile: Use shmobile_init_delay() on EMEV2
ARM: shmobile: Update EMEV2 DTS to include CPU frequency
Signed-off-by: Olof Johansson <olof@lixom.net>
Move r8a7779 SoC and its Marzen board to use common clocks,
multiplatform and initialise SCIF (serial) devices using DT.
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Merge tag 'renesas-r8a7779-multiplatform-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Renesas ARM Based SoC r8a7779-multiplatform Updates for v3.17" from
Simon Horman:
Move r8a7779 SoC and its Marzen board to use common clocks,
multiplatform and initialise SCIF (serial) devices using DT.
* tag 'renesas-r8a7779-multiplatform-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (32 commits)
ARM: shmobile: marzen: Do not use workaround for scif devices
ARM: shmobile: marzen: Initialise SCIF devices using DT
ARM: shmobile: marzen: Remove early_printk from command line
ARM: shmobile: r8a7779: Add scif nodes to dtsi
ARM: shmobile: r8a7779 dtsi: Correct #address-cells/#size-cells for clocks
ARM: shmobile: r8a7779 dtsi: Update unit-addresses for clocks
ARM: shmobile: r8a7779: Remove unused r8a7779_init_delay()
ARM: shmobile: marzen-reference: Use DT CPU Frequency
ARM: shmobile: r8a7779: Use DT CPU Frequency in common case
ARM: shmobile: r8a7779: Add Maximum CPU Frequency to DTS
ARM: shmobile: marzen-reference: Remove legacy clock support
ARM: shmobile: Remove Marzen reference DTS
ARM: shmobile: Let Marzen multiplatform boot with Marzen DTB
ARM: shmobile: Remove non-multiplatform Marzen reference support
ARM: shmobile: marzen-reference: Instantiate clkdevs for SCIF and TMU
ARM: shmobile: marzen-reference: Initialize CPG device
ARM: shmobile: r8a7779: Initial multiplatform support
ARM: shmobile: marzen-reference: Move clock and OF device initialisation into board code
ARM: shmobile: r8a7779: Move r8a7779_earlytimer_init to clock-r8a7779.c
ARM: shmobile: r8a7779: Add helper to read mode pins
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Add SPI device for RSPI on Genmai.
On this board, only rspi4 is in use. Its bus contains a single device
(a wm8978 audio codec), for which no bindings are defined yet.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
enabling of a few features that had to wait for the driver
dependencies to clear.
The fixes included are:
- Fix am43xx hard reset flags
- Fix SoC detection for DRA722
- Fix CPU OPP table for omap5
- Fix legacy mux parser bug if requested muxname is a prefix of
multiple mux entries
- Fix qspi interrupt binding that relies on the irq crossbar
that has not yet been enabled
- Add missing phy_sel for am43x-epos-evm
- Drop unused gic_init_irq() that is no longer needed
And the enabling of features that had driver dependencies are:
- Change dra7 to use Audio Tracking Logic clock instead of a fixed
clock now that the clock driver for it has been merged
- Enable off idle configuration for selected omaps as all the kernel
dependencies for device tree based booting are finally merged as
this is needed to get the automated PM tests working finally with
device tree based booting
- Add hwmod entry for ocp2scp3 for omap5 to get sata working as
all the driver dependencies are now in the kernel and this patch
fell through the cracks during the merge window
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Merge tag 'omap-for-v3.16/fixes-against-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Merge OMAP fixes from Tony Lindgren:
Fixes for omaps for issues discovered during the merge window and
enabling of a few features that had to wait for the driver
dependencies to clear.
The fixes included are:
- Fix am43xx hard reset flags
- Fix SoC detection for DRA722
- Fix CPU OPP table for omap5
- Fix legacy mux parser bug if requested muxname is a prefix of
multiple mux entries
- Fix qspi interrupt binding that relies on the irq crossbar
that has not yet been enabled
- Add missing phy_sel for am43x-epos-evm
- Drop unused gic_init_irq() that is no longer needed
And the enabling of features that had driver dependencies are:
- Change dra7 to use Audio Tracking Logic clock instead of a fixed
clock now that the clock driver for it has been merged
- Enable off idle configuration for selected omaps as all the kernel
dependencies for device tree based booting are finally merged as
this is needed to get the automated PM tests working finally with
device tree based booting
- Add hwmod entry for ocp2scp3 for omap5 to get sata working as
all the driver dependencies are now in the kernel and this patch
fell through the cracks during the merge window
* tag 'omap-for-v3.16/fixes-against-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: dra7-evm: remove interrupt binding
ARM: OMAP2+: Fix parser-bug in platform muxing code
ARM: DTS: dra7/dra7xx-clocks: ATL related changes
ARM: OMAP2+: drop unused function
ARM: dts: am43x-epos-evm: Add Missing cpsw-phy-sel for am43x-epos-evm
ARM: dts: omap5: Update CPU OPP table as per final production Manual
ARM: DRA722: add detection of SoC information
ARM: dts: Enable twl4030 off-idle configuration for selected omaps
ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
ARM: OMAP2+: hwmod: Change hardreset soc_ops for AM43XX
pwm-cells should be 3. Third cell is optional PWM flags. And This flag
supported by this binding is PWM_POLARITY_INVERTED.
Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Now that we have support for sun8i specific clocks in the driver,
add the corresponding clock nodes to the DTSI. Also update the
existing peripherals with the correct clocks.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Without the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
532000000
With the patch:
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck # cat clk_rate
532000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div # cat clk_rate
266000000
/debug/.../dpll_core_x2_ck/dpll_core_h12x2_ck/l3_iclk_div/l4_root_clk_div # cat clk_rate
133000000
The l3 clock derived from core DPLL is actually a divider clock,
with the default divider set to 2. l4 then derived from l3 is a fixed factor
clock, but the fixed divider is 2 and not 1. Which means the l3 clock is
half of core DPLLs h12x2 and l4 is half of l3 (as seen with this patch)
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Otherwise legacy boot clock data is used. This patch also includes the
clock data files to the base dtsi files.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Add the necessary nodes to enable the LCD controller and the
LCD panel that is attached to the Texas Instruments AM335x
EVMSK platform. Also setup the necessary pin mux within the
DT file to drive the LCD connector and add the correct
pinmux settings for the lcd pins to be configured to when
the SoC goes into sleep state for the minimum power
consumption.
For the sleep mode LCD pin settings, MUX_MODE7 is chosen as
this corresponds to switching the pins into input GPIO's with
an internal pulldown. Which has been determined to offer the
lowest power solution vs leaving the pins configured in LCD
mode.
Signed-off-by: Darren Etheridge <detheridge@ti.com>
Acked-by: Wolfram Sang <wsa@sang-engineering.com>
Tested-by: Felipe Balbi <balbi@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for TI's AM437x StarterKit Evaluation
Module.
Cc: Josh Elliot <jelliott@ti.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Tested-by: Franklin Cooper Jr. <fcooper@ti.com>
Tested-by: Tom Rini <trini@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
By providing labels for rtc, wdt, cpu and dispc nodes,
boards can access them to add board-specific data.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Tested-by: Franklin Cooper Jr. <fcooper@ti.com>
Tested-by: Tom Rini <trini@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tested on a cubieboard and the mini-x.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The ba10 tvbox is an A10 based android tvbox, with 512M RAM, 8G nand flash,
rtl8188ctv usb wifi 1 USB-A receptacle hooked up to an EHCI/OHCI controller,
1 USB-A receptacle hooked up to the OTG and 100Mbit ethernet using a
rtl8201 phy.
The PCB is labelled ba10 hence I've named the board ba10-tvbox. It is used
in noname allwinner A10 tv-boxes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The LinkSprite pcDuino V3 is an A20 based development board featuring
arduino compatible io headers, 1G RAM, 4G nand, sata, rtl8188cus usb wifi
and 100 Mbit ethernet using an ip101a phy:
http://www.pcduino.com/pcduino-v3/
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
[hdegoede@redhat.com: Various cleanups, correct led pins]
[hdegoede@redhat.com: Add axp209, ir and gpio-keys nodes]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The sun7i block is the same as the one in the sun4i, rename the compatible
to reflect this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
--
I've already included the matching change to sunxi-cir.c in my pull-req to
Mauro.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
At a node for the axp209, and where necessary the i2c controller to the dts
for various boards. Note the axp209 regulators are omitted as we don't have
any use for them yet, and on some boards were not sure how exactly they are
wired up.
Adding support for just the axp209 without the regulators is still useful, as
it will give us power-button and poweroff support.
Signed-off-by: Carlo Caione <carlo@caione.org>
[hdegoede@redhat.com: Drop the regulator bits for now]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
At a node for the axp209, and where necessary the i2c controller to the dts
for various boards. Note the axp209 regulators are omitted as we don't have
any use for them yet, and on some boards were not sure how exactly they are
wired up.
Adding support for just the axp209 without the regulators is still useful, as
it will give us power-button and poweroff support.
Signed-off-by: Carlo Caione <carlo@caione.org>
[hdegoede@redhat.com: Drop the regulator bits for now]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The pinctrl device is also an interrupt controller for external
interrupts. Add the missing #interrupt-cells property.
Also remove the unused #address-cells property.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[hdegoede@redhat.com: make the same change for sun4i, sun5i and sun6i]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Ippo-q8h is a tablet circuit board commonly found in cheap Android
tablets with A23 SoCs. There are at least 2 versions of the board, with
different peripherals, such as WiFi chips.
Common features among these tablets include 512 MB DRAM, NAND, MMC, LCD,
capacitive touchscreen, accelerometer, 1 or 2 camera sensors, USB OTG,
microphone and speaker.
v5 of these board designs has a ESP8089 WiFi chip (not supported)
connected to mmc1. This patch adds very basic support.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Integrator has a custom <mach/memory.h> header defining the
BUS_OFFSET for *_to_bus and bus_to_* operations as offset from
0x80000000.
This switches the Integrator over to using the mechanism
introduced for the Keystone to provide the same offset using
the device tree, deletes <mach/memory.h> and augments the
Integrator device tree to provide the bus offset.
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Jonathan Austin <jonathan.austin@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a stdout-path property to the Versatile devicetree so that automatic
console selection works without needing a console= line on the kernel
command line.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to
them.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
[Sergei: enabled PCI0]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add device nodes for the R8A7790 internal PCI bridge devices.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
[Sergei: added several properties to the PCI bridge nodes]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- drivers/misc fix for Kconfig PWM symbol
- correction of several values in DT after conversion to CCF
- fix at91sam9261/at91sam9261ek mistake in slow crystal vs. slow RC osc
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Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixes
Merge "First AT91 fixes batch for 3.16" from Nicolas Ferre:
- drivers/misc fix for Kconfig PWM symbol
- correction of several values in DT after conversion to CCF
- fix at91sam9261/at91sam9261ek mistake in slow crystal vs. slow RC osc
* tag 'at91-fixes' of git://github.com/at91linux/linux-at91:
ARM: at91/dt: sam9261: remove slow RC osc
ARM: at91/dt: define sam9261ek slow crystal frequency
ARM: at91/dt: sam9261: correctly define mainck
ARM: at91/dt: sam9n12: correct PLLA ICPLL and OUT values
ARM: at91/dt: sam9x5: correct PLLA ICPLL and OUT values
misc: atmel_pwm: fix Kconfig symbols
The at91sam9261 doesn't actually have a slow RC oscillator, remove it from the
dtsi.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
ICPLL can only take 0 or 1, it got mixed with OUT which can be in the [0-3]
range.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
ICPLL can only take 0 or 1, it got mixed with OUT which can be in the [0-3]
range.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The versatile dts is missing any clock data. Add the clocks.
It is not clear from the documentation where pclk comes from, so for
now it is a dummy clock which is sufficient for things to work.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
While not needed for probing, add the "arm,pl180" compatible string for
completeness.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Add valid-mask and clear-mask properties to the versatile dts so the
platform code doing the same thing can be removed.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Wildcards in compatible strings should be avoid. "marvell,armada38x"
was recently introduced but was not yet used.
The armada 385 SoC is a superset of the armada 380 SoC (with more CPUs
and more PCIe slots). So this patch replaces the use of
"marvell,armada38x" by the "marvell,armada380" string.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1403533011-21339-1-git-send-email-gregory.clement@free-electrons.com
Acked-by: Andrew Lunn <andrew@lunn.ch>
Cc: <stable@vger.kernel.org> # v3.15+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Commit eeb845459a
("ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id")
added phy-connection-type properties to ethernet PHY nodes.
Actually, the property has to be set for the ethernet port node instead.
Fix it by moving the corresponding properties to the correct nodes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1403555115-13111-1-git-send-email-sebastian.hesselbarth@gmail.com
Fixes: eeb845459a72: ('ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id')
Cc: <stable@vger.kernel.org> # v3.16+
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds records for two IR controllers on A20
Signed-off-by: Alexander Bersenev <bay@hackerdom.ru>
Signed-off-by: Alexsey Shestacov <wingrime@linux-sunxi.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- Use GPIO for card CD/WP on imx51-babbage and eukrea-mbimxsd51,
because controller base CD/WP is not working in esdhc driver due to
runtime PM support
- A couple of random ventana gw5xxx board fixes
- Add IMX_IPUV3_CORE back to defconfig, which gets lost when moving
IPUv3 driver out of staging tree
- Fix enet/fec clock selection on imx6sl
- Fix display node on imx53-m53evk board
- A couple of Cubox-i updates from Russell, which were omitted from
the merge window due to dependency
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Merge tag 'imx-fixes-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes
Pull "i.MX fixes for 3.16" from Shawn Guo:
- Use GPIO for card CD/WP on imx51-babbage and eukrea-mbimxsd51,
because controller base CD/WP is not working in esdhc driver due to
runtime PM support
- A couple of random ventana gw5xxx board fixes
- Add IMX_IPUV3_CORE back to defconfig, which gets lost when moving
IPUv3 driver out of staging tree
- Fix enet/fec clock selection on imx6sl
- Fix display node on imx53-m53evk board
- A couple of Cubox-i updates from Russell, which were omitted from
the merge window due to dependency
* tag 'imx-fixes-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: dts: imx51-eukrea-mbimxsd51-baseboard: unbreak esdhc.
ARM: dts: imx51-babbage: Fix esdhc setup
ARM: dts: mx5: Move the display out of soc {} node
ARM: dts: mx5: Fix IPU port node placement
ARM: imx_v6_v7_defconfig: Enable CONFIG_IMX_IPUV3_CORE
ARM: dts: hummingboard/cubox-i: move usb otg configuration to platform level
ARM: dts: cubox-i: add support for PWM-driven front panel LED
ARM: dts: imx6: ventana: correct gw52xx sgtl5000 clock source
ARM: dts: imx6qdl-gw5xxx: Fix Linear Technology vendor prefix
ARM: dts: imx6: ventana: fix include typo
ARM: dts: imx6sl: correct the fec ipg clock source
ARM: imx6sl: add missing enet clock for imx6sl
- use WFI macro in platform_do_lowpower because exynos cpuhotplug
includes a hardcoded WFI instruction and it causes compile error
in Thumb-2 mode.
- fix GIC reg sizes for exynos4 SoCs
- remove reset timer counter value during boot and resume for mct
to fix a big jump in printk timestamps
- fix pm code to check cortex-A9 for another exynos SoCs
- don't rely on firmware's secondary_cpu_start for mcpm
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Merge tag 'samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes
Merge Samsung fixes for 3.16 from Kukjin Kim:
- use WFI macro in platform_do_lowpower because exynos cpuhotplug
includes a hardcoded WFI instruction and it causes compile error
in Thumb-2 mode.
- fix GIC reg sizes for exynos4 SoCs
- remove reset timer counter value during boot and resume for mct
to fix a big jump in printk timestamps
- fix pm code to check cortex-A9 for another exynos SoCs
- don't rely on firmware's secondary_cpu_start for mcpm
* tag 'samsung-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Don't rely on firmware's secondary_cpu_start for mcpm
ARM: EXYNOS: fix pm code to check for cortex A9 rather than the SoC
clocksource: exynos_mct: Don't reset the counter during boot and resume
ARM: dts: fix reg sizes of GIC for exynos4
ARM: EXYNOS: Use wfi macro in platform_do_lowpower
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Peach-pit and Peach-pi boards are almost similar, hence the DTS file
is also very similar. Sorting nodes in both these files will allow
us to figure out the difference easily.
All the node aliases are sorted in alphabetically increasing order.
There is no functional change with this patch.
Signed-off-by: Tushar Behera <tushar.b@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Peach-pi board has MAX98091 audio codec connected on HSI2C-7 bus.
Signed-off-by: Tushar Behera <tushar.b@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The following commit:
89d7e5c mmc: sdhci-esdhc-imx: add runtime pm support
has the effect of also disabling the hardware card detect
in runtime pm.
We switch to GPIO based detection to avoid this issue.
This patch is based on:
ARM: dts: imx51-babbage: Fix esdhc setup
Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Since commit 89d7e5c131 (mmc: sdhci-esdhc-imx: add runtime pm
support), controller based card detection / write protection is not
supported anymore by esdhc driver. Let's use GPIO for CD/WP on esdhc1
instead.
While at it, fix cd gpio polarity for esdhc2. This is wrong and
currently only works because the imx esdhc driver ignores the polarity.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Move the display {} node out of the soc {} node . This just aligns
the DT with other boards, there is no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The "port" node was misplaced in the original patch, therefore making
the LCD dysfunctional on this board. Fix this by moving the "port" DT
node into the "display {}" node.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
As Mainlining effort for SolidRun CuBox has been carried out on the
Engineering Sample, the board DTS was reflecting this. Actually,
SolidRun CuBox comes in three different variants:
Engineering Sample (ES), production with 1GB RAM (1G),
and production with 2GB RAM (2G).
Therefore, we base current dove-cubox.dts on to the 1G production
variant and add a ES dts to add required quirk for misrouted SDHCI
card detect on top of dove-cubox.dts. For the 2G variant we rely on
the bootloader to setup correct RAM size.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1401228006-3212-1-git-send-email-sebastian.hesselbarth@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Describe LaCie 2Big and 5Big Network v2 using device tree.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1401132591-26305-3-git-send-email-andrew@lunn.ch
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The fixes included are:
- Ethernet clocks were wrongly defined for STiH415/416 platforms
- STiH416 B2020 revision E DTS file name contained uppercase, change to
lowercase.
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Merge tag 'sti-fixes-for-v3.16-rc1' of git://git.stlinux.com/devel/kernel/linux-sti into fixes
Merge "STi: DT fixes for v3.16" from Maxime Coquelin:
Couple of DT fixes for STi platform issues discovered on V3.16-rc1.
The fixes included are:
- Ethernet clocks were wrongly defined for STiH415/416 platforms
- STiH416 B2020 revision E DTS file name contained uppercase, change to
lowercase.
* tag 'sti-fixes-for-v3.16-rc1' of git://git.stlinux.com/devel/kernel/linux-sti: (2963 commits)
ARM: stih41x: Rename stih416-b2020-revE.dts to stih416-b2020e.dts
ARM: STi: DT: Properly define sti-ethclk & stmmaceth for stih415/6
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A first set of bug fixes that didn't make it for the merge window, and
two Kconfig cleanups that still make sense at this point. Unfortunately,
one of the two cleanups caused an unintended change in the original
version, so we had to revert one part of it and do some more testing
to ensure the rest is really fine. There was also a last-minute
rebase of the patches to remove another bad commit.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"A first set of bug fixes that didn't make it for the merge window, and
two Kconfig cleanups that still make sense at this point.
Unfortunately, one of the two cleanups caused an unintended change in
the original version, so we had to revert one part of it and do some
more testing to ensure the rest is really fine. There was also a
last-minute rebase of the patches to remove another bad commit"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: use menuconfig for sub-arch menus
ARM: multi_v7_defconfig: re-enable SDHCI drivers
ARM: EXYNOS: Fix compilation warning
ARM: exynos: move sysram info to exynos.c
ARM: dts: Specify the NAND ECC scheme explicitly on Armada 385 DB board
ARM: dts: Specify the NAND ECC scheme explicitly on Armada 375 DB board
ARM: exynos: cleanup kconfig option display
misc: vexpress: fix error handling vexpress_syscfg_regmap_init()
ARM: Remove ARCH_HAS_CPUFREQ config option
ARM: integrator: fix section mismatch problem
ARM: mvebu: DT: fix OpenBlocks AX3-4 RAM size
ARM: samsung: make SAMSUNG_DMADEV optional
remoteproc: da8xx: don't select CMA on no-MMU
bus/arm-cci: add dependency on OF && CPU_V7
ARM: keystone requires ARM_PATCH_PHYS_VIRT
ARM: omap2: fix am43xx dependency on l2x0 cache
Two reasons for this rename. Firstly, it removes the camel case
convention which isn't used by any other platform and secondly it
matches the naming convention for the internal kernel, which can
become annoying when flipping between the two.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
The factory bootloader on A385-DB boards expect the ECC strength to be
4 bits over 512 bytes. Hence, we need to specify this in the devicetree,
to prevent the kernel from assuming any different ECC scheme.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1400941030-2123-3-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The factory bootloader on A375-DB boards expect the ECC strength to be
4 bits over 512 bytes. Hence, we need to specify this in the devicetree,
to prevent the kernel from assuming any different ECC scheme.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1400941030-2123-2-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The OpenBlocks AX3-4 has a non-DT bootloader. It also comes with 1GB of
soldered on RAM, and a DIMM slot for expansion.
Unfortunately, atags_to_fdt() doesn't work in big-endian mode, so we see
the following failure when attempting to boot a big-endian kernel:
686 slab pages
17 pages shared
0 pages swap cached
[ pid ] uid tgid total_vm rss nr_ptes swapents oom_score_adj name
Kernel panic - not syncing: Out of memory and no killable processes...
CPU: 1 PID: 351 Comm: kworker/u4:0 Not tainted 3.15.0-rc8-next-20140603 #1
[<c0215a54>] (unwind_backtrace) from [<c021160c>] (show_stack+0x10/0x14)
[<c021160c>] (show_stack) from [<c0802500>] (dump_stack+0x78/0x94)
[<c0802500>] (dump_stack) from [<c0800068>] (panic+0x90/0x21c)
[<c0800068>] (panic) from [<c02b5704>] (out_of_memory+0x320/0x340)
[<c02b5704>] (out_of_memory) from [<c02b93a0>] (__alloc_pages_nodemask+0x874/0x930)
[<c02b93a0>] (__alloc_pages_nodemask) from [<c02d446c>] (handle_mm_fault+0x744/0x96c)
[<c02d446c>] (handle_mm_fault) from [<c02cf250>] (__get_user_pages+0xd0/0x4c0)
[<c02cf250>] (__get_user_pages) from [<c02f3598>] (get_arg_page+0x54/0xbc)
[<c02f3598>] (get_arg_page) from [<c02f3878>] (copy_strings+0x278/0x29c)
[<c02f3878>] (copy_strings) from [<c02f38bc>] (copy_strings_kernel+0x20/0x28)
[<c02f38bc>] (copy_strings_kernel) from [<c02f4f1c>] (do_execve+0x3a8/0x4c8)
[<c02f4f1c>] (do_execve) from [<c025ac10>] (____call_usermodehelper+0x15c/0x194)
[<c025ac10>] (____call_usermodehelper) from [<c020e9b8>] (ret_from_fork+0x14/0x3c)
CPU0: stopping
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.15.0-rc8-next-20140603 #1
[<c0215a54>] (unwind_backtrace) from [<c021160c>] (show_stack+0x10/0x14)
[<c021160c>] (show_stack) from [<c0802500>] (dump_stack+0x78/0x94)
[<c0802500>] (dump_stack) from [<c021429c>] (handle_IPI+0x138/0x174)
[<c021429c>] (handle_IPI) from [<c02087f0>] (armada_370_xp_handle_irq+0xb0/0xcc)
[<c02087f0>] (armada_370_xp_handle_irq) from [<c0212100>] (__irq_svc+0x40/0x50)
Exception stack(0xc0b6bf68 to 0xc0b6bfb0)
bf60: e9fad598 00000000 00f509a3 00000000 c0b6a000 c0b724c4
bf80: c0b72458 c0b6a000 00000000 00000000 c0b66da0 c0b6a000 00000000 c0b6bfb0
bfa0: c027bb94 c027bb24 60000313 ffffffff
[<c0212100>] (__irq_svc) from [<c027bb24>] (cpu_startup_entry+0x54/0x214)
[<c027bb24>] (cpu_startup_entry) from [<c0ac5b30>] (start_kernel+0x318/0x37c)
[<c0ac5b30>] (start_kernel) from [<00208078>] (0x208078)
---[ end Kernel panic - not syncing: Out of memory and no killable processes...
A similar failure will also occur if ARM_ATAG_DTB_COMPAT isn't selected.
Fix this by setting a sane default (1 GB) in the dts file.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Tested-by: Kevin Hilman <khilman@linaro.org>
Cc: <stable@vger.kernel.org> #v3.13+
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch fixes two problems: -
1) The device tree isn't currently providing sti-ethclk which is
required by the dwmac glue code to correctly configure the ethernet
PHY clock speed.
This means depending on what the bootloader/jtag has
configured this clock to, and what switch/hub the board is plugged
into you most likely will NOT successfully negotiate a ethernet link.
2) The stmmaceth clock was associated with the wrong clock. It was
referencing the PHY clock rather than the interconnect clock which
clocks the IP.
This patch also brings us closer to not having to boot the upstream
kernel with the clk_ignore_unused parameter.
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
The configuration of the USB OTG is a platform configuration decision,
not a microsom decision. Move this configuration out to the platform
level files.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The front panel LED on the Cubox-i is driven by one of the iMX6 PWM
channels, and is wired between the PWM output and supply.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Correct the invalid clock for the sgtl5000 audio codec on the GW52xx Ventana
baseboard.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
The vendor prefix for Linear Technology should be lltc,
same as the NASDAQ symbol.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fix typo and include the right dtsi file for the gw51xx board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
imx6sl fec MDIO clock source is from ipg 66Mhz, but the currect imx6sl
device tree define it as "enet_ref" clock (50Mhz), so the patch just
corrects imx6sl dtsi fec "ipg" clock.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
This patch support PIO transfer only at this point
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds a default PCIe bus clock node.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
[horms+renesas@verge.net.au: resolved conflict]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds the device tree clock node for the PCIe Controller
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds a default PCIe bus clock node.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch adds the device tree clock node for the PCIe Controller
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
audio_clk_a/b/c are required from sound driver
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch support PIO transfer only at this point
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Define the Henninger board dependent part of the I2C2 device node.
Based on the Koelsch I2C2 device tree patch by Wolfram Sang.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
A second i2c6 node was a added by
05e234a187058ee ("ARM: shmobile: koelsch dts: Add VDD MPU regulator for
DVFS"). Merge this into the existing node.
Also shuffle i2c nodes so they are all together.
Cc: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Due to an error when merging df40f256b18300e1 ("ARM: shmobile:
lager: add i2c1, i2c2 pins") a duplicate i2c3 node.
This patch moves the duplicate and moves to old node to
be closer to the other new i2c nodes.
Cc: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Update the Lager DTS to make use of the new unified legacy
memory map where the legacy window on Lager and Koelsch
have the same size.
With this change in place the code gets aligned with the
documentation.
After update the Lager board has the following map:
Bank0: 1GiB RAM (Legacy 32-bit: 0x40000000->0x7fffffff)
Bank1: 3GiB RAM (LPAE area: 0x140000000->0x1ffffffff)
Before the update the old map looked like this:
Bank0: 2GiB RAM (Legacy 32-bit: 0x40000000->0xbfffffff)
Bank1: 2GiB RAM (LPAE area: 0x180000000->0x1ffffffff)
Tested with and without LPAE on r8a7790 Lager.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Due to an error when resolving conflicts df40f256b18300e1 ("ARM: shmobile:
lager: add i2c1, i2c2 pins") added the i2c[12]_pins nodes to the wrong
node.
This patch moves them to their correct location in the pfc node.
Cc: Ben Dooks <ben.dooks@codethink.co.uk>
Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add pinctrl definitions for i2c1 and i2c2 busses on the Lager board
to ensure these are setup correctly at initialisation time. The i2c0
and i2c3 busses are connected to single function pins.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[horms+renesas@verge.net.au: Added shmobile to patch title]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add i2c0, i2c1, i2c2 and i2c3 nodes to the Lager reference device tree as
these busses all have devices on them that can be probed even if they
are no drivers yet.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
[horms+renesas@verge.net.au: Added shmobile to title]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.
- voltage-tolerance = 1%
It reflects the tolerance for the CPU voltage defined inside the OPP
table. Due to the lack of proper OPP definition, use an arbitrary safe
value.
- clock-latency = 300 us
Approximate worst-case latency to do a full DVFS transition for every
OPPs. Due to the lack of HW information, use an arbitrary safe value.
Note: The term transition-latency will be more accurate to define this
value since the clock transition latency is not the only parameter that
will define the overall DVFS transition.
- operating-points = < kHz - uV >
List of 6 operating points. All of them are using the same voltage
since DVS is not supported in R-CAR Gen2.
- clocks
phandle to the CPU clock source. This clock source is used for all the
2 CortexA15 located inside the same cluster.
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The CA15 cluster is capable of voltage scaling. Add the regulator
in the i2c6 node, to allow the generic CPUFreq driver to use it.
Enable the i2c6 pin mux and the device node as well since the
da9210 is connected to that bus.
Note: In R-CAR Gen2, each frequency is using the same voltage,
and DVS control is not used. Therefore, this patch set the
voltage(Vmin/Vmax) to 1000mv.
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.
- voltage-tolerance = 1%
It reflects the tolerance for the CPU voltage defined inside the OPP
table. Due to the lack of proper OPP definition, use an arbitrary safe
value.
- clock-latency = 300 us
Approximate worst-case latency to do a full DVFS transition for every
OPPs. Due to the lack of HW information, use an arbitrary safe value.
Note: The term transition-latency will be more accurate to define this
value since the clock transition latency is not the only parameter that
will define the overall DVFS transition.
- operating-points = < kHz - uV >
List of 6 operating points. All of them are using the same voltage
since the valid Vmin voltage is not documented in the HW spec.
- clocks
phandle to the CPU clock source. This clock source is used for all the
4 CortexA15 located inside the same cluster.
Signed-off-by: Benoit Cousson <bcousson+renesas@baylibre.com>
[gaku.inami.xw@bp.renesas.com: Change the setting of OPPs for ES2.0]
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The CA15 cluster is capable of voltage scaling. Add the regulator
in the i2c3 node, to allow the generic CPUFreq driver to use it.
Enable the i2c3 pin mux and the device node as well since the
da9210 is connected to that bus.
Note: In R-CAR Gen2, each frequency is using the same voltage,
and DVS control is not used. Therefore, this patch set the
voltage(Vmin/Vmax) to 1000mv.
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
[gaku.inami.xw@bp.renesas.com: Changes Vmin for disabling DVS]
Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Initialise SCIF devices using DT when booting marzen
using multiplatform.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Shawn Guo