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2 Commits

Author SHA1 Message Date
Jean-Christophe PLAGNIOL-VILLARD f363c407b4 ARM: at91: make sdram/ddr register base soc independent 
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
 2012-02-23 14:57:56 +01:00
Jean-Christophe PLAGNIOL-VILLARD 14f991a730 ARM: at91: Fix at91sam9g45 and at91cap9 reset 
As on the other sam9 we need to cleanly shutdown the DDRAM before rebooting.

On those SoC the SDRAM/DDRAM controller is different. So, the assembly code
ends up being not cleanly combined with previous at91sam9_alt_restart function.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
 2012-01-20 17:22:50 +01:00