Cleanup GPIO IRQ enable/disable handling by removing SoC-specific
Also split enable/disable IRQ into separate functions for better
readability and also facilitate potentially moving to generic irq_chip
in the future.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Cleanup IRQ status handling by passing IRQ status register offsets
via platform data.
Cleans up clearing of GPIO IRQ status and GPIO ISR handler.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Add register offset fields to GPIO platform_data for registers.
This patch adds registers that control direction, input and output
data. Using these register offsets in the common driver allows
removal of #ifdefs and greatly improves readability.
Also create dedicated data out functions: one for banks with dedicated
set/clear registers, and another for banks with a single mask
register.
Signed-off-by: Kevin Hilman <khilman@ti.com>
The get_gpio_index() function, littered with cpu_is_* checks can be easily
replaced by using bitops based on the GPIO bank width. Do so.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Rather than having a file-global bank_width variable, move it into
struct gpio_bank so it can be bank-specific. Note the bank width
is already passed per-bank via platform_data, so current code would
be incorrect if any banks had different width.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Remove the OMAP1 #ifdef and MPUIO special case for _clear_gpio_irqbank()
The MPUIOs do not need a register access to ack/clear the IRQ status,
since reading the IRQ status clears it. In addition, the MPUIO
irq_chip has an empty ack method, so _clear_gpio_irqbank() is never
used for MPUIOs.
Signed-off-by: Kevin Hilman <khilman@ti.com>
In commit 78a1a6d341 (ARM: OMAP4: Update
the GPIO support) braces were mistakenly added to included the
register read-back inside the cpu_is_* checking.
Remove the braces, ensuring that a register read-back is done, even
when the IRQSTATUS2 register is not written.
Note that the register read-back might be IRQSTATUS1 or IRQSTATUS2
depending on the CPU, but a read-back of any register in that region
will cause a flush of the posted writes.
Signed-off-by: Kevin Hilman <khilman@ti.com>
If gpio pins from bank[2-5] are marked as wakeup enable and if the wake is
through gpio IO pad wakeup, then that wakeup gpio interrupt is lost.
In the current implementation, GPIO driver stores the context of DATAIN of
all the gpio in the bank. During GPIO resuming, it checks DATAIN with wakeup
enabled pins of gpio bank. If there is status change, then manually toggle
GPIO_LEVELDETECT to generate pseudo interrupt.
Reported-by: Philippe Mazet <p-mazet@ti.com>
Tested-by: Philippe Mazet <p-mazet@ti.com>
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
_set_gpio_triggering uses read-modify-write on bank registers,
lock bank->lock around all calls to it to prevent register
corruption if two cpus access gpios in the same bank at the
same time.
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Setting the IRQWAKEN bit was overwriting previous IRQWAKEN bits,
causing only the last bit set to take effect, resulting in lost
wakeups when the GPIO controller is in idle.
Replace direct writes to IRQWAKEN with MOD_REG_BIT calls to
perform a read-modify-write on the register.
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
WARNING: arch/arm/plat-omap/built-in.o(.devinit.text+0x46c): Section mismatch in reference from the function omap_gpio_probe() to the function .init.text:omap_gpio_chip_init()
The function __devinit omap_gpio_probe() references
a function __init omap_gpio_chip_init().
If omap_gpio_chip_init is only used by omap_gpio_probe then
annotate omap_gpio_chip_init with a matching annotation.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Kevin Hilman