Commit Graph

46 Commits

Author SHA1 Message Date
Xing Zheng 8cbb59af7e arm64: dts: rockchip: add rockchip,grf property for RK3399 PMUCRU/CRU
The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13 20:03:15 +01:00
Shawn Lin 59cf70be5b arm64: dts: rockchip: add aspm-no-l0s for rk3399
Per the discussion of bug fix[1], we now actually
leaves the default clock choice for pcie phy is
derived from 24MHz OSC to guarantee the least BER.
So let's add aspm-no-l0s here and folks could delete
this property from their dts.

[1] https://patchwork.kernel.org/patch/9470519/
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-13 12:03:55 +01:00
Shawn Lin 712fa17772 arm64: dts: rockchip: add max-link-speed for rk3399
Per the errata of TRM, rk3399 won't support gen2 from
now on, so let's set max-link-speed to 1 in order not
to doing training for gen2.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-06 10:09:40 +01:00
William wu b5d1c57299 arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

The u2phy clock flow like this:
===
      u2phy ________________
           |                |    |-----> UTMI_CLK ---------> | EHCI |
OSC_24M ---|---> PHY_PLL----|----|
           |________^_______|    |-----> 480M_CLK ---|G|---> | USBPHY_480M_SRC| ----> USBPHY_480M for SoC
                    |
                    |
                   GRF
===

Signed-off-by: William wu <wulf@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02 14:25:10 +01:00
Brian Norris 8742466a43 arm64: dts: rockchip: add rk3399 eDP HPD pinctrl
We haven't enabled eDP support yet, but we might as well describe the
pin now.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02 14:25:10 +01:00
Brian Norris 647cea2e68 arm64: dts: rockchip: add rk3399 thermal_zones phandle
We're going to need to amend this table in board files.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-01-02 14:25:10 +01:00
Linus Torvalds 482c3e8835 ARM: 64-bit DT updates for v4.10
A couple of interesting new SoC platforms are now supported, these are
 the respective DTS sources:
 
 - Samsung Exynos5433 mobile phone platform, including an (almost) fully
   supported phone reference board.
 - Hisilicon Hip07 server platform and D05 board, the latest iteration
   of their product line, now with 64 Cortex-A72 cores across two
   sockets.
 - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product
   line, used in Android tablets and ultra-cheap development boards
 - NXP LS1046A Communication processor, improving on the earlier LS1043A
   with faster CPU cores
 - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810)
   mobile phone SoCs
 - Early support for the Nvidia Tegra Tegra186 SoC
 - Amlogic S905D is a minor variant of their existing Android consumer
   product line
 - Rockchip PX5 automotive platform, a close relative of their popular
   rk3368 Android tablet chips
 
 Aside from the respective evaluation platforms for the above
 chips, there are only a few consumer devices and boards added
 this time:
 
 - Huawei Nexus 6P (Angler) mobile phone
 - LG Nexus 5x (Bullhead) mobile phone
 - Nexbox A1 and A95X Android TV boxes
 - Pine64 development board based on Allwinner A64
 - Globalscale Marvell ESPRESSOBin community board based on Armada 3700
 - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive  board
 
 For the existing platforms, we get bug fixes and new peripheral support
 for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom, Rockchip, Berlin,
 and ZTE.
 
 Conflicts:
 - Documentation/devicetree/bindings/arm/shmobile.txt: a
   rename/add conflict, keep both modifications and maintain
   alphabetical ordering.
 - arch/arm64/boot/dts/*/*.dtsi: nodes were added in netdev,
   mmc and clk, keep both sides in each case.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIVAwUAWFMYq2CrR//JCVInAQJ38BAAzKC2AmZw2U5t8de1RuC7OOefHnWxzXaI
 hpH5sLLIF10D52VrztqG2EauQWa2K0OYpkO5Up+d8WVdRm6dL2Y9wTMOhdadqWmb
 zPthdGuSpI6yRiST51Umr1pvt5rm/0KYMAiP1B1ySIWCeOyxFmm9er6ZU3By6kbx
 bbXEzY2vs22GJ3+rNxYOVGm1hlhgBaoYnkth2AIXwiGt5OUn4yDs/17+WqNZlg7S
 Bj9vdvn+A/IeiaGZGRUn8J2HxUCeIxJzwntKJyoRfVu6BH+qlrPLhFh/N3Ttzb+3
 Xjh+uQgikEp/2pkaq6oNJLATOXCAL8+UIAL+ZMJ1jiVI7Q1WBQITj14QgNgbkupX
 1Bg25eS3I3HSmOg1tnUeEzF3N3hK8jlb9lA0HZm9m6RuegFsVIGHfte7xOdRbZki
 dHAVy0xAoBPoXWnUfoekc1/L4AfsBh57GfbIBhf+xZs2eKp7Jw22eVwc9YsdDpc1
 3s6aEbAsQWU7IgSWWEOJMi/q7Z6By7db3dIGLqtwszVvqzjkcszXQZSxjaOHlseK
 j6Ci6yQ3UeG05QviySFyVsOxfHrL5SczYexsbkKE/kXfQZXR7x+GQzjm/BwYvEkO
 Q+gHAbGBI5IM6hTBDLnHkn+WkXYk3EhyTcFykxs2ykJhWsOd9ReBuCTxr4Wey40U
 Q80HYHv/leY=
 =geT0
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "A couple of interesting new SoC platforms are now supported, these are
  the respective DTS sources:

   - Samsung Exynos5433 mobile phone platform, including an (almost)
     fully supported phone reference board.
   - Hisilicon Hip07 server platform and D05 board, the latest iteration
     of their product line, now with 64 Cortex-A72 cores across two
     sockets.
   - Allwinner A64 SoC, the first 64-bit chip from their "sunxi" product
     line, used in Android tablets and ultra-cheap development boards
   - NXP LS1046A Communication processor, improving on the earlier
     LS1043A with faster CPU cores
   - Qualcomm MSM8992 (Snapdragon 808) and MSM8994 (Snapdragon 810)
     mobile phone SoCs
   - Early support for the Nvidia Tegra Tegra186 SoC
   - Amlogic S905D is a minor variant of their existing Android consumer
     product line
   - Rockchip PX5 automotive platform, a close relative of their popular
     rk3368 Android tablet chips

  Aside from the respective evaluation platforms for the above chips,
  there are only a few consumer devices and boards added this time:

   - Huawei Nexus 6P (Angler) mobile phone
   - LG Nexus 5x (Bullhead) mobile phone
   - Nexbox A1 and A95X Android TV boxes
   - Pine64 development board based on Allwinner A64
   - Globalscale Marvell ESPRESSOBin community board based on Armada 3700
   - Renesas "R-Car Starter Kit Pro" (M3ULCB) low-cost automotive board

  For the existing platforms, we get bug fixes and new peripheral
  support for Juno, Renesas, Uniphier, Amlogic, Samsung, Broadcom,
  Rockchip, Berlin, and ZTE"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (168 commits)
  arm64: dts: fix build errors from missing dependencies
  ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible
  ARM64: dts: meson-gxl: Add support for Nexbox A95X
  ARM64: dts: meson-gxm: Add support for the Nexbox A1
  ARM: dts: artpec: add pcie support
  arm64: dts: berlin4ct-dmp: add missing unit name to /memory node
  arm64: dts: berlin4ct-stb: add missing unit name to /memory node
  arm64: dts: berlin4ct: add missing unit name to /soc node
  arm64: dts: qcom: msm8916: Add ddr support to sdhc1
  arm64: dts: exynos: Enable HS400 mode for eMMC for TM2
  ARM: dts: Add xo to sdhc clock node on qcom platforms
  ARM64: dts: Add support for Meson GXM
  dt-bindings: add rockchip RK1108 Evaluation board
  arm64: dts: NS2: Add PCI PHYs
  arm64: dts: NS2: enable sdio1
  arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash
  arm64: tegra: Add NVIDIA P2771 board support
  arm64: tegra: Enable PSCI on P3310
  arm64: tegra: Add NVIDIA P3310 processor module support
  arm64: tegra: Add GPIO controllers on Tegra186
  ...
2016-12-15 15:58:28 -08:00
Linus Torvalds 9465d9cc31 Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner:
 "The time/timekeeping/timer folks deliver with this update:

   - Fix a reintroduced signed/unsigned issue and cleanup the whole
     signed/unsigned mess in the timekeeping core so this wont happen
     accidentaly again.

   - Add a new trace clock based on boot time

   - Prevent injection of random sleep times when PM tracing abuses the
     RTC for storage

   - Make posix timers configurable for real tiny systems

   - Add tracepoints for the alarm timer subsystem so timer based
     suspend wakeups can be instrumented

   - The usual pile of fixes and updates to core and drivers"

* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
  timekeeping: Use mul_u64_u32_shr() instead of open coding it
  timekeeping: Get rid of pointless typecasts
  timekeeping: Make the conversion call chain consistently unsigned
  timekeeping_Force_unsigned_clocksource_to_nanoseconds_conversion
  alarmtimer: Add tracepoints for alarm timers
  trace: Update documentation for mono, mono_raw and boot clock
  trace: Add an option for boot clock as trace clock
  timekeeping: Add a fast and NMI safe boot clock
  timekeeping/clocksource_cyc2ns: Document intended range limitation
  timekeeping: Ignore the bogus sleep time if pm_trace is enabled
  selftests/timers: Fix spelling mistake "Asyncrhonous" -> "Asynchronous"
  clocksource/drivers/bcm2835_timer: Unmap region obtained by of_iomap
  clocksource/drivers/arm_arch_timer: Map frame with of_io_request_and_map()
  arm64: dts: rockchip: Arch counter doesn't tick in system suspend
  clocksource/drivers/arm_arch_timer: Don't assume clock runs in suspend
  posix-timers: Make them configurable
  posix_cpu_timers: Move the add_device_randomness() call to a proper place
  timer: Move sys_alarm from timer.c to itimer.c
  ptp_clock: Allow for it to be optional
  Kconfig: Regenerate *.c_shipped files after previous changes
  ...
2016-12-12 19:56:15 -08:00
Brian Norris e6186820a7 arm64: dts: rockchip: Arch counter doesn't tick in system suspend
The "arm,no-tick-in-suspend" property was introduced to note
implementations where the system counter does not quite follow the ARM
specification that it "must be implemented in an always-on power
domain".

Particularly, RK3399's counter stops ticking when we switch from the
24MHz clock to the 32KHz clock in low-power suspend, so let's mark it as
such.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-11-21 11:15:01 +01:00
William Wu fe7f2de1c6 arm64: dts: rockchip: add usb2-phy otg-port support for rk3399
Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can
be used for USB2.0 part of USB3.0 OTG controller.

Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-15 16:22:24 +01:00
Elaine Zhang 1bc60beec0 arm64: dts: rockchip: add pd_sd power-domain node for rk3399
Add the sd power-domain, its qos area and assign it to the
sdmmc device node.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-14 16:20:44 +01:00
Elaine Zhang a1907df27e arm64: dts: rockchip: add eMMC's power domain support for rk3399
Control power domain for eMMC via genpd to reduce power consumption.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-14 16:20:23 +01:00
Jeffy Chen 2afc1db0c5 arm64: dts: rockchip: add gmac needed pclk for rk3399 pd
This patch fixes that sometimes hang at start-up time of the system.
As the below log:
...
[   11.136543] calling  pm_genpd_debug_init+0x0/0x60 @ 1
[   11.141602] initcall pm_genpd_debug_init+0x0/0x60 returned 0 after 11 usecs
[   11.148558] calling  genpd_poweroff_unused+0x0/0x84 @ 1
<hang>

In some cases, the rk3399 should turn off the gmac power domain to save
power if some boards didn't register the gmac device node for rk3399.
Then, rk3399 need to make sure the gmac's pclk enabled if we need
operate the gmac power domain. (Due to the NOC had enabled always)

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-14 15:33:36 +01:00
Shawn Lin 4d3222f707 arm64: dts: rockchip: add three new resets for rk3399 PCIe controller
pm_rst, aclk_rst and pclk_rst should be controlled by driver, so we
need to add these three resets for PCIe controller.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
2016-11-10 11:14:46 -06:00
Jaehoon Chung c49590691f arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
In drivers/mmc/core/host.c, there is "max-freqeuncy" property.
It should be same behavior, So Use the "max-frequency" instead of
"clock-freq-min-max".

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-09 15:08:55 +01:00
Ziyuan Xu 0d326927f9 arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399
There is a 'cpu-id' field in efuse, export it for other drivers
reference.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-02 00:28:39 +01:00
Chris Zhong 06ad4b2fad arm64: dts: rockchip: add powerdomain for typec on rk3399
The tcpc power domain will try to power up/down the power of Type-C PHY.
Hence, we need control it in Type-C PHY driver with the pm_runtime helper.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-10-16 02:42:59 +02:00
Chris Zhong f606193a10 arm64: dts: rockchip: add Type-C phy for RK3399
There are 2 Type-C phy on RK3399, they are almost same, except the
address of register. They support USB3.0 Type-C and DisplayPort1.3
Alt Mode on USB Type-C. Register a phy, supply it to USB3 controller
and DP controller.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-07 20:20:08 +02:00
Roger Chen eb3a6a6a9e arm64: dts: rockchip: add the gmac needed node for rk3399
The RK3399 GMAC Ethernet Controller provides a complete Ethernet interface
from processor to a Reduced Media Independent Interface (RMII) and Reduced
Gigabit Media Independent Interface (RGMII) compliant Ethernet PHY.

This patch adds the related needed device information.
e.g.: interrupts, grf, clocks, pinctrl and so on.

The full details are in [0].

[0]:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt

Signed-off-by: Roger Chen <roger.chen@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-07 20:10:34 +02:00
Caesar Wang 6840eb0d76 arm64: dts: rockchip: support the pmu node for rk3399
This patch adds to enable the ARM Performance Monitor Units for rk3399.
ARM cores often have a PMU for counting cpu and cache events like cache
misses and hits.

This uses the new interrupt-partition mechanism to allow the two pmu
instances to use the per-cpu interrupt.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-06 01:02:21 +02:00
Caesar Wang 210bbd38bb arm64: dts: rockchip: change all interrupts cells to 4 on rk3399 SoCs
Add the interrupts cells value for 4, and the 4th cell is zero.

Due to the doc[0] said:" the system requires describing PPI affinity,
then the value must be at least 4"
The 4th cell is a phandle to a node describing a set of CPUs this
interrupt is affine to. The interrupt must be a PPI, and the node
pointed must be a subnode of the "ppi-partitions" subnode. For
interrupt types other than PPI or PPIs that are not partitionned,
this cell must be zero. See the "ppi-partitions" node description
below.

[0]:
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-06 01:02:11 +02:00
Caesar Wang 4a3a3d32c7 arm64: dts: rockchip: add the tcpc for rk3399 power domain
The tcpc is the Type C Port Controller and Type C Port Delivery (tcpd)
is part of it, we haven't used them now, add it to save power consumption.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-05 00:10:44 +02:00
Finley Xiao b7ee3b2742 arm64: dts: rockchip: add efuse0 device node for rk3399
Add a efuse0 node in the device tree for the ARM64 rk3399 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-02 17:19:42 +02:00
Shawn Lin 85aaa57459 arm64: dts: rockchip: add the PCIe controller support for RK3399
This patch introduces PCIe support found on RK3399 platform,
and specify phys phandle for it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-02 17:16:31 +02:00
Shawn Lin 29a0be1c9e arm64: dts: rockchip: add the PCIe PHY for RK3399
This patch adds PCIe node for RK3399 to support
PCIe controller.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-02 17:15:59 +02:00
Caesar Wang d43c97a515 arm64: dts: rockchip: add the gmac power domain on rk3399
This patch adds the gmac ppower-domain to save power consumption
by letting the driver core handle the power-domain so we can
save power on boards not needing Ethernet.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-02 12:57:01 +02:00
Douglas Anderson a8bcaea78f arm64: dts: rockchip: Add pinctrl entry for 32k clock on rk3399
On some rk3399 boards GPIO0_A0 is hooked up to a 32 kHz clock.  This can
be used as the source for various clocks in the system.

Add a pinmux so boards can get this pin properly configured.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-09-02 12:52:31 +02:00
Shunqian Zheng bb4b6201d2 arm64: dts: rockchip: set to CCI clock of RK3399 to 600M
Per testing, this can reduce the memory latency and d8 gets
better scores.

Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-26 13:38:46 +02:00
Xing Zheng 0895b3a8fd arm64: dts: rockchip: fix the address map for WDT0 and WDT1
Due to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff840000

And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-26 13:38:37 +02:00
Caesar Wang fe99621515 arm64: dts: rockchip: add the saradc for rk3399
This patch adds saradc needed information on rk3399 SoCs.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-24 11:29:07 +02:00
Frank Wang 103e9f8537 arm64: dts: rockchip: add usb2-phy support for rk3399
Add usb2-phy nodes and specify phys phandle for ehci.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-17 11:47:56 +02:00
Elaine Zhang 807a2371d3 arm64: dts: rockchip: add the power domain node for rk3399
In order to meet low power requirements, a power management unit (PMU) is
designed for controlling power resources in RK3399. The RK3399 PMU is
dedicated for managing the power of the whole chip.

1. add pd node for RK3399 Soc
2. create power domain tree
3. add qos node for domain

From the DT/binds and driver can get more detail information:
The driver:
        drivers/soc/rockchip/pm_domains.c
The document:
        Documentation/devicetree/bindings/soc/rockchip/power_domain.txt

Note:
As the TRM lists many voltage domains and power domains, then this patch
adds some domains for driver. Due to some domains
(e.g. emmc, usb, core)...We can't turned off it on
bootup, or says some device driver can't handle the power domain enough.
Maybe We will add more other domains in the future or later.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-08-08 10:57:04 +02:00
Linus Torvalds ed780686de ARM: 64-bit DT updates for v4.8
Just as the 32-bit contents, the 64-bit device tree branch also contains
 a number of additions this release cycle.
 
 New platforms:
  - LG LG1313
  - Mediatek MT6755
  - Renesas r8a7796
  - Broadcom 2837
 
  Other platforms with larger updates are:
  - Nvidia X1 platforms (USB 3.0, regulators, display subsystem)
  - Mediatek MT8173 (display subsystem added)
  - Rockchip RK3399 (a lot of new peripherals)
  - ARM Juno reference implementation (SCPI power domains, coresight, thermal)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJXnnlFAAoJEIwa5zzehBx3vvQQAJRlQ8JtQYzPyyiBGn/F8rbr
 JFf2clMobYwPBQGFHQOC2WGEAZEhTMcc0exzfLp4Iu+9wsZW28KQCZvZHk3Gn60/
 U/e9/V3xFlCFudgOPoxrUzil1XWG6hxI6PMetn2+WwBa3PziZQczXiJu1iWWP1HE
 XSusuE9SL7w0EfBDtJcbdZPQC2Ciq3mzBB7wLEE0Dblz4WgZuE74wWMVpjtb9bhV
 sWtveX45J/UwzUkeIrErwhSzDRCD4D/Vw6p/1gcmCQfY+LFsLs6/QUJbglThyhSJ
 xo72jc6W2Y+FvX4XgFgjofS57mgfdwgmCSY0OhA7FRCWxbRllkzQrgE5JmPAP0J8
 SwfhNe7uH0onuSmiaaTPdcVy6lx572keN6LWjxdW08/qSsDY+TxdxG/zVP3C0lcZ
 Al5NgwP9oViUpSOLkzwmlZvva+8WBLzDLQjMfduX/JsTUubJSVht+34XS2o7uE9D
 15HkqdHX7tQ6GOcOoERr2bKVGkG2MKxMgFcwmILPOARcqKAbxJ/Sq97axJ3Hqdzg
 GLcPV3YKgQ005vhJfswUN1jjKQbjvOY+aAhCekfs/xMyJz+K9IzkRPxKuVDt/1Tg
 J6X5yqk12yRiCvfpHUeFs3LTHLsocX3dM8wevkEacNdEZ7hXyhBzkAgZKjt7ujJ/
 NQtezrdMW/ZRNq7CoS4z
 =g0hR
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull 64-bit ARM DT updates from Olof Johansson:
 "Just as the 32-bit contents, the 64-bit device tree branch also
  contains a number of additions this release cycle.

  New platforms:
   - LG LG1313
   - Mediatek MT6755
   - Renesas r8a7796
   - Broadcom 2837

  Other platforms with larger updates are:
   - Nvidia X1 platforms (USB 3.0, regulators, display subsystem)
   - Mediatek MT8173 (display subsystem added)
   - Rockchip RK3399 (a lot of new peripherals)
   - ARM Juno reference implementation (SCPI power domains, coresight,
     thermal)"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits)
  arm64: tegra: Enable HDMI on Jetson TX1
  arm64: tegra: Add sor1_src clock
  arm64: tegra: Add XUSB powergates on Tegra210
  arm64: tegra: Add DPAUX pinctrl bindings
  arm64: tegra: Add ACONNECT bus node for Tegra210
  arm64: tegra: Add audio powergate node for Tegra210
  arm64: tegra: Add regulators for Tegra210 Smaug
  arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
  arm64: tegra: Enable XUSB controller on Jetson TX1
  arm64: tegra: Enable debug serial on Jetson TX1
  arm64: tegra: Add Tegra210 XUSB controller
  arm64: tegra: Add Tegra210 XUSB pad controller
  arm64: tegra: Add DSI panel on Jetson TX1
  arm64: tegra: p2597: Add SDMMC power supplies
  arm64: tegra: Add PMIC support on Jetson TX1
  Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock"
  arm64: dts: hi6220: Add pl031 RTC support
  arm64: dts: r8a7796/salvator-x: Enable watchdog timer
  arm64: dts: r8a7796: Add RWDT node
  arm64: dts: r8a7796: Use SYSC "always-on" PM Domain
  ...
2016-08-01 18:47:01 -04:00
Thomas Gleixner 3d93f42d44 Merge branch 'clockevents/4.8' of http://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull the clockevents/clocksource tree from Daniel Lezcano:

  - Convert the clocksource-probe init functions to return a value in order to
    prepare the consolidation of the drivers using the DT. It is a big patchset
    but went through 01.org (kbuild bot), linux next and kernel-ci (continuous
    integration) (Daniel Lezcano)

  - Fix a bad error handling by returning the right value for cadence_ttc
    (Christophe Jaillet)

  - Fix typo in the Kconfig for the Samsung pwm (Alexandre Belloni)

  - Change functions to static for armada-370-xp and digicolor (Ben Dooks)

  - Add support for the rk3399 SoC timer by adding bindings and a slight
    change in the base address. Take the opportunity to add the DYNIRQ flag
    (Huang Tao)

  - Fix endian accessors for the Samsung pwm timer (Matthew Leach)

  - Add Oxford Semiconductor RPS Dual Timer driver (Neil Armstrong)

  - Add a kernel parameter to swich on/off the event stream feature of the arch
    arm timer (Will Deacon)
2016-07-07 15:41:13 +02:00
Huang Tao 1e8567d53d arm64: dts: rockchip: Add rktimer device node for rk3399
Add a 'rktimer' node in the device treee for the ARM64 rk3399 SoC.

Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2016-06-28 10:17:09 +02:00
Douglas Anderson 5d26ad9cfb arm64: dts: rockchip: add ap_pwroff and ddrio_pwroff pins for rk3399
There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff.
Let's add the definition of these two pins to rk3399's main dtsi file so
that boards can use them.

These two pins are similar to the global_pwroff and ddrio_pwroff pins in
rk3288 and are expected to be used in the same way: boards will likely
want to configure these pinctrl settings in their global pinctrl hog
list.

Note that on rk3288 there were two additional pins in the "sleep"
section: "ddr0_retention" and "ddr1_retention".  On rk3288 designs these
pins appeared to actually route from rk3288 back to rk3288.  Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-27 01:07:40 +02:00
Douglas Anderson ed388cdd2e arm64: dts: rockchip: Provide emmcclk to PHY for rk3399
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY.  Hook things up in the main rk3399 dtsi file.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-22 18:24:33 +02:00
Douglas Anderson 64e3481c8a arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component.  Specify the syscon to enable that.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-22 18:24:05 +02:00
David Wu 69e5a8fe8c arm64: dts: rockchip: add i2c nodes for rk3399
We've got 9 (count em!) i2c controllers on rk3399, some of which are in
the PMU power domain and some of which are normal peripherals.  Add them
all to the main rk3399 dtsi file so future patches can turn them on in
the board dts files.

Note: by default we try to set the i2c clock rate to 200 MHz so that we
can achieve good i2c functional clock rates.  200 MHz gives us the
ability to make very close to 100 kHz / 400 kHz / 1 MHz rates.  If
boards want to tune clock rates further they can always override.
Possibly boards could want to tune this if:
- they wanted to save an infinitesimal amount of power and they knew
  their i2c bus was slow anyway.  Since we gate the functional clock
  when the i2c bus is not active, power savings would only be while i2c
  transfers were happening and probably won't be very big anyway.
- they wanted to eek out a bit more speed by carefully tuning the source
  clock to make divisions work out perfectly, accounting for the rise /
  fall time measured on an actual board.

Note also that we still request 200 MHz for the PMU i2c busses even
though we expect that we won't make that exactly (currently PPLL is 676
MHz which gives us 169 MHz).

Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[dianders: wrote desc; put in assigned-clocks; reordered nodes]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-18 14:00:23 +02:00
Caesar Wang 95c27ba7bd arm64: dts: rockchip: add thermal nodes for rk3399 SoCs
This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal
data is including the cpu and gpu sensor zone node.

The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings.
The thermal zone node must contain, apart from its own properties, one
sub-node containing trip nodes and one sub-node containing all the zone
cooling maps.

The following is the parameter is introduced:
* polling-delay:
The maximum number of milliseconds to wait between polls

* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.

* trips:
A sub-node which is a container of only trip point nodes required to
describe the thermal zone.

* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.

* cooling-device:
A phandle of a cooling device with its specifier, referring to which
cooling device is used in this cooling specifier binding. In the cooling
specifier, the first cell is the minimum cooling state and the second cell
is the maximum cooling state used in this map.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-06-06 13:02:00 +02:00
Masahiro Yamada 15b7cc78f0 arm64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 2
Tree-wide replacement was done by commit 2ef7d5f342 (ARM, ARM64:
dts: drop "arm,amba-bus" in favor of "simple-bus"), but we have some
new users of "arm,amba-bus" at Linux 4.7-rc1.  Eliminate them now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-03 12:13:15 -07:00
Heiko Stuebner 6d0e3a45de arm64: dts: rockchip: add rk3399 io-domain core nodes
Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Brian Norris b4e87c097c arm64: dts: rockchip: add sdhci/emmc for rk3399
Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to
200 MHz, to support all supported timing modes.

Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably
have a compliant Arasan controller, but let's have a rockchip property
as the canonical backup/precautionary measure. Per Heiko's previous
suggestion, let's not clutter the arasan doc with it.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Brian Norris 1675926249 arm64: dts: rockchip: make rk3399's grf a "simple-mfd"
Per the examples in
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt, we need the
grf node to be a simple-mfd in order to properly enumerate child devices
like our eMMC PHY.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>

[directly mimic for the pmugrf, which will need the same change later
and there is no need to pollute commit history with another patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Xing Zheng a09906cd8c arm64: dts: rockchip: assign default rates for core rk3399 clocks
These clocks are all core clocks used by many blocks/peripherals, many
of whose drivers don't set their clock rates at all. Let's assign
reasonable default clock rates for these core clocks, so that these
peripherals get something reasonable by default, and also so that if
child devices want to select a clock rate themselves, their muxes have
some reasonable parent clock rates to branch off of (rather than just
the boot-time defaults).

This helps the eMMC PHY, for one, to get a reasonable ACLK rate.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-05-30 09:43:30 +02:00
Jianqun Xu f048b9a4d4 arm64: dts: rockchip: add core dtsi file for RK3399 SoCs
This patch adds core dtsi file for Rockchip RK3399 SoCs.

The RK3399 has big/little architecture, which needs a separate
node for the PMU of each microarchitecture, for now it missing
the pmu node since the old one could not work well.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-04-28 22:25:38 +02:00